EL 511

VLSI Design
Instructor:
Mazad S. Zaveri
Faculty Block 4, Room 4206
Email: mazad_zaveri@daiict.ac.in
http://intranet.daiict.ac.in/~mazad_zaveri/

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EL 511 VLSI Design

MOS Capacitor with N-type substrate

- Under Various Bias Conditions

N-type substrate (or body)

In P-channel MOSFET

Depending on the applied

gate-voltage
MOS Cap could exhibit the
following conditions:

(VG < 0)

Flat band (VG = 0)

Accumulation (VG > 0)
Depletion (VG < 0)
Onset of inversion (VG = VT)
Inversion (VG < VT)

Onset of Inversion
Inversion

Depletion
VT

(VG < 0)

Flat band
Accumulation
0

Applied Volt. VG
VLSI systems work at 0 to +ve Volts. How do we give ve voltages to P-MOSFET?
EL 511 VLSI Design

Equations (according to Pierrets book)

Numerical Examples
Consider NA = 1018 cm-3
What is surface potential at inversion?

Consider ND = 1018 cm-3

What is surface potential at inversion?

Draw the approx. band diagram ?

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[ Ei (bulk ) Ei ( surface)]
q
1
F = [ Ei (bulk ) EF (bulk )]
q

S =

Ei (bulk)

kT N A P-type semiconductor
ln
F =

q ni
kT N D
ln
F =
N-type semiconductor
q
ni

S = 2F

Ei (surface)

At the depletion to inversion transition point

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EL 511 VLSI Design

Equations (from Pierret)

2KS 0

W =
S
qN A

1/ 2

2KS 0

Wmax =
2F
qN A

qN A
W
E=
KS 0

1/ 2

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EL 511 VLSI Design

MOS Cap: P-type substrate

Similar in functioning to the n-type substrate MOS Cap

But the relation of applied gate voltage to the various exhibited MOS
Cap conditions are reversed
Flat band

Onset of Inversion
Inversion
Depletion

Accumulation
0

VT

Applied Volt. VG

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EL 511 VLSI Design

P-type substrate: Flat Band Condition

When VG = 0 (No applied
bias)
Metal Fermi-level and substrate
Fermi-level are aligned
No band bending

Surface
Bulk

Assuming that the workfunction of

metal and semiconductor are equal
(ideal condition)
The characteristics of the substrate
(concentration of holes) is the same
everywhere (in the bulk and near the
surface)

Block charge diagram

No generated charges
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EL 511 VLSI Design

P-type substrate: Accumulation

When VG<0
Relatively
Metal Fermi-level goes up (relatively to substrate
Fermi-level)
For simplicity, assume that substrate Fermi-level
remains in a fixed position, because substrate is
grounded.

Band bending will be such that (near the

surface)
Ei moves away from the semiconductor Fermilevel
The concentration of holes increases at/near the
surface as compared to the bulk

Notice, oxide bands also bend, but with constant

slope

Block charge diagram

Negative charge on the gate
Leads to a positive charge (accumulation of
holes) near the surface region in the
semiconductor substrate
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EL 511 VLSI Design

P-type substrate: Depletion

When VT> VG >0
Relatively
Metal Fermi-level goes down (relative to substrate EF)

Band bending will be such that

Ei (surface) moves closer to EF
The concentration of holes decreases at/near the
surface
How?
Holes near the surface are repelled (due to applied +ve
bias on gate); i.e. electron from bulk will be attracted, and
will fill up missing bonds (holes) at acceptor atoms
Hence, these acceptor atoms become -ve charged
ionized acceptor atoms (fixed charges), and create a
depletion region.

Block charge diagram

+ve charge on the gate
Leads to a -ve charge (ionized acceptors in depletion
region) near the surface
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EL 511 VLSI Design

P-type substrate: Onset of Inversion and Inversion

When VG >= VT (VG = VT at Onset of Inversion)

Relatively
Metal Fermi-level continues to go down (relatively to substrate
EF)

Band continue to bend (same direction as VT> VG >0)

Ei (surface) crosses the EF level, and continues to move down
Hole concentration continues to decrease near the surface
Electron concentration continues to increase near the surface
When Ei(surface) = EF, we have p(surface) = n(surface) = ni
When Ei(surface) < EF, we have n(surface) > p(surface), and
n(surface) < p(bulk)
When EF - Ei(surface) = Ei(bulk) - EF, we have inversion of the
surface
We have n(surface) = p(bulk), majority carriers at surface are
now electrons
Also, in other words, Ei(bulk) - Ei(surface) = 2[Ei(bulk)- EF], at
inversion

Block charge diagram

More +ve charge on the gate
Leads to a -ve charge (ionized acceptors in depletion region) near
the surface
Depletion region width grows (assume max. at inversion)
Leads to increase in -ve charged electrons at surface
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EL 511 VLSI Design

MOS Cap Structure: Summary

Depending on the
applied gate
voltage
MOS Cap exhibits:
Accumulation
Depletion
Inversion

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EL 511 VLSI Design

NMOS transistor aka N-Channel MOSFET

Cut-off Region
When 0<Vgs<Vt
No free electrons in the body
Body-Source and Body-Drain are reverse
biased
Almost zero current flows

Linear/Resistive/Un-saturated Region
When Vgs>Vt and Vds<Vgs-Vt
Channel (of majority carriers) is formed
between D and S
Numbers of carriers and conductivity increase
with gate voltage
Vds = Vgs-Vgd, needs to be non-zero for
electric field to push the carriers from S to D
Current is a function of Vgs and Vds

Saturation Region
When Vgd<Vt, or Vds>Vgs-Vt
Channel is no longer inverted near the drain; it
pinches off
Electrons in the channel, approaching the
drain, will get injected in the depletion region,
and accelerated to the drain, due to the
electric field
Current is a function of only Vgs
Current not a function of Vds, and hence
saturates, w.r.t drain voltage
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EL 511 VLSI Design

Ideal IV Equations (NMOS)

Linear or
Resistive or
Un-saturated

<

Saturation

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EL 511 VLSI Design

Ideal IV Characteristics NMOS

What is the meaning of this

plot?
Vds
DC (fine) sweep from 0 to 1.8V

Vgs
DC (step) sweep
0.6, 0.9, 1.2, 1.5, 1.8

Where are linear and saturation

regions in the plot?
Boundary condition
Vds >= Vgs-Vt

Can we approx verify this

graph, with the given
equations?
Can we find the resistance of
the transistor in linear/resistive
region from this plot?

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EL 511 VLSI Design