IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO.

12, DECEMBER 2012

3503

Accurate Compact Modeling for Sub-20-nm NAND

Flash Cell Array Simulation Using the PSP Model
Jongwook Jeon, Il Han Park, Myounggon Kang, Student Member, IEEE, Wookghee Hahn,
Kihwan Choi, Student Member, IEEE, Sunghee Yun, Gi-Young Yang,
Keun-Ho Lee, Young-Kwan Park, and Chilhee Chung

AbstractIn this paper, we have developed a new floating-gatetype Flash cell compact model based on the channel potential
by using PSP metal-oxide-semiconductor description. Cell-to-cell
coupling, FowlerNordheim tunneling, and new leakage current
formulas have been implemented on Verilog-A compact model.
The channel potential calculation of the PSP model enables
accurate modeling of channel coupling and leakage currents
which are associated with the boosted channel. In addition, the
model parameter extraction procedure through 3-D technology
computer-aided design (TCAD) and SPICE simulation is presented. The simulation results agree well with measured data of
sub-20-nm NAND cells.
Index TermsCell-to-cell coupling, compact modeling,
FowlerNordheim (FN) tunneling, leakage current, NAND Flash,
SPICE simulation.

I. I NTRODUCTION

CALING OF Flash memory cell size reduces the margin

of multithreshold voltage level, while cell-to-cell interference, which is well known as the most critical scaling barrier
for NAND Flash memories, is increased [1]. This brings an
essential requirement of an accurate circuit level simulator to
design advanced multilevel memories, which can help design
optimized algorithms for program/erase (P/E) and read operations [2], [3]. Although several papers about analytic modeling
of Flash memory cell for SPICE simulation have been reported [4][8], they are mainly focusing on either basic FowlerNordheim (FN) tunneling during P/E operations or interference
between neighboring floating gates (FGs). There is a call for
more thorough investigations on phenomena at a string level
and various operations with nanoscale devices. Although the
behavior of channel potential was investigated with BSIM4 in
[9], the accurate calculation of channel potential and leakage
Manuscript received May 1, 2012; revised June 28, 2012 and August 13,
2012; accepted September 4, 2012. Date of publication October 24, 2012; date
of current version November 16, 2012. This work was supported by Samsung
Electronics Company, Ltd. The review of this paper was arranged by Editor
Y.-H. Shih.
J. Jeon, S. Yun, G.-Y. Yang, K.-H. Lee, Y.-K. Park, and C. Chung are with
Semiconductor R&D Center, Device Solutions Business, Samsung Electronics
Company, Ltd., Hwaseong 445-701, Korea (e-mail: voix0707@naver.com;
sunghee.yun@samsung.com; giyoung.yang@samsung.com; keunho.lee@
samsung.com; youngpark@samsung.com; chungc@samsung.com).
I. H. Park, M. Kang, W. Hahn, and K. Choi are with the Flash Design
Team, Memory Division, Device Solutions Business, Samsung Electronics
Company, Ltd., Hwaseong 445-701, Korea (e-mail: ilhan.park@samsung.com;
kang77@snu.ac.kr; wg.hahn@samsung.com; kihwan.choi@samsung.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2012.2219863

current models of boosted channel are not available because

BSIM4 is a threshold-voltage-based model.
In this work, we have developed a channel-potential-based
accurate FG Flash cell compact model with sub-20-nm NAND
cell strings. To model a Flash cell, a surface-potential-based
model is much more appropriate than a threshold-voltage-based
model because boosted channel potential can be defined. The
surface-potential-based model can also be used to model the capacitive coupling and leakage currents accurately. To describe
the boosted channel potential, we have adopted PSP metaloxide-semiconductor (MOS) description, which is a surfacepotential-based model [10]. We have developed cell-to-cell
coupling, FN tunneling current, and leakage current models
based on the channel potential approach, and they are implemented into Verilog-A. Precise leakage models related with the
boosted channel are proposed from the results of device level
technology computer-aided design (TCAD) simulation. TCAD
simulation is also used to calculate FG coupling and channel
boosting ratio. The model parameters are extracted from the
measurement of a sub-20-nm Flash cell array, and the predicted
results show good agreement with the measured array behaviors. In addition, the extraction procedure of the parameters is
presented. The developed model accurately describes both dc
and transient behavior of a NAND Flash array.
II. C OMPACT M ODELING OF A F LASH C ELL
Fig. 1 shows the NAND Flash array used for developing the
compact model. Sixty-four NAND Flash cells are connected
in a string (WL0WL63) with two dummy cells (Dummy0
and Dummy1), one ground select line (GSL), and one string
select line (SSL). CSL means common source line bias, and
PPW means pocket p-well bias. The simulated NAND Flash
array is composed of three identical strings, and the center
is the one to be analyzed, whereas the two side strings are
aggressors to describe capacitive coupling effects on the main
string. The memory cell is the FG type, and it is described as
MOS transistors with a stacked ONO capacitor CONO in series
to the FG terminal as shown in Fig. 1. Word-line (WL) bias is
applied to the control gate (CG). In addition, the P/E current
source is attached between the body and the FG.
A. Capacitive Coupling
The capacitive coupling in Flash cells is shown in
Fig. 2(a)(c). Coupling capacitance components are mainly
separated into two categories, which are related with

0018-9383/$31.00 2012 IEEE

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012

Fig. 1. Schematic of a NAND Flash array. Sixty-four cells are organized in a

single string. Three identical strings form a basic NAND Flash array.

as CCOUP = QFG_VICTIM /VAGG_NODE . The channelrelated components, CCG-CH(WL) , CFG-CH(WL) , CFG-CH(BL) ,

CCH-CH(BL) , and CFG-CH(Diag) , are modeled as follows. The
influence of channel coupling is implemented by calculating
the channel potential variation associated with the potential
variations of CG, FG, and channel of adjacent cells, instead of
adding direct coupling capacitance. The reason is that channel
node is defined as an output node only. The channel potential
variation can be quantified by formulating the effective gate
voltage. In sub-20-nm technology, the short-channel effects
should be carefully considered. The PSP model provides necessary parameters describing the short-channel effects such
as velocity saturation, DIBL, channel length modulation, and
mobility degradation [11]. These effects are automatically taken
into account in the calculation of the surface potential of the
drain side (D ). The channel potential (VCH ) is defined as the
midchannel surface potential VCH = (S + D )/2, where S
is the surface potential of the source side. The effective gate
) due to the channel potential variation is
to-body voltage (VGB
formulated as

= VGS + VSB
+ VG VFB + VG_coup1 + VG_coup2
VGB

+VG_coup3 + VG_coup4 + VG_coup5 + VG_coup6

(1)

where VGS is the FG bias, VG is the effect of draininduced barrier lowering (DIBL), and VFB is the flatband
voltage. The channel potential variation is modeled by using
VG_coup1 , VG_coup2 , VG_coup3 , VG_coup4 , VG_coup5 ,
and VG_coup6 which are defined as

Fig. 2. Cell-to-cell capacitance coupling considered in this work: (a) Along

the BL direction, (b) along the WL direction, and (c) along the diagonal
direction.

the FG and the channel potentials. In this paper, FGrelated components, i.e., CONO , CCGFG(WL) , CFGFG(BL) ,
CFGFG(WL) , and CFGFG(Diag) , are calculated by the 3-D
TCAD simulations. The amount of charge variations in
FG of the victim (QFG_VICTIM ) cell is measured by
the changes in the bias of the aggressors (VAGG_NODE ).
Then, coupling capacitance (CCOUP ) can be calculated

VG_coup1 = COUPWG VCG(Adj.WL)

(2)

VG_coup2 = COUPWF VFG(Adj.WL)

(3)

VG_coup3 = COUPBG VCG(Adj.BL)

(4)

VG_coup4 = COUPBF VFG(Adj.BL)

(5)

VG_coup5 = COUPBC VCH(Adj.BL)

(6)

VG_coup6 = COUPDF VFG(Adj.Diag.)

(7)

where VFG(Adj,BL) , VFG(Adj,WL) , and VFG(Adj,Diag.) mean the

FG potentials of adjacent bit line (BL), WL, and diagonal,
respectively. VCG(Adj,BL) and VCG(Adj,WL) mean the CG potentials of adjacent BL and WL, respectively. VCH(Adj,BL)
means the channel potential of adjacent BL. COUPBF, the
adjacent COUPWF, and COUPDF represent the coupling
effects of FG along the BL, WL, and diagonal directions,
respectively. COUPBG and COUPWG represent the coupling
effects of the adjacent CG along the BL and WL directions,
respectively. COUPBC represents the coupling effect of the
adjacent channel along the BL direction.
B. FN Tunneling Currents
To model the change of the FG charge during P/E, the FN
tunneling mechanism [12] is used
2
IFN = AREA ETUN
exp(/ETUN )

(8)

JEON et al.: ACCURATE COMPACT MODELING FOR NAND FLASH CELL ARRAY SIMULATION

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Fig. 4. Experimental conditions to observe GIDL current properties of GSL.

Fig. 5. Definition of the index of boosting potential Vboost .

Fig. 3. Three-dimensional TCAD simulation results of two leakage current
mechanisms (BTBT and II) for EEE and PEP patterns.

where and are optimized parameters, AREA is the tunnel

FN injection area, and ETUN is the electric field through the
oxide. Note that ETUN is accurately calculated by using the

channel potential as in ETUN = (VGB

VFB VCH )/TOX .
C. Leakage Currents
Based on the different mechanism, the leakage current in a
Flash array can be separated into junction leakage and
GIDL current. The junction leakage current occurs in narrow
depletion region when there is a large potential difference
between the channel and the body, and it is modeled with bandto-band tunneling (BTBT) and impact ionization (II) components. The junction leakage current is dependent on the state
of the neighbor channels of the side strings (programmed or
inhibited). Fig. 3 shows the 3D-TCAD simulation results of
BTBT and II leakage currents in EEE and PEP patterns where
E means inhibited string and P is programmed string. The
dominant leakage mechanism is different in the two cases due
to the boosted channel potential level and the depletion width.
BTBT and II models are transformed by using the advanced
diode model (level500) [13]
NAND

Iii_CHS

0


= ZAV I exp ZB
CS rev
VCS
Ibtbt_CHB

0
BT 1
=  BT 2Wdep 1.5  BT 2Wdep 

exp
V
V
CB

CB

for VCS 0
for VCS > 0

for VCB 0
for VCB > 0

(9)

(10)

Iii_CHB

0
= ZC

VCB
ZD Wdep



ZDW
Irev exp VCBdep

for VCB 0
for VCB > 0 (11)

where Wdep is the depletion width, Wdep = (2 Si

VCB /qNe )1/2 , Irev is the reverse bias saturation current,
Irev = 7.13 1013 [A], VCB is the reverse bias between the
channel and the body, and VCS is the reverse bias between the
channel and the source. BT 1, BT 2, ZA, ZB, ZC, and ZD
are optimized parameters. Iii_CHS is the II current flowing
through channel to source which is caused by the reverse bias
between boosted channel and low potential source as shown
in Fig. 3(b). High-electric-field-dependent leakage currents
between channel and body are modeled with Ibtbt_CH and
IiiCHB taking pattern dependence into account as shown in
Fig. 3(c) and (d). In PSP model, the GIDL current model is
calculated in a single MOSFET by using the gatedrain overlap
(VOV ) and the drainbody (VDB ) voltage [14]. However,
GIDL current model should be reexamined in NAND Flash
array circumstance because the adjacent cells and strings affect
the GIDL current behavior. The indirect approach is used to
characterize GIDL current by adopting the index of boosting
potential Vboost in this work. Fig. 4 shows the experimental
setup to observe GIDL current properties in NAND cell array
where incremental-step-pulse programming (ISPP) is used to
program. Vboost is defined as the threshold voltage difference
of the cells (WL32) between programmed and inhibited
strings as shown in Fig. 5. Vboost will be dropped when the
leakage currents flow out of the boosted channel region. Vboost
decreases as VGSL is set lower than the threshold voltage of
GSL as shown in Fig. 6(a) and (b), and it is the evidence of the
existence of GIDL current of GSL. The pattern and adjacent
cell voltage dependences are observed in Fig. 6(a) and (b),
respectively. This GIDL current dependence of neighbor cells

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012

Fig. 6. Measured Vboost in experiments of Fig. 4. (a) Pattern and (b) adjacent
cell dependences on GIDL current are observed.

along BL and WL directions is also observed in GIDL current

of the cell region. Based on this investigation, it is deduced
that, when calculating GIDL current, neighbor cells should be
taken into account. The new GIDL current model is proposed
as follows. To develop GIDL current model, the BTBT model
of the uniform electric field limit by Kane and Keldysh was
used [15]. GIDL current model of the PSP is also based on this
model [11].
GIDL current based on [15] is expressed as
2

exp (BGIDL
/Etov )
JGIDL Etov

(12)

where BGIDL
is a physical parameter which is dependent on the
direct/indirect tunneling and the effective mobility. The value

is 1.9 107 [V cm1 ] [16]. Etov is the maximum

of BGIDL
electric field at the Si/SiO2 interface in the drain overlap region.
Etov consists of a dominant vertical component of victim and
neighbor cells and a lateral component which is proportional
to VDB and VSB . While only VDB is considered in PSP model,
the effect of VSB on GIDL current is also taken into account
because the lateral field is comparable to the vertical field at
the point of the GIDL current occurrence [17]. Thus, Etov
is calculated as (15) shown at the bottom of the page where
CGIDL , DGIDL , EGIDL , and FGIDL are empirical parameters.
COX is the gate oxide capacitance per unit area. Using (12) and
(15), the GIDL current becomes


BGIDL
2
exp
IGIDL = AGIDL Vtov
(16)
Vtov

/Cox .
where AGIDL= (WLov Cox /Si )2 and BGIDL= Si BGIDL
The values of AGIDL and BGIDL can be modulated to the
measured data to optimize the magnitude and the gate voltage
dependence of the GIDL current, respectively. As three addi-

Evertical =

Fig. 7.

Extraction procedure diagram of model parameter.

tional terminals of VOV(WL) , VOV(BL) , and VSB are introduced,

new GIDL current parameters of DGIDL , EGIDL , and FGIDL
are adopted. If DGIDL , EGIDL , and FGIDL parameters are set
to zero, GIDL model (16) becomes the same as that in the PSP
model [14].
III. PARAMETER E XTRACTION AND R ESULTS
The model parameter extraction procedure is shown in Fig. 7.
To obtain the model parameters, we have used cell array of
real NAND Flash circumstance as depicted in Section II. Pattern initialization means that the initial status of the victim
cells FG node is set to initial status of measurements, and
it is performed by injecting some amount of charge into FG
node. Before starting parameter extraction, physical process
parameters of channel length/width, overlap length, doping
concentration of body and gate poly, and oxide thickness are
set into the PSP model. As mentioned in Section II, FGrelated coupling capacitances are obtained from well-calibrated
3-D TCAD simulation. The optimized PSP model parameter
sets are obtained from measured dc data by using the genetic
algorithm with the array simulation [18]. When measuring the


QS
COX

VOV(VIC) + EGIDL VOV(WL) + FGIDL VOV(BL)

Si
Si

Elateral = CGIDL VDB DGIDL VSB


2
COX

VOV(VIC) + EGIDL VOV(WL) + FGIDL VOV(BL) + (CGIDL VDB DGIDL VSB )2

Etov =
Si
=

COX
Vtov
Si

(13)
(14)

(15)

JEON et al.: ACCURATE COMPACT MODELING FOR NAND FLASH CELL ARRAY SIMULATION

Fig. 8. Transfer curve of main cell in which symbols are measured and lines
are simulated data. Insets are plotted in linear scale.

dc characteristics of the NAND array, the pass bias (Vpass )

should be large enough to turn on the cell transistors in all
cell patterns. The parameters for channel coupling capacitances
(COUPWG, COUPWF, COUPBG, COUPBF, COUPBC,
and COUPDF) are extracted in sequence. These parameters
are extracted from the cell-to-cell coupling measurements.
The channel coupling parameters are extracted for various
initial Vth s of the victim cell. The magnitude of interference
from each direction is dominantly determined by FG-to-CH
and CG-to-CH coupling parameters of COUPWF, COUPBF,
COUPDF, COUPWG, and COUPBG. The dependence of
BL interference on initial Vth of the victim cell is modeled
by CH-to-CH coupling parameter COUPBC. One iterative
process is required between dc and channel coupling modeling
because they are related interdependently. The model parameters of FN tunneling current ( and ) are extracted from
the measurement of program and erase speeds. The junction
capacitance (Cjunc ) and outer fringe capacitance (Cof ) should
be considered to acquire accurate boosting channel potential.
From 3-D TCAD simulation, the boosting channel potential can
be plotted versus VFG . Cjunc and Cof and these two capacitances are fitted to the 3-D TCAD simulation result. Note that
the leakage components in 3-D TCAD simulation are turned
off to confirm the only effect of parasitic capacitances on the
boosting ratio. The next step is an extraction of the leakage
current parameters. ZA and ZB are extracted from the result of
EEE pattern in which the II between boosted channel and lowpotential-source region is the dominant leakage mechanism.
BT 1, BT 2, ZC, and ZD are obtained from the results of PEP
and PEE patterns. The GIDL current parameters of AGIDL ,
BGIDL , CGIDL , DGIDL , EGIDL , and FGIDL are obtained from
pattern and adjacent cell (Dummy0 for GSL-GIDL and WL31
for cell-GIDL) dependences. DGIDL , EGIDL , and FGIDL are
optimized with the effects of VSB (VCSL ), adjacent WL cells,
and adjacent BL cells, respectively. In order to extract the model
parameter of the junction leakage current, GIDL current should
be suppressed by biasing lower Vpass voltage to the adjacent
cells. By biasing lower Vpass voltage to VDUM0 and VWL0 , the
field crowding between GSL and Dummy0 can be eliminated;
as a result, GSL-GIDL current is suppressed. Before extracting
the model parameter related to the GIDL current, the model
parameters related to the junction leakage current are extracted.
Note that the coupling and the leakage current models should be
considered in the two side strings as well as in the center string.
Fig. 8 shows the results of dc transfer curve simulation where

3507

Fig. 9. (a) Experiments of cell-to-cell interference and (b) modeling results

for various initial victim states.

Fig. 10. Program speed where the FN tunneling current model is verified.

BL current is plotted versus WL32 voltage for various body

biases (VPPW ), in which Vpass is biased at other WL cells and
GSL/SSL is turned on. Fig. 9(a) shows cell-to-cell interference
which is equivalent to Vth shift of a victim cell as those of
adjacent cell (aggressors) change where P1 and P3 represent the
states of Vth = 0 V and 4 V, respectively. The proposed channel
coupling model shows good agreement with the measured
data in Fig. 9(b). In addition, the channel coupling effect is
clearly described in this figure. The model without channel
coupling effect cannot predict the interference behaviors for
various initial victim states. This is why the surface-potentialbased compact model is needed for sub-20-nm NAND Flash cell
modeling. By extracting the FN parameters ( and ) proposed
in Section II-B, the program speed for various VPGM s is well
predicted as shown in Fig. 10. The proposed junction leakage
and GSL-GIDL current models show good agreement with
the measured Vboost data in Figs. 11 and 12, respectively.
Note that the table in Fig. 11 shows the experimental setup to
measure the junction leakage current with suppressing GIDL
current as mentioned before. As VGSL decreases, GIDL current
increases, and then, the boosted channel potential decreases.
As a result, the junction leakage current is decreased due to
the reduced boosted channel potential. It is explained that the
Vboost drops and saturates when decreasing VGSL as shown in
Fig. 12. Fig. 13 shows the measurement conditions under the
cell-GIDL current. Fig. 14 shows the results of the cell-GIDL
model. It is verified that the proposed leakage current models
reflect well for various patterns and neighbor cell effects in
Figs. 1113. The comparison between the proposed model and
the measured Vth versus ISPP for various patterns is shown in

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 12, DECEMBER 2012

Fig. 15.

Fig. 11. Pattern dependence of Vboost under junction leakage current flow.

Disturb simulation results for various patterns.

total CPU time is approximately 1200 s (ISPP from 13 to

20.2 V with 0.3-V step). The total CPU time for simulation is
dependent on the operation types of the NAND Flash array.
IV. C ONCLUSION
In this paper, we have investigated the compact modeling for
Flash array simulation in which the surface-potentialbased PSP model was used. In NAND Flash strings, the models
of cell-to-cell coupling, junction leakage, and GIDL current
are proposed from the analysis of 3-D TCAD simulation
and measured data. In addition, we presented the procedure
of model parameter extraction which allows extracting exact
model parameter sets. The modeling results were verified with
the measured data, and good agreement was observed. The
developed model allows accurately predicting the dc and transient properties of sub-20-nm NAND Flash cell array including
disturb behavior. Thus, it can be used to develop optimized
algorithms and to examine fail mechanisms.
NAND

Fig. 12. (a) Pattern and (b) adjacent cell (Dummy0) dependences of Vboost
under the GSL-GIDL leakage current flow.

R EFERENCES

Fig. 13.
region.

Experimental conditions to observe GIDL current properties of cell

Fig. 14. (a) Pattern and (b) adjacent cell (WL31) dependences of Vboost
under the cell-GIDL current flow.

Fig. 15. Since this disturb behavior is strongly dependent on

cell-to-cell coupling, FN tunneling, and leakage currents, it is
confirmed that the proposed models are accurately developed
to predict Flash cell array characteristics. When simulating the
program operation in the full NAND array (3 64 cells), the

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Jongwook Jeon received the Ph.D. degree from the

Department of Electrical Engineering, Seoul National University, Seoul, Korea.
He is currently with Semiconductor R&D Center, Device Solutions Business, Samsung Electronics
Company, Ltd., Hwaseong, Korea.

Il Han Park received the Ph.D. degree in electrical

engineering from Seoul National University, Seoul,
Korea.
He is currently with Flash Design Team, Memory
Division, Device Solutions Business, Samsung Electronics Company, Ltd., Hwaseong, Korea.

3509

Kihwan Choi (S01) received the Ph.D. degree from

the University of Southern California, Los Angeles,
in 2005.
He is currently with the Flash Design Team, Memory Division, Device Solutions Business, Samsung
Electronics Company, Ltd., Hwaseong, Korea.

Sunghee Yun received the M.S. and Ph.D. degrees

from Stanford University, Stanford, CA, in 2000 and
2004, respectively.
Since 2004, he has been with Semiconductor R&D
Center, Device Solutions Business, Samsung Electronics Company, Ltd., Hwaseong, Korea.

Gi-Young Yang received the Ph.D. degree from the

Korea Advanced Institute of Science and Technology, Daejeon, Korea.
He is currently with Semiconductor R&D Center, Device Solutions Business, Samsung Electronics
Company, Ltd., Hwaseong, Korea.

Keun-Ho Lee received the Ph.D. degree from the

Korea Advanced Institute of Science and Technology, Daejeon, Korea.
He is currently with TCAD group, Semiconductor
R&D Center, Device Solutions Business, Samsung
Electronics Company, Ltd., Hwaseong, Korea.

Myounggon Kang (S10) received the Ph.D. degree

from Seoul National University, Seoul, Korea.
He is currently with Flash Design Team, Memory
Division, Device Solutions Business, Samsung Electronics Company, Ltd., Hwaseong, Korea.

Young-Kwan Park received the M.S. degree from

Samsung Semiconductor Institute of Technology,
Yongin, Korea.
He is currently the Vice President of CAE team,
Samsung Electronics Company, Ltd., Hwaseong,
Korea.

Wookghee Hahn received the M.S. degree in electrical engineering from Korea University, Seoul, Korea.
He is currently with the Flash Design Team, Memory Division, Device Solutions Business, Samsung
Electronics Company, Ltd., Hwaseong, Korea.

Chilhee Chung received the Ph.D. degree from

Michigan State University, East Lansing, Michigan.
He is currently the Executive Vice President
of the Semiconductor R&D Center, Device Solutions Business, Samsung Electronics Company, Ltd.,
Hwaseong, Korea.