3 Ic&ecad-Manual

III B.
TECH - I SEM (R09) ECE :
Exp.No. 1
IC APPLICATIONS & ECAD LAB
OP AMP APPLICATIONS
Exe.No.
ADDER, SUBTRACTOR, COMPARATOR CIRCUITS
Dt.
AIM: To construct an adder, subtractor and comparator using 741 Op-Amp and to verify their
operation.
APPARATUS:
S.No.
1
2
3
4
5
6
7
8
9
Name of the equipment

IC 741
CRO
Function generator
Bread board
Dual Power Supply
Regulated Power Supply
Resistors
CRO probes
Connecting wires
Range
20 MHz
20 MHz
(-12V) 0 (+12V)
0-5V
10 k
No.s
1
1
1
1
1
2
5
2
10
DESIGN:
Adder / Summing amplifier:
Rf
The output of Adder V0 = - R 1
(V1+V2)
ChooseRf = R1 = 10 k then
V0 = - (V1+V2)
Subtractor:
The output of Subtractor V0 =
Rf
R1
(Vb-Va)
Choose Rf = R1 = 10 k then
V0 = Vb-Va
VISVODAYA TECHNICAL ACADEMY, KAVALI
III B.TECH - I SEM (R09) ECE :
THEORY:
Summer/Adder:
Op-Amp can be used to design a circuit whose output is the sum of several input signals.
Such a circuit is called summing amplifier or summer. Obtain either non-inverting (or) inverting
summer. Fig.1 (a) shows the circuit diagram of two input inverting summer.
It has two input voltages V and V which are applied to inverting terminal of Op-Amp.
The Non-inverting terminal of Op-Amp is grounded.
1
In order to understand the operation of the circuit, assume the following conditions.
(i). Since input resistance of Op-Amp is very large,
the current drawn by either of input terminals of Op-Amp is ZERO.
i.e., IB1 = IB1 = 0
(ii). Since Open loop gain of Op-Amp is very large,
the difference input (Vp-Vn) is essentially ZERO for a finite output voltage.
i.e., (Vp-Vn) = 0 Vp = Vn
In the circuit shown in Fig.1(a), Since V p is connected to physical ground, V n is also at
ground potential. This is called Virtual ground. Due to virtual ground, Vp = Vn = 0.
Referring Fig.1(a), Apply KCL at node n , we have
V nV 1
R1
-(
If
V1
R1
V nV 2
+
R2
V nV 0
+ IB1=0
Rf
V2
V0
R2 ) = R f ( since Vn = Vp = 0 & IB1 = 0)
R1 = R2then
V0 = -
Rf
R1
(V1+V2)
Thus output is amplified and inverted sum of two inputs.

Rf
Note: For non-inverting summing amplifier, V0 = ( 1 + R 1
) (V1+V2)
Subtractor :
A basic differential amplifier can be used as a subtractor. It has two input signals Va and Vb
applied to inverting & non-inverting terminals respectively.
From the Fig.1(b),Vp =
Vb
R 1+ R f
Rf
Referring Fig.1(b), Apply KCL at node n - we have

V nV a
V nV 0
+
+ IB1=0
R1
Rf
Vn
Vn
R1 + R f
Vn(
V0
Rf
Va
V0
) = R1 + R f ( since IB1 = 0)
Va
1
1
R 1 + R f ) - R1
Vb
R 1+ R f
R 1 + R f Rf ( R 1 R f
V0 =
Rf
R1
V0
Rf
) -
Va
R1 ( since Vn = Vp
( Vb Va)
Thus, the output voltage V0 is equal to the voltage

Vb applied to the non inverting terminal minus voltage Va
applied to inverting terminal.
.
Comparator:
A comparator is a circuit which compares signal
voltage applied at one input terminal of an op-amp with a known reference voltage at the other
input terminal. It is basically an open
loop op-amp with output Vsat as in the ideal transfer characteristics.
The output of comparator is given by
Input to comparator
Output of comparator
If Vp>Vn
Vo = + Vsat
If Vp<Vn
Vo = - Vsat
Note that for all possible values of Vp and Vn , the output V0 is restricted to only
two values +Vsat & -Vsat. Thus the comparator accepts analog signals at the input and produces
a binary output at the output terminal and hence it is called as single bit ADC.
There are basically 2 types of comparators.
(a) Non inverting comparator:
Input is applied to Non-inverting terminal & Vref is applied to Inverting terminal
(b) Inverting comparator:
Input is applied to Inverting terminal & Vref is applied to Non-inv terminal
The applications of comparator:
i. zero crossing detector
ii. window detector
iii. time marker generator
iv. phase detector.
CIRCUIT DIAGRAM OF ADDER :
OBSERVATIONS:
Adder:
S.No.
V (Volts)
1
V (Volts)
2
V = -(V +V ) Volts
(Practical )
0
V = -(V +V ) Volts
(Theoretical)
0
1
2
PROCEDURE:
Adder:
1. Connect the circuit as shown in Fig.1(a)..
2. Apply input voltages V = 2V, V = 3V
1
3. Measure the output voltage at pin (6) and note down the reading.
4. For different values of V and V measure the output voltage.
1
CIRCUIT DIAGRAM OF SUBTRACTOR:
OBSERVATIONS:
Subtractor:
S.No.
Va(Volts)
Vb(Volts)
V = (Vb Va) Volts

(Practical )
0
V = (Vb Va) Volts

(Theoretical)
0
1
2
PROCEDURE:
Subtractor :
1. Connect the circuit as shown in Fig.1 (b)..
2. Apply input voltages Va = 2 V, Vb = 3V
3. Measure the output voltage at pin(6) and note down the reading.
4. For different values of Va and Vb measure the output voltage.
CIRCUIT DIAGRAM OF COMPARATOR :
MODEL GRAPH:
OBSERVATIONS:
S.No
Input sine wave

VP-P (Volts)
REF
(Volts)
Output square wave

T1
T2
Amplitude
(Volts)
(ms)
(ms)
T
(ms)
PROCEDURE:
1. Connect the circuit as shown in Fig.1(c)
2. Select the sine wave of 1 V peak to peak, 1 kHz frequency.
3. Apply the reference voltage 0 V to inverting terminal of Op-Amp.
3. Observe the output waveform on CRO and plot.
RESULT:
VIVA QUESTIONS:
1. What is an op-amp?
2. What are ideal characteristics of op amp?
3. What is the function of adder?
4. What is meant by comparator?
5. What are the applications of comparator?
WORKSPACE
Exp.No. 2(a)
Exe.No.
Dt.
ACTIVE FILTER APPLICATIONS FIRST ORDER LPF
10
AIM: To construct a First order Butterworth LPF for a cut-off frequency of 1 kHz with
a pass band gain of 2 and to obtain its frequency response.
APPARATUS:
S.No.
1
2
3
4
5
6
7
8
9
10

IC 741
CRO
Function generator
Bread board
Dual Power Supply
Capacitor
Resistors
Potentiometer
CRO probes
Connecting wires
Range
20 MHz
20 MHz
(-12V) 0 (+12V)
0.01 F
10 k
22 k
No.s
1
1
1
1
1
1
3
1
2
10
DESIGN:
The upper cut-off frequency of LPF is given by fH =
1
2 RC
Let fH = 1 kHz, C = 0.01 F then R = 15.9 k

By using 22 k potentiometer, we can set R = 15.9 k.
Pass band gain AF
Rf
= (1 + R 1 ) = 2.
Choose RF = 10 k and R1 = 10 k.
THEORY :
Active Filters:
An electric filter is a frequency selective circuit that passes the signals of specified band of
frequencies and blocks/attenuates the signals of frequencies outside this band.
11
Classification of Filters:
1.
2.
3.
4.
5.
Based on input signals

Analog & Digital filters
Based on components used
Active & Passive filters
Based on frequency of operation
AF & RF filters
Based on pass band & stop bands
LPF, HPF, BPF, BRF, All pass filters
Based on frequency response :
Butterworth filters (flat pass band & flat stop band)
Chebyshev filters (ripple pass band & flat stop band)
Cauer filter (ripple pass band & ripple stop band)
Bessel filter (similar to Butterworth filter but gain decreases sharply at fc )
6. Based on the Order of the filter.

The actual response of the filter changes with increase in frequency in stop band.
The rate at which the gain changes in the stop band is indicated by the Order n.
As the order of the filter increases, the response is more close to the ideal response.
Advantages of Active Filters:
1.
2.
3.
4.
Gain and frequency adjustment flexibility

No loading problem due to high Ri and low R0 of Op-Amp.
Active filters eliminate the need for inductors which are large, heavy & costly.
The frequency response of active filters can be made to approach the ideal form.
LOWPASS FILTER:
The first order Butterworth LPF uses an RC network for filtering. The Op-Amp
is used in the non- inverting configuration, hence it does not load down the RC network.
Resistor RF and R1 determine the gain of the filter.
The transfer function of the LPF is given by
V0
T(jw) = V
= AF/
1+ j(
whereAF = (1 +
f
)
fH
RF
R1
) = pass band gain of filter
f = frequency of the input signal.

fH=Cut-off frequency / Break frequency / 3-dB frequency
1
= 2 RC
The gain (or) magnitude and phase angle equations of the LPF can be obtained by
converting T(jw) into its equivalent polar form as follows.
Gain = |
V0
V
Phase = Tan-1
| = AF /
(
1+(
12
f 2
)
fH
f
)
fH
The operation of the LPF can be verified from the gain magnitude equation.
(i) For very low frequencies i.e f<fH , the gain is constant and equal to AF
1
(ii) At frequency f = f H , the gain is 2 times of its maximum value.
(iii)
This frequency is called as Cut-off frequency/ Break frequency / 3-dB frequency.

For high frequencies f> f H, the gain decreases at a rate of 20 dB/ decade
as frequency increases.
CIRCUIT DIAGRAM:
MODEL GRAPH:
13
PROCEDURE:
1. Connect the circuit as shown in Fig.2.1
2. Apply sine wave of amplitude 1 Vp-p to the non inverting input terminal.
3. Vary the frequency of input signal from 10 Hz to 100 kHz.
4. Note down the corresponding output voltage for each frequency.
5. Tabulate the values and calculate the gain in dB.
6. Plot a graph between frequency and gain.
8. Calculate the 3-dB frequency and Identify stop band & pass band from the graph.
TABULAR COLUMN:
S.No
.
Frequency
(Hz)
V0
(Volts)
Vin = 1 V
Gain in dB
20 log (Vo / Vin )
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Exp.No. 2(b)
14
ACTIVE FILTER APPLICATIONS -
Exe.No.
FIRST ORDER HPF
Dt.
AIM: To construct a first order Butterworth HPF for a cut-off frequency of 1 kHz with
a pass band gain of 2 and to obtain its frequency response.
APPARATUS:
S.No.
1
2
3
4
5
6
7
8
9
10

IC 741
CRO
Function generator
Bread board
Dual Power Supply
Capacitor
Resistors
Potentiometer
CRO probes
Connecting wires
Range
20 MHz
20 MHz
(-12V) 0 (+12V)
0.01 F
10 k
22 k
No.s
1
1
1
1
1
1
3
1
2
10
DESIGN:
The Lower cut-off frequency of HPF is given by
fL =
1
2 RC
Let fH = 1 kHz , C = 0.01 F then R = 15.9 k

By using 22 k potentiometer, we can set R = 15.9 k.
Pass band gain AF = (1 +
Rf
R1
) = 2.
Choose RF = 10 k and R1 = 10 k.
15
THEORY:
HIGH PASS FILTER:

The first order Butterworth HPF uses RC network for filtering.The Op-Amp
is used in the non- inverting configuration, hence it does not load down the RC network.
Resistor RF and R1 determine the gain of the filter.
The transfer function of the HPF is given by
T (jw) =
V0
V
Where AF = (1 +
= AF /
Rf
R1
1 j (
fL
)
f
) = pass band gain of filter
f = frequency of the input signal.

fH =Cut-off frequency / Break frequency / 3-dB frequency
1
= 2 RC
The gain (or) magnitude and phase angle equations of the HPF the can be obtainedby
converting T(jw) into its equivalent polar form as follows.
V0
fL 2
1+(
)
Gain = | V | = AF /
f
fL
Phase = Tan-1 ( f )
The operation of the LPF can be verified from the gain magnitude equation.
(i) For high frequencies i.e f > f L , the gain is constant and equal to AF
1
(ii) At frequency f = f L, the gain is 2 times of its maximum value.
(iii)
This frequency is called as Cut-off frequency/ Break frequency / 3-dB frequency.

For Low frequencies f< f L, the gain changes at a rate of 20 dB/ decade.
16
CIRCUIT DIAGRAM:
MODEL GRAPH:
PROCEDURE:
17

2. Apply sine wave of amplitude 1 Vp-p to the non inverting input terminal.
3. Vary the frequency of input signal from 10 Hz to 100 kHz.
4. Note down the corresponding output voltage for each frequency.
5. Tabulate the values and calculate the gain in dB.
6. Plot a graph between frequency and gain.
8. Calculate the 3-dB frequency and Identify stop band & pass band from the graph.
TABULAR COLUMN:
S.No
.
Frequency
(Hz)
V0
(volts)
Vin = 1 V
Gain in dB
20 log (Vo / Vin )
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RESULT:
18
VIVA QUESTIONS:
1. What is the function of the filter?
2. What are the different types of filters?
3. What are the advantages of Active filters?
3. Define pass band and stop band of filters?
4. Define cut off frequency of a filter?
5. What is the difference between HPF & LPF?
Exp.No. 3
FUNCTION GENERATOR USING OP-AMP
Exe.No.
Dt.
AIM:
To design a function generator using Op-Amp to generate square wave, triangular wave &
saw tooth waveforms at 1 kHz frequency.
APPARATUS:
S.No.
1
2
3
4
5
6

IC 741
CRO
Bread board
Dual Power Supply
Capacitor
Resistor
Potentiometers
8
9
CRO probes
Connecting wires
Range
20 MHz
(-12V) 0 (+12V)
0.1 F
330
1 k
10 k
47 k
No.s
2
1
1
1
1
1
1
1
1
2
10
DESIGN:
Let Vsat = 10V
The amplitude of Triangular wave V01 =
2 R2
R1
For a triangular wave of 5 V amplitude,
19
Vsat
R2
R1
= 0.25
Use R2 = 330 standard resistor & R1 = 1 k POT.
Time Period of Triangular wave F =
R1
4 R2 R 3 C
For output frequency of 1 kHz, T = 1 ms

Choose C = 0.1 F then R3 = 10 k .
THEORY:
The function generator generates different types of waveforms which are functions of time.
The circuit shown in Fig.4.1. is a function generator which generates square and triangular wave. It
consists of a comparator and an integrator. The output of comparator is a square wave of amplitude
Vsat . This voltage is applied to the inverting of integrator A2 producing a triangular wave.
The operation of the function generator can be explained as follows:
Initially let us consider the o/p of comparator v01 = +Vsat.
Since this +Vsat is applied to integrator, the o/p of integrator v02 is a -ve ramp.
Since v02 is ve ramp, the node voltage Vp decreases.
At time t= T1 , Vp decreases, crosses ZERO and goes in -ve direction.
This switches the o/p of comparator from +Vsat to - Vsat.
Now the o/p of integrator v02 is +ve ramp signal & Vp increases.
This switches the o/p of comparator from -Vsat to + Vsat.
This cycle repeats.
The amplitude of Square wave v01 = +Vsat
The amplitude of Triangular wave v02 =

Time Period of Triangular wave F =
2 R2
R1
20
Vsat
R1
4 R2 R 3 C
CIRCUIT DIAGRAM:
MODEL GRAPH:
21
OBSERVATIONS: ( for Triangular wave generator )

Peak-to-peak
amplitude (V)
T1 (ms)
T2 (ms)
T(ms)
frequency (Hz)
Triangular waveform
Square wave o/p
CIRCUIT DIAGRAM:
22
MODEL GRAPH:
OBSERVATIONS: ( for Sawtooth waveform generator )

Peak-to-peak
amplitude (V)
T1 (ms)
T2 (ms)
T(ms)
frequency (Hz)
Sawtooth waveform
Square wave o/p
PROCEDURE:
1. Connect the circuit as shown in the Fig.3.1.
2. Observe the triangular waveform output at pin (6) of Op-Amp (A2) and square wave
output at pin (6) of Op-Amp (A1).
3. Note down the amplitude & time periods of square wave and triangular wave outputs
4. Plot the waveforms on a graph sheet.
5. To get the saw tooth waveform, connect the circuit as shown in fig.3.3.
6. Repeat the steps 2, 3 & 4.
23
RESULT:
VIVA QUESTIONS:
1. What is a function generator?
2. List some applications of function generator?
3. What is the use of integrator circuit in function generator?
4. Which circuit acts as a square wave generator?
WORKSPACE
Exp.No. 4(a)
Exe.No.
Dt.
24
MONOSTABLE MULTIVIBRATOR
USING IC 555 TIMER
AIM: To construct and study the operation of a monostable multivibrator using IC 555 timer.
25
APPARATUS:
S.No.
1
2
3
4
5
6
7
8
9
10
11

IC 555 Timer
CRO
Function generator
Bread board
Range
20 MHz
20 MHz
0 - 30 V
0.01 F
0.1 F
10 F
1 k
10 k
Capacitors
Electrolyte capacitor
Resistors
Diode BY127
CRO probes
Connecting wires
No.s
1
1
1
1
1
1
2
1
1
1
1
2
10
DESIGN:
Let the trigger input T = 4 ms ( f = 250 Hz )
Output pulse width of monostable multi
tp = 1.1 RC
For the pulse width of 1.1 ms, Choose C = 0.1 F
then R = 10 k.
THEORY:
The monostable multi vibrator has one stable state and one quasi stable state. The circuit
remains in its stable state until an external trigger pulse is applied. When the external trigger pulse
is applied to monostable circuit, it switches to quasi-stable state and after a pre-defined time
interval it will automatically comes back to its original stable state. This circuit is also called as
one shot multivibrator.
This circuit is useful for generating a single output pulse of required period in response to a
triggering signal. The width of the output pulse depends only on external components R & C.
The negative triggering pulses are generated through input differentiator circuit & diode D.
26
Let us assume that the circuit is in stable state i.e., the output V0 is at +Vsat.
When the negative trigger is applied at pin (2),
The output of internal comparator C2 goes to HIGH state and sets the flip-flop.
Hence output V0 goes to HIGH state which is its quasi stable state
Now the capacitor C starts charging towards +Vcc through R.
2
When the capacitor voltage reaches 3 Vcc which is the threshold voltage of comparator C1
The output of internal comparator C1 goes to LOW state and resets the flip-flop.
Hence output V0 goes to LOW state which is its stable state.
Now internal transistor T1 will be ON and capacitor discharges through T1.
The duration of quasi stable state (or) output pulse duration of mono-stable multivibrator
depends on the capacitor charging time constant i.e., the time required for the capacitor to charge
up to
2
3
Vcc. It is given by
tp = 1.1 RC
The applications of 555 timer in mono-stable mode are

(i)
Missing pulse detector
(ii)
Frequency divider
(iii)
Linear ramp generator
(iv)
Pulse width modulator
CIRCUIT DIAGRAM:
27
INTERNAL DIAGRAM OF IC 555 :
28
MODEL GRAPH :
PROCEDURE:
2. Apply a negative triggering at pin (2).
3. Measure the output voltage at pin (3) by connecting it to the channel-1.
4. Measure the output voltage across capacitor at pin (7) by connecting it to the channel-2
5. Note down the amplitude & time period of output pulse and compare with theoretical values.
6. Plot the graph for input & output waveforms
29
RESULT :
VIVA QUESTIONS :
30
1. What is another name for mono stable multi?

2. What is the purpose of pin reset?
3. Define duty cycle?
4. What are the various applications of one shot?
5. How many external triggers are necessary in one shot?
ASTABLE MULTIVIBRATOR
Exp.No. 4(b)
Exe.No.
USING IC 555 TIMER
Dt.
AIM: To construct and study the operation of the astable multivibrator using IC 555 timer.
APPARATUS:
S.No.
1
2
3
4

IC 555 Timer
CRO
Bread board
Capacitors
6
7
8
9
Resistor
Diode BY127
CRO probes
Connecting wires
Range
20 MHz
0 - 30 V
0.01 F
0.1 F
6.8 k
No.s
1
1
1
1
1
1
2
1
2
10
DESIGN:
Let Vcc = 10 V, T1 = 1 ms, T2 = 0.5 ms
For astable multivibrator using IC 555 timer,
T1 = 0.693 (RA+RB) C
T2 = 0.693 RB C
Let C = 0.01 F then, RB = 6.8 k & RA = 6.8 k.
31
THEORY :
The astable multivibrator has two quasi-stable states and it continuously switches between
these two quasi-stable states. The duration of each quasi stable states depends only on external
components RA , RB & C. It is also called as square wave generator / free running multivibrator.
The astable multivibrator is useful for generating a square wave of required time period &
duty cycle. The circuit shown in Fig.4.5. is the astable multivibrator using 555 timer. The operation
of this circuit can be explained as follows:
Consider an instant when the o/p is at HIGH state.
When v0 is at HIGH, the o/p of internal Flip-flop Q =1 & Q1 = 0
Since, Q1 = 0,
The internal Transistor OFF
& capacitor C starts charging towards + Vcc with time constant (RA+RB) C.
This capacitor voltage is applied as threshold input to comparator C1.

2
At time t= T1 , the capacitor voltage reaches 3 Vcc , the output of C1 becomes HIGH.
This HIGH output from C1 resets the Flip-flop & Hence Q = 0 & Q1 = 1.
Now output When v0 is LOW & Since Q1 = 1, the internal Transistor ON.
& capacitor C starts discharging through transistor with time constant RBC.
This capacitor voltage is applied as trigger input to comparator C2.
1
At time t= T1 , the capacitor voltage reaches 3 Vcc , the output of C2 becomes HIGH.
This HIGH output from C2 sets the Flip-flop & Hence Q = 1 & Q1 = 0.
This makes the transistor OFF and again capacitor C starts charging.
Thus the capacitor periodically charges and discharges between
The time during which the capacitor charges from
1
3
Vcc to
2
3
Vcc and
2
3
1
3
Vcc.
Vcc is called as charging
period (or) ON time and it is given by T1 = 0.693 (RA+RB) C.
The time during which the capacitor discharges from
2
3
Vcc to
1
3
32
Vcc is called as discharge
period (or) OFF time and it is given by T2 = 0.693 RBC.

The time period of output square wave is T = ( T1 + T2 )
The duty cycle D =
T1
T 1 +T 2
= 0.693 (RA+2RB) C.
R A + RB
R A +2 R B
CIRCUIT DIAGRAM:
INTERNAL DIAGRAM OF IC 555 :
33
MODEL GRAPH :
34
OBSERVATIONS :
PRACTICAL VALUES
-ve
peak(V)
+ve
peak(V)
T1
(ms)
T2
(ms)
THEORITICAL VALUES
T
(ms)
-ve
peak(V)
+ve
peak(V)
T1
(ms)
T2
(ms)
T
(ms)
Output
at pin(3)
Output
at pin(7)
PROCEDURE:
2. Switch on the power supply Vcc (+10V)
3. Measure the output voltage at pin (3) by connecting it to the channel-1.
4. Measure the output voltage across capacitor at pin (7) by connecting it to the channel-2
5. Note down the amplitude & time period of output waves and compare with theoretical values.
6. Plot the graph for output waveforms
RESULT :
35
VIVA QUESTIONS:
1. Define astable multi?
2. What is the other name for astable multi?
3. Mention the applications of free running oscillator?
4. How many external triggers are necessary for astable?
36
WORKSPACE
Exp.No. 5(a)
37
VOLTAGE REGULATOR USING IC 723
Exe.No.
LOW VOLTAGE REGULATOR
Dt.
AIM : (a) To design and verify a low voltage regulator for an output voltage of 6V.
(b) To obtain load regulation characteristics.
APPARATUS:
S.No.
1
2
3
4
5
6

LM 723 IC
Bread board
dc ammeter
dc voltmeter
Digital multimeter
Capacitors
Resistors
9
10
Potentiometer
Connecting wires
Range
0 - 30 V
0-2 A
0-20 V
0.1 F
100 pF
1 k
2.2 k
5.6 k
10 k
15 k
22 k
No.s
1
1
1
1
1
1
1
1
1
1
1
1
1
1
10
DESIGN :
The output of a low voltage regulator using IC723 is given by
R2
V0 = 7.15 *( R 1+ R 2 )
For an output voltage of 6V,
Let R1 = 1 k then, R2 = 5.2 k (use R2 = 5.6 k )
Choose C = 100 pF & R3 =
R1 R 2
R 1+ R 2
= 2.2 k.
38
THEORY:
A voltage regulator is a circuit that supplies constant voltage regardless of changes in load
current,temperature ,power supply. Except for the switching regulators, all other types of regulators
are linear regulators.
LM 723 IC is general purpose linear voltage regulator.Input voltage of this 723 IC is 40 V
maximum. Output voltage is adjustable from 2V to 30 V.
The functional block diagram of IC 723 has two sections.
(i)
Reference constant voltage source: The zener diode and a constant current source
produces a fixed voltage about 7.15V at terminal Vref.
(ii)
Error Amplifier: A series pass transistor Q1 and a current limiting resistor Q2
Low Voltage Regulator:

The Vref is applied to non-inverting input of error amplifier through a potential divider.
The difference between VP and V0 is applied to the
The output of low voltage regulator is given by
V0 =
7.15 *(
R2
R 1+ R 2
39
CIRCUIT DIAGRAM:
TABULAR COLUMN :
Line Regulation
Input Voltage
Vin (Volts)
S.No.
Output Voltage
Vo (Volts)
1
2
3
4
5
6
7
8
9
10
11
12
PROCEDURE:
40
1.
2.
3.
4.
Connect the circuit as shown in fig 5.1.

Connect the power supply between 12 and 7 pins
Connect the volt meter between 10 and 7 pins
Vary the input voltage from 0V to 12V in steps and note down the corresponding
Output voltage.
5. Draw the graph between input voltage and output voltage.
RESULT:
VIVA QUESTIONS:
1. What is regulator?
2. What is meant by line regulation?
3. What is meant by load regulation?
4. Formula for % REGULATION?
5. What is full load in voltage regulation?
Exp.No. 5(b)
41
VOLTAGE REGULATOR USING IC 723
Exe.No.
HIGH VOLTAGE REGULATOR
Dt.
AIM: To design and set up a High voltage regulator for an output voltage of 12V.
APPARATUS:
S.No.
1
2
3
4
5
6

LM 723 IC
Bread board
dc ammeter
dc voltmeter
Digital multimeter
Capacitors
Resistors
9
10
Potentiometer
Connecting wires
Range
0 - 30 V
0-2 A
0-20 V
0.1 F
100 pF
1 k
2.2 k
5.6 k
10 k
15 k
22 k
No.s
1
1
1
1
1
1
1
1
1
1
1
1
1
1
10
DESIGN :
The output of a high voltage regulator using IC732 is given by
R1
V0 = 7.15 *(1+ R 2 )
For an output voltage of 12V,
Let R1 = 10 k then, R2 = 17.7 k (use R2 = 15 k).
Choose C = 100 pF & R3 = 6.8 k
CIRCUIT DIAGRAM:
42
TABULAR COLUMN :
Line Regulation
Input Voltage
Vin (Volts)
S.No.
Output Voltage
Vo (Volts)
1
2
3
4
5
6
7
8
9
10
11
12
PROCEDURE:
LINE REGULATION
43
1.
2.
3.
4.
Connect the circuit as shown in fig 5.2.

Connect the power supply between 12 and 7 pins
Connect the volt meter between 10 and 7 pins
Vary the input voltage from 0V to 15V in steps and note down the corresponding
Output voltage.
5. Draw the graph between input voltage and output voltage.
RESULT:
VIVA QUESTIONS:
1. What is regulator?
2. What is meant by line regulation?
3. What is meant by load regulation?
4. Formula for % REGULATION?
5. What is full load in voltage regulation?
WORKSPACE
44
45
Exp.No. 6
4 - BIT DAC USING OP AMP
Exe.No.
Dt.
AIM:
To construct and verify 4-bit digital to analog converter.
APPARATUS:
S.No.
1
2
3
4
5

4-bit DAC trainer
Dual Power Supply
Multimeter
Patch cards
Range
(-12V) 0 (+12V)
5V
No.s
1
1
1
1
4
THEORY:
The Digital to Analog Converter (DAC) converts n-bit binary word into equivalent analog
voltage or current . The DAC uses an Op-Amp as current to voltage converter and a binary
weighted resistor network (or) R-2R ladder network.
Weighted Resistor DAC:
The weighted resistor DAC uses a binary weighted resistor network which consists of
n- resistors with values 20R, 21R, 22R, 23R, 2n-1R. The input binary data ( b0b1b2b3 .) is
applied to weighted resistor network through digitally controlled SPDT switches. If the binary input
to a particular switch is 1, it connects resistance to the reference voltage (V R) and if the input is 0,
the switch connects the resistor to the ground.
The disadvantage of weighted resistor DAC is it requires wide range of resistors values
0
(2 R to 2n-1R). Also the fabrication of large values of resistors on IC is difficult.
R-2R ladder DAC:
In binary weighted resistor DAC, wide range of resistors values (2 0R to 2n-1R) are required.
This can be avoided by using R-2R ladder type DAC where only 2 values of resistors are required
( R and 2R) . The input binary data ( b0b1b2b3) is applied through digitally controlled SPDT
switches. Binary inputs can be high (+5V) or low(0V).
If the binary input to a particular switch is 1, it connects resistance to the reference voltage
(VR) and if the input is 0, the switch connects the resistor to the ground.
The output current I0 is the binary weighted sum of all currents and it is given by
I0 =
VR
0
2 R
bn-1
VR
1
2 R
bn-2 +
VR
22 R
bn-3
+ .+
R
n1
46
b0
CIRCUIT DIAGRAM:
TABULAR COLUMN:
Binary Input
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Equivalent
Theoretical
Practical
Decimal Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Analog output (V)
Analog output (V)
47
PROCEDURE:
1. Connect the circuit as shown in figure 6.1.
2. Pin7 is connected to +Vcc and Pin 4 is connected to -Vcc
3. Apply the Binary input ( b0b1b2b3).
4. Output is taken between Pin 6 and ground
5. Measure the corresponding output voltage using Multimeter and tabulate.
6. Plot the graph between binary input and analog output.
RESULT:
VIVA QUESTIONS:
1. What is meant by resolution,linearity & accuracy of DAC?
2. What are the disadvantages of weighted resistor DAC?
3. What are the values of resistors required in weighted resistor DAC if LSB resistor value is
12K for a 4 bit DAC?
4. What are the applications of DAC?
48
WORKSPACE
.No. 1
49
LOGIC GATES
Exe.No.
Dt.
AIM: To Simulate all basic gates and universal gates using VHDL.
TOOLS:
VHDL software XILINX 9.2I
MODELSIM simulator
PROCEDURE:
1. Write separate VHDL programs for all basic gates and universal gates.
2. Simulate them by using MODELSIM simulator.
3. Draw the wave forms separately.
AND GATE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity AND2 is
Port ( A : in std_logic;
B : in std_logic;
Y : out std_logic);
end AND2;
architecture Behavioral of AND2 is
begin
Y<=A AND B;
end Behavioral;
50
OR GATE:
library IEEE;
entity OR2 is
B : in std_logic;
Y : out std_logic);
end OR2;
architecture Behavioral of OR2 is
begin
Y<=A OR B;
end Behavioral;
NOT GATE:
library IEEE;
entity not1 is
Y : out std_logic);
end not1;
architecture Behavioral of not1 is
begin
Y<= not A;
end Behavioral;
51
NAND GATE:
library IEEE;
entity NAND2 is
B : in std_logic;
Y : out std_logic);
end NAND2;
architecture Behavioral of NAND2 is
begin
Y<=A NAND B;
end Behavioral;
NOR GATE:
library IEEE;
entity NOR2 is
B : in std_logic;
Y : out std_logic);
end NOR2;
architecture Behavioral of NOR2 is
begin
52
Y<=A NOR B;
end Behavioral;
XOR GATE:
library IEEE;
entity XOR2 is
B : in std_logic;
Y : out std_logic);
end XOR2;
architecture Behavioral of XOR2 is
begin
Y<= A XOR B;
end Behavioral;
XNOR GATE:
library IEEE;
entity XNOR2 is
B : in std_logic;
Y : out std_logic);
53
end XNOR2;
architecture Behavioral of XNOR2 is
begin
Y<= A XNOR B;
end Behavioral;
TRUTH TABLES FOR LOGIC GATES

AND GATE
OR GATE
NOT GATE
54
NAND GATE
NOR GATE
XOR GATE
XNOR GATE
A
Y=A B
55
LOGIC GATES OUTPUT WAVEFORM
p=not a
q=b or c
s=d and e
t=f nand g
u=h nor I
v=j xor k
RESULT :
56
VIVA QUESTIONS
1. Why NAND /NOR gates are called universal gates?
2. Which IC is an XOR gate?
3. Draw 2 input XOR gate using 2 input NAND gates.
4. State Demorgans Theorm.
5. What is an Acronym of VHDL?
6. What are the different Design Units in VHDL?
7. Design AB+CD using NAND gates.
Exp.No. 2
ADDERS AND SUBTRACTORS
Exe.No.
Dt.
2(a) HALF ADDER

AIM: To Simulate Half adder using VHDL.
TOOLS:
MODELSIM simulator
PROCEDURE:
1. Write VHDL program for Half adder.
2. Simulate half adder using MODELSIM simulator.
3. Draw the wave forms separately.
PROGRAM:
library IEEE;
entity halfadder is
57
Port ( a : in std_logic;
b : in std_logic;
sum : out std_logic;
carry : out std_logic);
end halfadder;
architecture Behavioral of halfadder is
begin
sum<= a xor b;
carry<= a and b;
end Behavioral;
LOGIC DIAGRAM :
TRUTH TABLE FOR HALF ADDER
SUM
0
0
1
1
0
1
0
1
0
1
1
0
CARR
Y
0
0
0
1
58
HALF ADDER OUTPUT WAVE FORM
2(b) HALF SUBTRACTOR

AIM: 1.To simulate Half Subtractor using VHDL.
TOOLS:
VHDL software
MODELSIM simulator
PROCEDURE:
1. Write VHDL program for Half Subtractor.
2. Simulate Half Subtractor using MODELSIM simulator.
3. Draw the wave form separately.
PROGRAM:
library IEEE;
59
entity halfsubtractror is
b : in std_logic;
Diff : out std_logic;
Borrow : out std_logic);
end halfsubtractor;
architecture Behavioral of halfsubtractor is
signal abar : std_logic;
begin
diff <= a xor b;
abar<= not a;
borrow<= abar and b;
end Behavioral;
LOGIC DIAGRAM :
TRUTH TABLE FOR HALF SUBTRACTOR
DIFFERENC
BORROW
0
0
1
1
E
0
1
1
0
0
1
0
1
60
0
1
0
0
HALF SUBTRACTOR OUTPUT WAVE FORM
2(c)FULL ADDER
AIM: 1. To simulate Full adder using VHDL.
TOOLS:
MODELSIM simulator
PROCEDURE:
1. Write separate VHDL program for Full adder.
2. Simulate Full adder using MODELSIM simulator.
PROGRAM:
61
library IEEE;
entity FULLADDER is
b : in std_logic;
c : in std_logic;
end FULLADDER;
architecture Behavioral of FULLADDER is
begin
sum<= a xor b xor c;
carry<= (a and b) or (b and c) or (c and a);
end Behavioral;
LOGIC DIAGRAM :
62
TRUTH TABLE FOR FULL ADDER

A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
SUM
0
1
1
0
1
0
0
1
CARRY
0
0
0
1
0
1
1
1
FULL ADDER OUTPUT WAVE FORM
2. (d) FULL SUBTRACTOR
AIM: 1.To simulate Full Subtractor using VHDL.

TOOLS:
MODELSIM software
PROCEDURE:
1. Write separate VHDL programs for Full Subtractor.
2. Simulate Full Subtractor using MODELSIM simulator.
63

PROGRAM:
library IEEE;
entity FULLSUBTRACTOR is
b : in std_logic;
c : in std_logic;
dif : out std_logic;
borrow : out std_logic);
end FULLSUBTRACTOR;
architecture Behavioral of FULLSUBTRACTOR is
signal abar : std_logic;
begin
abar <= not a;
dif<= a xor b xor c;
borrow<= (abar and b) or (b and c) or (abar and c);
end Behavioral;
LOGIC DIAGRAM :
64
TRUTH TABLE FOR FULL SUBTRACTOR
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DIFFERENC
E
0
1
1
0
1
0
0
1
BORRO
W
0
1
1
1
0
0
0
1
FULL SUBTRACTOR OUTPUT WAVE FORM
65
2. (e) RIPPLE CARRY ADDER
AIM: 1.To simulate ripple carry adder using VHDL.

TOOLS:
VHDL software
MODELSIM simulator
PROCEDURE:
1. Write separate VHDL program for ripple carry adder.
2. Simulate ripple carry adder using MODELSIM simulator.
PROGRAM:
library IEEE;
entity RCA is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
c : inout std_logic_vector(4 downto 0);
s0,s1,s2,s3 : out std_logic);
end RCA;
architecture rca_s of RCA is
component fa is
Port ( x : in std_logic;
y : in std_logic;
z : in std_logic;
sum: out std_logic;
end component;
begin
f1: fa portmap (a(0),b(0),0,s0,c(1));
f1: fa portmap (a(1),b(1),c(1),s1,c(2));
f1: fa portmap (a(2),b(2),c(2),s2c(3));
f1: fa portmap (a(3),b(3),c(3),s3,c(4));
end rca_s;
66
library IEEE;
entity fa is
Port ( x : in std_logic;
y: in std_logic;
z : in std_logic;
end fa;
architecture Behavioral of fa is
begin
sum<= x xor y xor z;
carry<= (x and y) or (x and z) or (y and z);
end Behavioral;
LOGIC DIAGRAM:
RIPPLE CARRY ADDER OUTPUT WAVEFORM
67
RESULT :
VIVA QUESTIONS
1. Design Full adder using two Half adders?
2.
3.
4.
5.
6.
7.
8.
68
Design Full subtractor using two Half Subtractors?

Why ripple carry adder is slow?
What are the advantages of carry look ahead adder?
Define an Entity?
What is the Architecture?
What is Simulation?
What are the Different Simulation tools?
WORKSPACE
69
Exp.No. 3
Exe.No.
DECODER/ENCODER
Dt.
3. (a). 3 TO 8 DECODER-74138
AIM: 1.To simulate 3 to 8 Decoder using VHDL software.
TOOLS:
MODELSIM simulator
PROCEDURE:
1. Write VHDL program for 3 to 8 decoder.
2. Simulate the program by using MODELSIM simulator.
3. Draw the waveforms separetly.
PROGRAM
library IEEE;
entity decoder3to8 is
Port ( a : in std_logic_vector(2 downto 0);
e1 : in std_logic;
e2_l : in std_logic;
e3_l : in std_logic;
70
Y_l : out std_logic_vector(7 downto 0));

end decoder3to8;
architecture decoder1 of decoder3to8 is
signal y_li:std_logic_vector(7 downto 0);
begin
with a select
y_li<= "11111110" when "000",
"11111101" when "001",
"11111011" when "010",
"11110111" when "011",
"11101111" when "100",
"11011111" when "101",
"10111111" when "110",
"01111111" when "111",
"11111111" when others;
Y_l<=y_li when(e1 and not e2_l and not e3_l)='1'
else
"11111111";
end decoder1;
PIN AND LOGIC DIAGRAM OF IC 74X138
71
TRUTH TABLE FOR 3 TO 8 DECODER
IN PUT
OUT PUT
E1
E2L
E3L
Y7L
Y6L
Y5L
Y4L
Y3L
Y2-L Y1L
Y0L
0
X
X
1
1
1
1
1
1
1
1
X
1
X
0
0
0
0
0
0
0
0
X
X
1
0
0
0
0
0
0
0
0
X
X
X
0
0
0
0
1
1
1
1
X
X
X
0
0
1
1
0
0
1
1
X
X
X
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
DECODER OUTPUT WAVE FORM
72
VIVA QUESTIONS
1.
2.
3.
4.
5.
6.
7.
How much number of inputs and outputs for a 2 to 4 Decoder?

How to Design 5 to 32 decoder using 3 to 8 decoder?
Design Full adder using 3to 8 Decoder?
Which IC is 2 to 4 decoder?
What are the terminals G1, G2a_L, G2b_L in IC 74x138?
What are the Different modes in Entity Declaration?
What is synthesis?
3.B ENCODER
AIM: 1.To simulate Encoder using VHDL software.
TOOLS:
MODELSIM simulator
PROCEDURE:
1. Write VHDL program for Encoder.
3.Draw the waveforms separetly.
PROGRAM
library IEEE;
73
entity enc is
Port ( d : in std_logic_vector(7 downto 0);
e : in std_logic;
z : out std_logic_vector(2 downto 0));
end enc;
architecture Behavioral of enc is
begin
p1:process(d,e)
begin
if(e='1')then
case d is
when "10000000" =>z<="000";
when "01000000" =>z<="001";
when "00100000" =>z<="010";
when "00010000" =>z<="011";
when "00001000" =>z<="100";
when "00000100" =>z<="101";
when "00000010" =>z<="110";
when "00000001" =>z<="111";
when others=>z<="ZZZ";
end case;
else
z<="XXX";
end if;
end process p1;
end Behavioral;
PIN AND LOGIC DIAGRAM OF IC74X148
74
Truth table of Encoder using IC74X148
EI_
l
1
0
I0_
L
X
X
INPUTS
I1_ I2_
L
L
X
X
X
X
I3_
L
X
X
I4_
L
X
X
I5_
L
X
X
I6_
L
X
X
I7_
L
X
0
A2_
L
1
0
OUTPUTS
A1_ A0_
L
L
1
1
0
0
GS_
L
1
0
EO_
L
1
1
0
0
0
0
0
0
0
0
X
X
X
X
X
X
0
1
X
X
X
X
X
0
1
1
X
X
X
X
0
1
1
1
X
X
X
0
1
1
1
1
X
X
0
1
1
1
1
1
X
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
75
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
ENCODER OUT PUT WAVE FROM
RESULT :
VIVA QUESTIONS
1.
2.
3.
4.
5.
6.
7.
What is the Difference between Encoder and Decoder?

What is the application of priority Encoder?
What are the Data Objects in VHDL?
Convert 1100 1100 1112 into a Floating point number?
What is the difference between signal and variable?
Define Delta delay?
Which is the recent XILINIX Version?
Exp.No. 4
Exe.No.
MULTIPLEXER/DEMULTIPLEXER
Dt.
76
4.(A). 8X1 MULTIPLEXER- 74151

AIM:
1. To simulate 8x1 multiplexer using VHDL software.
TOOLS :
VHDL Software XILINX 9.2I
MODELSIM simulator
PROCEDURE:
1. Write a VHDL program for 8x1 multiplexer.
2. Simulate the code by using MODELSIM simulator.
3. Draw the waveforms separately.
library IEEE;
entity MUX8X1 is
Port ( I : in std_logic_vector(7 downto 0);
S : in std_logic_vector(2 downto 0);
E_L : in std_logic;
Z : buffer std_logic;
ZBAR : buffer std_logic);
end MUX8X1;
architecture MUX8X1_a of MUX8X1 is
begin
process(S,I,E_L)
begin
if E_L='0' then
case S is
when "000"=>Z<=I(0);
when "001"=>Z<=I(1);
when "010"=>Z<=I(2);
when "011"=>Z<=I(3);
when "100"=>Z<=I(4);
when "101"=>Z<=I(5);
when "110"=>Z<=I(6);
when "111"=>Z<=I(7);
77
when others =>Z<='0';

end case;
else
Z<='0';
end if;
end process;
ZBAR<=not Z;
End MUX8X1_a;
PINDIAGRAM OF IC74X151
LOGIC DIAGRAM OF IC74X151
78
TRUTH TABLE FOR 8*1 MULTIPLEXER
Enable
H
L
L
L
L
L
L
L
L
S2
X
L
L
L
L
H
H
H
H
INPUT
S1
X
L
L
H
H
L
L
H
H
OUTPUT
ZBAR
Z
H
L
I0
I0
I1
I1
I2
I2
I3
I3
I4
I4
I5
I5
I6
I6
I7
I7
S0
X
L
H
L
H
L
H
L
H
8*1 MULTIPLEXER OUTPUT WAVEFORM
VIVA QUESTIONS
1.
2.
3.
4.
5.
6.
7.
Implement F(a,b,c) = 0,2,4,7 ,6 using 2 to 4 multiplexer?

What is the difference between multiplexer and Demultiplexer?
What are the application s of multiplexer?
What is the function of IC74x157?
What is Configuration?
What is the application of Package?
What is the Difference between sequential statement and concurrent statement?
79
4.B. 1 TO 4 DEMULTIPLEXER
AIM:
1. To simulate 1 to 4 Demultiplexer using VHDL.
TOOLS:
MODELSIM simulator
PROCEDURE:
1. Write VHDL program for 1 to 4 demultiplexer.
3. Draw the waveforms obtained.
.
PROGRAM:
library IEEE;
entity DMUX is
Port ( E : in std_logic;
D: in std_logic;
S : in std_logic_vector(1 downto 0);
Y : out std_logic_vector(3 downto 0));
end DMUX;
architecture Behavioral of DMUX is
begin
process(E,S,D)
begin
if E='0' then
Y<="0000";
end if;
if E='1' then
case S is
when "00"=>Y(0)<=D;
80
when 01=>Y(1)<=D;
when 10=>Y(2)<=D;
when 11=>Y(3)<=D;
when others =>Y<=0000;
end case;
end if;
end process;
end Behavioral;
LOGIC DIAGRAM OF 2 TO 4 DEMULTIPLEXER:
TRUTH TABLE FOR 1 TO 4 DEMULTIPLEXER
Enable
0
1
1
1
1
S1
X
0
0
1
1
S0
X
0
1
0
1
Y0
0
D
0
0
0
Y1
0
0
D
0
0
Y2
0
0
0
D
0
Y3
0
0
0
0
D
81
1 TO 4 DEMULTIPLEXER OUTPUT WAVEFORM
RESULT:
VIVA QUESTIONS
1. Where do you prefer Behaviour model?

1. Which model uses the Process Statement?
2. What are the applications of Demultiplexer?
3. Declare the component 2 input OR-Gate?
4. Where do you prefer structural model?
5. What are different Libraries inVHDL?
6. What is the difference between Decoder and Demultiplexer?
82
Exp.No. 5
4-BIT COMPARATOR-7485
Exe.No.
Dt.
AIM:
1. To simulate 4-Bit Comparator using VHDL Software.
TOOLS REQUIRED:
1. VHDL Software XILINX 9.2I
2. MODELSIM simulator.
PROCEDURE:
1.
2.
3.
4.
5.
6.
Write a VHDL Program for 4 Bit-Comparator.

Simulate the code using MODELSIM simulator.
Take IC 7485.
Make connections on Board.
Switch ON the 5V dc supply.
Verify the functionality of IC 7485 by comparing the
two 4-Bit binary numbers.
7. Record the results.
PROGRAM:
library IEEE;
entity COMP4 is
Port ( A : in std_logic_vector(3 downto 0);
B : in std_logic_vector(3 downto 0);
ALTBIN : in std_logic;
AEQBIN : in std_logic;
AGTBIN : in std_logic;
ALTBOUT : out std_logic;
83
AEQBOUT : out std_logic;

AGTBOUT : out std_logic);
end COMP4;
architecture Behavioral of COMP4 is
begin
process(A,B,ALTBIN,AEQBIN,AGTBIN)
variable ALTB,AEQB,AGTB : std_logic;
begin
ALTB :=0;
AEQB :=0;
AGTB :=0;
if A=B then AEQB:=1;
end if;
if A>B then AGTB:=1;
end if;
if A<B then ALTB:=1;
end if;
ALTBOUT<=ALTB OR (AEQB AND ALTBIN);
AEQBOUT<=AEQB OR AEQBIN;
AGTBOUT<=AGTB OR (AEQB AND AGTBIN);
end process;
end Behavioral;
PIN DIAGRAM OF IC7485
84
LOGIC DIAGRAM OF 4 -BIT COMPARATOR
85
86
4 BIT COMPARATOR OUTPUT WAVEFORM
RESULT :
VIVA QUESIONS
1.
2.
3.
4.
5.
6.
Which IC is 8 bit Comparator?

How many IC74x85 s required designing 16-bit comparator?
How much is input data for IC74x85 comparator?
Give examples for signal assignment statement and variable assignment statement.
Where do you use deffered constant?
What is STD_LOGIC?
87
7. What are the values in STD_LOGIC?
Exp.No. 6
D-FLIP-FLOP (IC 7474)
Exe.No.
Dt.
AIM: 1.To simulate positive Edge-Triggered D-flip-flop using VHDL.
TOOLS:
MODELSIM simulator
PROCEDURE:
1.
2.
3.
4.
5.
6.
Write VHDL program for positive Edge triggered D flip-flop.

Simulate the program by using MODELSIM simulator.
Draw the wave forms obtained.
Take IC 7474.
Make connections on breadboard.
Verify the truth table of IC 7474.
PROGRAM:
Librarary IEEE;
entity DFF is
Port ( D : in std_logic;
CLK : in std_logic;
CLR : in std_logic;
PRE : in std_logic;
Q : out std_logic;
QBAR : out std_logic);
end DFF;
88
architecture Behavioral of DFF is

begin
process(D,CLK,CLR,PRE)
begin
if CLR=0 AND PRE=0 then
Q<=1;
QBAR<=1;
elsif CLR=0 then
Q<=0;
QBAR<=1;
elsif PRE=0 then
Q<=1;
QBAR<=0;
elsif CLK=1 AND CLKEVENT then
Q<=D;
QBAR<=NOT D;
end if;
end process;
end Behavioral;
PIN AND LOGIC DIAGRAMOF IC7474
89
TRUTH TABLE FOR D FLIP-FLOP

INPUT
PRESET
0
1
0
1
1
CLEAR
1
0
0
1
1
CLOCK
X
X
X
D
X
X
X
1
0
OUTPUT
Q
1
0
INVALID
1
0
QBAR
0
1
0
1
D FLIP-FLOP OUTPUT WAVEFORM
RESULT:
VIVA QUESTIONS
1.
2.
3.
4.
5.
6.
7.
90
What is the difference between latch and flip-flop?

What is the characteristic equation of D flip-flop?
Design D flip-flop using RS flip-flop?
What is meant by the statement clock=1 and clockevent?
What is the difference between function and procedure?
Which model uses with select statement?
What is meant by race around condition?
Exp.No. 7
JK-FLIP-FLOP(IC-74X109)
Exe.No.
Dt.
AIM: 1.To simulate JK flip-flop using VHDL.

TOOLS:
MODELSIM simulator
PROCEDURE:
1.
2.
3.
4.
5.
6.
Write VHDL program for JK flip-flop.

Simulate the program by using MODELSIM simulator.
Draw the wave forms obtained.
Take IC 74x109.
Make connections on breadboard.
Verify the truth table of IC 74x109
.
PROGRAM:
library IEEE;
entity jkff is
Port ( clk,j,k,rst : in BIT;
q,qbar : inout BIT);
end jkff;
architecture Behavioral of jkff is
91
begin
process(j,k,clk,rst,q,qbar)
begin
if(rst=1)then
q<=0;
qbar<=1;
elsif(clk=1 and clkevent)then
if(j=0and k=0)then
q<=q;
qbar<=qbar;
elsif(j=0and k=1)then
q<=0;
qbar<=1;
elsif(j=1and k=0)then
qbar<=0;
q<=1;
else
q<=not q;
qbar<=not qbar;
end if;
end if;
end process;
end Behavioral;
PIN DIAGRAM OF IC 74x109
92
CLOCKED JK FLIP-FLOP USING NAND GATES
93
TRUTH TABLE FOR JK FLIP-FLOP
CLOCK
CLEAR
QBAR
JK FLIP-FLOP OUTPUT WAVEFORM
RESULT:
94
VIVA QUESTIONS
1.
2.
3.
4.
5.
6.
7.
How do you design T flip-flop using JK flip-flop?

Write characteristic equation for JK flip-flop?
How do you eliminate race around condition in JK flip-flop?
What is meant by toggle conditon in JK flip-flop?
Which IC s are JK flip-flops?
Which model uses Case Statement?
What is the difference between entity and package?
Exp.No. 8
Exe.No.
DECADE COUNTER-7490
Dt.
95
AIM: 1.To simulate Decade counter using VHDL software.
TOOLS:
MODELSIM simulator
PROCEDURE:
1. Write VHDL program for Decade counter.
3. Take IC 7490.
4. Make connections using breadboard.
5. Switch ON the +5V DC supply.
6. Verify the truth table by applying the clock cycles.
PROGRAM:
GENERAL METHOD
library IEEE;
entity decadecounter is
generic(n:integer:=10);
Port ( clk,clr,pre: in std_logic;
q : out std_logic);
end decadecounter;
architecture Behavioral of decadecounter is
begin
process(clk,clr,pre)
96
variable temp: integer range 0 to n;

begin
if(clr =1)then
temp:=0;
elsif(pre=1 ) then
temp:=n-1;
elsif clk=0 and clkevent then
temp:=temp+1;
if temp =n then
temp:=0;
end if;
end if;
q <= temp;
end process;
FOR IC 7490
library IEEE;
entity ic7490 is
Port ( clk1,clk2 : in std_logic;
q:inout std_logic_vector( 3 downto 0);
Nq:inout std_logic_vector( 3 downto 0));
end ic7490;
architecture Behavioral of ic7490 is
component jkff is
port(j,k,clk : in std_logic;
97
q :inout std_logic ;
nq : inout std_logic);
end component;
component and2 is
port( a,b: in std_logic;
c:out std_logic);
end component;
signal s1,s2:std_logic;
begin
j1:jkff port map('1','1',clk1,q(0),open);
j2:jkff port map(s1,'1',q(0),q(1),open);
j3:jkff port map('1','1',q(1),q(2),open);
j4:jkff port map(s2,'1',q(0),q(3),s1);
a1:and2 port map(q(1),q(2),s2);
end Behavioral;
AND GATE:
library IEEE;
entity and2 is
Port ( a,b : in std_logic;
c : out std_logic);
end and2;
architecture Behavioral of and2 is

begin
c<= a and b;
98
end Behavioral;
JKFF:
library IEEE;
entity jkff is
Port ( j,k,clk : in std_logic;
q :inout std_logic :='0';
nq : inout std_logic:='1');
end jkff;
architecture Behavioral of jkff is

begin
process(j,k,clk)
begin
if clk='0' and clk'event then
if j='0' and k='0' then
q<=q;nq<=nq;
elsif j='1' and k='0' then
q<='1';nq<='0';
q<='0';nq<='1';
q<=not q;nq<=not nq;
else
q<=q;nq<=nq;
end if;
99
end if;
end process;
end Behavioral;
end behavioral;
PIN DIAGRAM OF IC7490
LOGIC DIAGRAM OF IC 7490
100
TRUTH TABLE FOR DECADE COUNTER
PR
E
CL
R
CL
K
QD
QC
QB
QA
DECADE COUNTER SIMULATED OUTPUT WAVEFORM
101
RESULT:
V IVA QUESTIONS
1.
2.
3.
4.
5.
6.
7.
What is the difference between synchronous counter and asynchronous counter?

What is the difference between register and counter?
What is the modulus of decade counter?
Can you design 3 bit counter using IC7490?
Declare file data type?
What are the different modes in file declaration?
Where do you use access data type?
102
Exp.No. 9
Exe.No.
UNIVERSAL SHIFT REGISTER-74194
Dt.
AIM:
1. To simulate the 4-bit shift register using VHDL software.
TOOLS :
VHDL Software XILINX 9.2I
MODEL SIM simulator
PROCEDURE:
1. Write a VHDL program for a Universal Shift Register.
2. Run the program.
3. Simulate the code by MODEL SIM simulator.
4. Take IC 74194.
5. Make connections in Bread Board.
6. Switch ON the +5V dc supply.
7. Verify the truth table by varying the inputs.
PROGRAM
library IEEE;
103
entity unishftreg is
Port ( clr_l : in std_logic;
clk : in std_logic;
sh_ld : in std_logic;
i : in std_logic_vector(3 downto 0);
j : in std_logic;
k : in std_logic;
q : out std_logic_vector(3 downto 0));
end unishftreg;
architecture Behavioral of unishftreg is

begin
process(clr_l,clk,sh_ld,i,j,k)
variable temp:std_logic_vector(3 downto 0);
begin
if clr_l='0' then
temp:="0000";
elsif clk='1' and clk'event then
if sh_ld='0' then
temp:=i;
elsif (j and k)='0' then
temp:=temp(2 downto 0)&'0';
else
temp:=temp(2 downto 0)&'1';
104
end if;
end if;
q<=temp;
end process;
end Behavioral;
PIN DIAGRAM OF IC 74X194:
LOGIC DIAGRAM OF IC 74X194:
105
TRUTH TABLE FOR UNIVERSAL SHIFT REGISTER

CLEAR
SH/LD
CLOCK
FUNCTION
Asynchronous
clear
No change in input
Load input data
Shift from QA
toward QD, QA = 0
Shift from
QDtoward QA, QA =
106
UNIVERSAL SHIFT REGISTER OUTPUT WAVEFORM
RESULT:
VIVA QUESTIONS
1.
2.
3.
4.
5.
6.
What are the applications of IC74X194?

How do you design Ring counter using IC74X194?
How many states are there in 4-bit ring counter?
How do you design Johnson counter?
How many states are there in 4-bit Johnson Counter?
If x=10 then
Y<=0;
End if;
Write Equivalent concurrent statement.
7.
107
Declare package with one component and one function.
ASSIGNMENT
1.T FLIP-FLOP
2.RS FLIP-FLOP
3.RING COUNTER
4,JOHNSON COUNTER
5.UP/DOWN COUNTER
6.4TO16 DECODER
7.16X1 MULTIPLEXER
8.MEALY FSM
9.MOORE FSM
10.SERIAL IN SERIAL OUT SHIFT REGISTER
108
APPENDIX - A
A1. INTRODUCTION TO OP-AMP
An Op-Amp is a direct coupled High gain differential amplifier which amplifies the
difference between two input voltages. It was originally designed for computing mathematical
operations such as addition, subtraction, multiplication, division, integration, differentiation, log
and anti-log operations hence the name Operational Amplifier.
Circuit Symbol:
Basic Information of Op-Amp :

1. The Op-Amp has the following terminals:
Two input terminals INV & NON-INV terminals ( pins 2 & 3 )
One output terminal V0 (pin 6)
Two Power supply terminals V+ & V (pins 7 & 4)
Two Offset null terminals pins 5 & 8.
2. The output of Op-Amp is proportional to the difference between input voltages applied to
Non-inverting & Inverting terminals of Op-Amp.
V0 ( Vp Vn )
V0 = A ( Vp Vn ) = A
OL
OL
109
vd
3. The signal appearing at INV terminal Vn is inverted at the output i.e., the output has 1800
out of phase with input hence the name INVERTING TERMINAL.
4. The signal appearing at NON-INV terminal Vp has in phase with output hence the name
NON-INVERTING TERMINAL.
5. The Op-Amp responds equally well to both AC & DC input voltages.
Ideal OP-AMP characteristics :

1.
2.
3.
4.
5.
6.
7.
8.
Open loop voltage gain

AOL
=
Input Resistance
Ri
=
Output Resistance
R0
= 0
Common mode rejection ratio CMRR =
Slew rate
SR =
Bandwidth
BW =
Input bias currents
IB1 = IB2 = 0
Input offset voltage
vio = 0
Specifications of Op-Amp A 741 :

The 741 op-amp is originally manufactured by Fair Child and it is sold as A 741
where A represents the manufacturers code. The 741 op-amp is also manufactured by some
other manufacturers. All these have same specifications.
Ex:
National Semiconductor : LM 741,
Motorola: MC 1741
Texas Instruments: SN 52741
Signetics : NS 741
RCA : CA 3741
The different versions of 741 op-amp are :
741
: Military grade Op-Amp
741C : Commercial grade Op-Amp
741A : Improved version of 741
741E : Improved version of 741C
741S : Military grade Op-Amp with high Slew Rate
741CS : Commercial grade Op-Amp with high Slew Rate
Operating Temperature ranges:
Military temperature range
Commercial temperature range
: - 550 C to
: 00 C to
+ 1250 C
+ 750 C
Industrial temperature range
: - 200 C
to
110
+ 850 C
Electrical characteristics of 741 op-amp: ( for VS = 15 V @ 250 C )

1. Input bias current IB = 500 nA (max.)
2. Input offset current Iio = 200 nA (max.)
3. Input offset voltage Vio = 60 mV (max.)
4. Input resistance Ri = 2 M
5. Output resistance R0 = 75
6. CMRR = 90 dB
7. PSRR = 150 V / V
8. Offset voltage drift = 15 V / 0C
9. Offset current drift = 200 pA / 0C
10. Output voltage swing VSat = 13 V for RL > 2 k
11. Slew rate SR = 0.5 V / s
12. Large signal voltage gain AOL = 2 * 105
13. Power consumption = 85 mW.
A2. INTRODUCTION TO IC 555 TIMER
INTERNAL BLOCK DIAGAM OF 555 TIMER:
111
Features of 555 timer:

1.
2.
3.
4.
5.
6.
7.
8.
+ 5 V to + 18 V power supply
High output current ( 200 mA)
Timing from s to hrs
Adjustable duty cycle
Output can drive TTL
Temp.stability of 0.05 % per 10C change in temp.
Reliable and easy to use
Low cost
Applications of 555 timer:

In monostable mode
1. Missing pulse detector
2. Frequency divider
3. Linear ramp generator
4. Pulse width modulator
In astable mode
1. FSK generator
2. Pulse position modulation
3. Square wave generator

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III B.

TECH - I SEM (R09) ECE :

IC APPLICATIONS & ECAD LAB

ADDER, SUBTRACTOR, COMPARATOR CIRCUITS

Name of the equipment

VISVODAYA TECHNICAL ACADEMY, KAVALI

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IC APPLICATIONS & ECAD LAB

Thus output is amplified and inverted sum of two inputs.

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From the Fig.1(b),Vp =

IC APPLICATIONS & ECAD LAB

Referring Fig.1(b), Apply KCL at node n - we have

Thus, the output voltage V0 is equal to the voltage

III B.TECH - I SEM (R09) ECE :

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CIRCUIT DIAGRAM OF ADDER :

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CIRCUIT DIAGRAM OF SUBTRACTOR:

V = (Vb Va) Volts

V = (Vb Va) Volts

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CIRCUIT DIAGRAM OF COMPARATOR :

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Input sine wave

Output square wave

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ACTIVE FILTER APPLICATIONS FIRST ORDER LPF

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Name of the equipment

Let fH = 1 kHz, C = 0.01 F then R = 15.9 k

Pass band gain AF

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Based on input signals

6. Based on the Order of the filter.

Gain and frequency adjustment flexibility

) = pass band gain of filter

f = frequency of the input signal.

III B.TECH - I SEM (R09) ECE :

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This frequency is called as Cut-off frequency/ Break frequency / 3-dB frequency.

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