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lthough CMOS technology is slowly maturing as a competitive RF-IC contender, the lack of
efficient design tools and accurate device models constitutes a major hindrance to commercial
acceptance. These shortcomings are of high importance since they indicate a serious lack of
practical design experience. For successful first-try circuit design, there must be a large degree of
consistency between simulated and measured device performance. Note that CMOS technology barely
offers sufficient performance for typical RF applications and simultaneously suffers from very large
process tolerances. Hence, it is essential that device models are accurate enough to prevent conservative
over-designs. For other types of integrated technologies, e.g. gallium arsenide, high modeling accuracy
has often been achieved by offering only a limited set of devices to the designer. Each of the available
devices is then carefully characterized and a model is created for commercial simulation tools. As RF
CMOS is still in its infancy, such design practice has not yet been adopted and it is questionable if it
ever will. This is particularly evident with active devices where the use of fully scalable model libraries
has manifested itself as a vital part of integrated circuit design. Further, a free choice of device
dimensions allows the designer to approach optimum process performance more closely with low-cost
technologies. For current RF CMOS work, full scalability is thus assumed and much effort is dedicated
to make commercial transistor models - such as BSIM3v3 [1], MM9 [2], and EKV [3] - applicable to RF
design in the gigahertz frequency range.
This paper describes some of the hurdles that must be overcome in order to facilitate fully scalable RF
MOSFET models. First, the paper is initiated with a section on RF MOSFET design issues. The section
discusses the contradictions between (i) layout for optimum RF performance and (ii) layout for high
modeling consistency. Next, a unit transistor layout based on a cluster of fingers is presented which
facilitates scalable modeling. Although such design practice imposes a limitation on the design freedom,
the necessary confinements can be introduced without significantly degrading the device RF
performance. Several measurements on submicron devices are presented in order to validate the
advantages of having a consistent layout and scalability results for a 0.25m bulk process are presented.

Troels Emil Kolding received his M.Sc. and Ph.D. degrees in 1996 and 2000 respectively. He is currently a design engineering
manager with RISC Group Denmark. His research interests include RF CMOS technology and techniques.

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Although many recently published modeling innovations have proven their validity in practical modeling
situations [1]-[4], they are not sufficient means to facilitate complete modeling scalability. The main
problem is that the designer has the full freedom to optimize the transistor layout with any desirable
performance criteria in mind. This leads to extrinsic parasitics that are very significant for the device
performance at gigahertz frequencies. Unfortunately, these parasitics are often very hard to predict in
practice and thus very difficult to add manually during simulations. Hence, a scalable model is only fully
applicable if it takes into account these effects and, hence, the specific layout of the device. In BSIM3v3
some extrinsic effects, e.g. diffusion implants, may be specified in terms of drawn dimensions. However,
other very significant effects, such as bulk effects and gate resistance, are not considered and currently
compensation is conducted through ballpark estimates or optimization techniques. This is a precarious
situation since it requires that each device be considered individually. In the following, the different RF
transistor layout techniques are discussed.
One important layout technique, which is often applied to improve the layout of large RF transistors, is
PXOWLILQJHUGLVWULEXWLRQ illustrated in Figure 1. By distributing the total gate width into smaller parallel
transistors, significant reduction of gate resistance and parasitic junction effects is achieved [6]. These
improvements translate into higher cutoff and maximum oscillation frequencies as well as lower device
noise [5,6]. Common practice includes the use of contacts on both sides of the gate fingers. This
configuration leads to an overall gate resistance of [6]
: SRO\
5J =
,
12 1 2 /
where SRO\ is the resistivity of the poly-silicon gate material (typically 5-20/sq), : and / are the total
width and length of the gate, and 1 is the number of parallel fingers. Note that a large reduction is
achieved by increasing 1 and values below 1-2 may easily be achieved for typical RF transistors.
Although the above equation immediately indicates that a very small finger width is optimum, the exact
choice of configuration (e.g. number of fingers) is a tradeoff between the gate resistance and other
effects. Consequently, there is no single generic way to layout an RF-optimum transistor.

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A drawback of distributing the transistor into many parallel structures is that (i) the extrinsic gate-bulk
parasitics increase and (ii) more gate-source and gate-drain overpasses are required. In Figure 2b, this
aspect is illustrated. Hence, extrinsic fringing effects are increased by employing multi-fingered layouts
and thus a tradeoff between gate resistance and fringing effects is required in practice. These issues
become very critical at gigahertz frequencies and the transistor performance depends significantly on the
layout when used in RF applications. This aspect is illustrated in Figure 2a, which shows the extracted
gate-drain susceptance for a 300x0.5 micron NMOSFET configured with a different number of fingers
(from 10 to 50). It is clear from the 30% variation depicted in Figure 2a, that a specification of just
transistor length and width is inadequate to completely describe its operation.

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Another important effect at gigahertz frequencies is associated with the substrate under the transistor. As
has been generally accepted in the RF CMOS community, accurate modeling of the transistor bulk
region is essential to obtain good RF models [1]-[4]. A cross-section of a single-finger transistor is
shown in Figure 3 and it is seen that there is a non-zero distance between the nearest substrate contact
placed by the designer and the intrinsic bulk just below the channel to which the modeling equations
refer (the back-gate). The corresponding resistance is a complicated function of the process parameters
and may be quite large for technologies offering good device isolation; e.g. VKDOORZWUHQFKLVRODWLRQ
processes. Due to a relatively low transconductance per drain current, RF transistors are usually large
enough to render the resistive and dielectric substrate losses very important for device operation in the
gigahertz range. The cause is the relatively large junction capacitance of the drain and source implants
which brings the substrate impedance into play. Consideration of these effects is particularly important
for accurate modeling of the output characteristics of the MOSFET [1]-[4]. In general, the bulk
interaction for a particular process is a complicated function of the individual transistor layout including
the placement of bulk contacts. Usually, substrate contacts are placed for every 3-6 fingers in a multifinger layout in order to make the device less susceptible to substrate-carried noise. By this approach,
the bulk resistance to the nearest ground strap is also reduced without sacrificing too much of the
parasitic reduction which is gained by sharing source and drain diffusion areas among gates.

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From observing the large importance of these layout-induced effects, it is clear that a viable solution
must be sought. The designer may manually add fringing and other effects to the model. However, this is
a tedious and complicated solution for large designs. Alternatively, the model may include an interface
to specify the layout configuration of the device. However, as shall be evident from the following,
extrinsic effects are not described by simple layout relations. Hence, the ultimate solution is to design
transistors that are scalable in intrinsic as well as extrinsic effects. This is the approach studied here.

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As may be appreciated from the previous discussion, the designer may improve the transistor
performance by choosing a particular layout of the device. One of the main benefits from applying a
large number of fingers is a reduction of gate resistance. However, for very large values of 1, the effects
of extrinsic gate-source and gate-drain underpasses start to become a large fraction of the intrinsic
(desired) effects since each gate becomes very narrow. Hence, 1 should not be chosen only with gate
resistance in mind. Previously published results have shown that a finger width around 10m gives an
optimization of the maximum oscillation frequency of a device [5]. However, as is evident from the
results in Table 1, the same finger width is not optimum for all total transistor widths; even if the
maximum oscillation frequency is the solely considered parameter.
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For narrower transistors it appears that a smaller finger width is desirable since the gate resistance
dominates the value of the maximum oscillation frequency. For wider transistors, the number of parallel
fingers is so large that the gate resistance is reduced to significant levels even for longer finger widths.
Hence, the maximum oscillation frequency is now dominated by extrinsic effects associated with
fringing and bulk parasitics. Consequently, a larger finger width is desirable in order to reduce the ratio
of extrinsic effects to intrinsic effects. Note that the results of Table 1 cannot be generally applied as the
optimum configuration depends on the specific process parameters.
Note from this treatment that the number of fingers is a complicated parameter that involves several
trade-offs. In the above case only the maximum oscillation frequency was considered and inclusion of
noise and nonlinearity issues further complicate the scenario. The optimum finger width does not appear
to remain constant regardless of :. This complicates the achievement of consistent effects and scalable
modeling as shall be evident from the following section.

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With model scalability set as the main goal, it is essential that transistors of different sizes have scalable
intrinsic as well as extrinsic parasitics. In this context, only transistors of minimum length are
considered which is the typical choice for RF applications. However, the specified layout methods are
generally applicable to other values of / as well. Consequently, the goal is to achieve full scalability in
: for constant values of /. In order for all significant transistor effects to be scalable, the following
conditions must be fulfilled:

The ratio of extrinsic to intrinsic effects must remain constant regardless of the value for :.

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The extrinsic effects, including underpass fringing, contact resistances, bulk effects, and gate
interconnects, must be proportional to : (parallel effects) and 1/: (series effects).
The gate resistance must scale inversely with :. A limitation to this can be QRQTXDVLVWDWLF
(NQS) effects that are most visible for large transistor widths or at higher frequencies.

In order to achieve the above conditions, it is required that some layout restraints are introduced. For a
scalable configuration it is required that finger length remains constant. Further, it is essential that the
number of fingers between substrate contacts is consistent. A way to accomplish this is to base all
transistors on a unit FOXVWHURIILQJHUV (COF). An example COF is illustrated in Figure 4a.
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Larger transistor widths are accomplished by parallel coupling the COF instances. Note that by basing
all transistors on a unit COF, the design flexibility is reduced. There are several disadvantages including:
(i) Only widths that are a multiple of the COF width can be implemented and (ii) the COF configuration
may not be optimum for all transistor widths. To overcome these disadvantages in practice it usually
suffices to design 2-3 different COF instances to cover different width ranges and applications. Typical
COF design guidelines are listed in Table 2. However, note that the values are very dependent on the
particular type of process. Although some performance is lost by introducing high layout consistency,
the derived advantages of scalability are usually important enough to justify this approach in practice.
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In order to illustrate the above concepts, several transistors have been fabricated in a 0.25m bulk
polycide CMOS process. The process uses tungsten for its bottom metal layer, which has a lower
conductivity than other aluminum-composites. Further, the resistivity of the polycide is a little higher
than for many other similar processes. Due to these significant series effects, it has been estimated that
best performance for transistors up to around 200 micron is achieved for finger widths around 5m.
Hence, all transistor designs presented here are based on a 4-fingered COF with a finger length of 5m.
The corresponding gate resistance for a single COF is estimated from the electrical specification
document to typically 2.3; including contacts. Eight common-source NMOSFETs have been fabricated
with very different widths, ranging from 40-320 micron. Using a calibrated vector network analyzer, the
scattering parameters have been measured over a large frequency and bias range. Note that in order to
verify scalability, different transistors must be given the same bias voltages. Transistor performance is

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not generally scalable for constant bias current. Very careful de-embedding has been conducted to take
into account contact effects and test-fixture parasitics. For verification of scalability down to very small
transistor widths, very accurate de-embedding is required in order not to offset results. In order to
facilitate a more intuitive comparison, the measured scattering parameters have been converted into
admittance (<) parameters. These Y-parameters have been converted into the quasi-static equivalent
parameters illustrated in Figure 5 [6] by the method of reference [4]. A resistor has been added to denote
the bulk effects and the representation appears to be valid at the frequencies considered in this paper.

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The extracted results at 2.5GHz are shown in Figure 6. The different admittances of Figure 5 have been
plotted as a function of : in order to verify scalability. One exception is the gate resistance that is
plotted versus 1/: as the series effects should be inversely proportional to : in order to facilitate total
scalability. Two different bias conditions have been considered; one in the triode region and one in the
saturation region. All eight transistors are located close to each other on the die in order to reduce
tolerances. Still some variation will take place and as only one set of transistors has been measured this
is even visible from the results. Since the small deviations appear random, it is assumed that tolerances
constitute the main cause. From considering the plots of JP, <JV, <JG, and <GV in Figure 6 the results
appear very satisfactory. The gate-drain admittance displays a close fit to the expectations thereby
indicating a high level of consistency with respect to extrinsic fringing effects per unit width. Note that
since <GV is significantly affected by the bulk resistance at the given frequency (this has been verified in
the S-parameter domain), it appears that the careful COF layout indeed gives scalable bulk effects. This
has also been verified by the direct measuring approach proposed in reference [7]. For this particular
COF, the substrate coefficient was extracted to 3.2mm for the bias point in the triode region and
3.4mm for the bias point in the saturation region. By applying a higher drain bias, the expanded
depletion zone gives an increased distance between intrinsic and extrinsic bulk regions. Consequently,
the bulk resistance increases. Usually one generic coefficient may be used throughout the practical bias
range with adequate accuracy [7].
Although admittances and the bulk resistance appear to scale accurately with device width, this
apparently is not the case for the gate resistance 5J. The resistance appears to be inversely proportional
to the gate width only for the smallest transistors. As the particular COF has been designed for very low
gate resistance, it appears that the input resistance for larger devices is dominated by distributed channel
effects rather than the resistivity of the polycide [8]. Hence, the curve appears to flatten out as the width
is increased and scalability is not fulfilled for this particular parameter. For longer channel lengths, it has
been verified that these effects become even more pronounced. For simplicity, it appears to be a good
solution to extract only a single value of 5J for each bias point regardless of the width. For the presented
bias conditions, it appears that a value around 1.5 is a sound choice. While considering the absolute
values for gate resistance, it should generally be noted that the extraction of 5J is associated with great

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difficulty and that the accuracy of this parameter is typically quite low at the present frequency. With the
high level of scalability indicated by Figure 6, it seems reasonable to present the parameters in terms of
transistor width. This has been done in Table 3 for the considered bias points. Note that in general the
presented extraction results are only valid at one bias point and one frequency. For lower frequencies
where quasi-static operation can be assumed, it usually suffices to represent the admittances by a
corresponding capacitor thereby facilitating a frequency-independent description.
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This paper has indicated the significant difference between device layout minded for performance and
device layout minded for consistency. A high level of consistency is required if compact models are to
address the extrinsic MOSFET parasitics which are of high importance to gigahertz modeling. These
parasitics include extrinsic fringing effects, gate resistance, and bulk effects. As most extrinsic effects
are strongly related to the specific transistor layout, it is vital that transistors are based on a unit
configuration in order to facilitate scalability at the device level. By utilizing the proposed cluster of
fingers, it is possible to obtain high scalability without significantly degrading the device performance.
By using high layout consistency, it is possible to extract general process/layout parameters that may be
added to compact model formulations. One limitation to obtaining scalability appears to be the nonquasi-static effects that prevent the gate resistance from being scalable for large transistor widths.
However, it appears that extracting a constant value for the gate resistance gives sufficiently accurate
results when the resistance is low.


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W. Liu, R. Gharpurey, M. C. Chang, U. Erdogan, R. Aggarwal, and J. P. Mattia, R.F. MOSFET Modeling Accounting for
Distributed Substrate and Channel Resistances with Emphasis on the BSIM3v3 SPICE Model, LQ 7HFKQLFDO 'LJHVW RI
,QWHUQDWLRQDO(OHFWURQ'HYLFHV0HHWLQJ,('0, (San Francisco, California, USA), pp. 309-312, December 1997.
L. F. Tiemeijer, L. M. F. de Maaijer, R. van Langevelde, A. J. Scholten, and D. B. M. Klaassen, RF CMOS Modelling,
LQ3URFHHGLQJVRI:RUNVKRSRQ$GYDQFHVLQ$QDORJ&LUFXLW'HVLJQ$$&', (Nice, France), pp. I.1-I.20, March 1999.
C. Enz and Y. Cheng, MOS Transistor Modeling Issues for RF Circuit Design, LQ 3URFHHGLQJV RI :RUNVKRS RQ
$GYDQFHVLQ$QDORJ&LUFXLW'HVLJQ$$&', (Nice, France), pp. IV.1-IV.26, March 1999.
S. H.-M. Jen, C. C. Enz, D. R. Pehlke, M. Schrter, and B. J. Sheu, $FFXUDWH0RGHOLQJDQG3DUDPHWHU([WUDFWLRQIRU
0267UDQVLVWRUV9DOLGXSWR*+] IEEE Transactions on Electron Devices, vol. 46, pp. 2217-2227, November 1999.
C. S. Kim, H. K. Yu, H. Cho, S. Lee, and K. S. Nam, CMOS Layout and Bias Optimization for RF IC Design
Applications, LQ3URFHHGLQJVRI,(((0776, (Denver, Colorado, USA), pp. 945-948, 1997.
Y. Tsividis, 2SHUDWLRQDQG0RGHOLQJRIWKH0267UDQVLVWRU, McGraw-Hill, Inc., 2nd ed., 1999.
T. E. Kolding, Test Structure for Universal Estimation of MOSFET Substrate Effects at Gigahertz Frequencies, LQ
3URFHHGLQJVRI,(((,QWHUQDWLRQDO&RQIHUHQFHRQ0LFURHOHFWURQLF7HVW6WUXFWXUHV,&076, (Monterey, California, USA),
March 2000.
X. Jin, J.-J. Ou, C.-H. Chen, W. Liu, M. J. Deen, P. R. Gray, and C. Hu, An Effective Gate Resistance Model for CMOS
RF and Noise Modeling, LQ 7HFKQLFDO 'LJHVW RI ,QWHUQDWLRQDO (OHFWURQ 'HYLFHV 0HHWLQJ ,('0, (San Francisco,
California, USA), pp. 961-964, December 1998.