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Ramya N2
AbstractThis paper presents logic level estimators of leakage current for nanoscale digital standard cell circuits. Here
the proposed estimation model is based on the characterization of internal node voltages of cells and the characterization
of leakage current in a single Field-Effect Transistor (FET). Finally the estimation model allowed direct implementation of
supply voltage variation impact on leakage current and output voltage drop (loading effect).The technique is feasible for
implementation in Hardware Description Language (HDL) and HDL cell models supporting leakage estimation at
simulation time.
Index Terms FET, HDL, Leakage current, Standard cell
1 INTRODUCTION
3 METHODOLOGY
This approach presents Logic-level estimators of the leakage current,
in nanoscale standard cell based designs.
Very accurate
characterization of the leakage current in a single FET is
straightforward.
108
QP
QN
Q1
3.2
OUT
GND
Fig. 1. Equivalent circuit for voltage drop calculation
B
C
GND
Fig. 2. Stacks of three N-type transistors
109
CONCLUSION
ACKNOWLEDGMENT
The author wish to thank N. Ramya and Dr.P. Thiruvalarselvan for
fruitful discussions.
REFERENCES
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[6]
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