Analog Integr Circ Sig Process

DOI 10.1007/s10470-009-9357-z

Design of improved rail-to-rail low-distortion and low-stress

switches in advanced CMOS technologies
A. Galhardo J. Goes N. Paulino

Received: 27 November 2008 / Revised: 15 May 2009 / Accepted: 28 July 2009

Springer Science+Business Media, LLC 2009

Abstract This paper describes the efficient design of an

improved and dedicated switched-capacitor (SC) circuit
capable of linearizing CMOS switches to allow SC circuits
to reach low distortion levels. The described circuit (SC
linearization control circuit, SLC) has the advantage over
conventional clock-bootstrapping circuits of exhibiting
low-stress, since large gate voltages are avoided. This
paper presents exhaustive corner simulation results of a SC
sample-and-hold (S/H) circuit which employs the proposed
and optimized circuits, together with the experimental
evaluation of a complete 10-bit ADC utilizing the referred
S/H circuit. These results show that the SLC circuits can
reduce distortion and increase dynamic linearity above
12 bits for wide input signal bandwidths.
Keywords Switch linearization
Reliability

Switched-capacitor linearization control circuit (SLC)

Bootstrapped switch
Clock boosting

1 Introduction
Present and emergent CMOS technologies require the use of
low supply voltages. This means that it is necessary to guarantee that the linearity of the switches in the signal path is kept

A. Galhardo (&)
DEEA Instituto Superior de Engenharia de Lisboa, Lisbon,
Portugal
e-mail: galhardo@deea.isel.ipl.pt
J. Goes
N. Paulino
DEE-FCT-UNL/CTS-UNINOVA, Faculdade de Ciencias e
Tecnologia da Universidade Nova de Lisboa, Monte da
Caparica, Portugal
e-mail: jg@uninova.pt

over rail-to-rail signal swings, needed in many low-voltage

switched-capacitor circuits (SC), spanning from 10-14b
ADCs to accurate analog filters. Using large NMOS and
PMOS switches (CMOS transmission-gates), i.e., devices
with large channel widths, can provide enough conductivity
during the sampling and charge transfer operations. However, the variation of the conductance of the implemented
switches (specially the sampling switches) over the entire
signal swing is directly translated into harmonic distortion.
In order to reach such dynamic linearity levels, clockboosting techniques are traditionally employed, which consist
of using dedicated SC circuits for improving the lack of linearity of the switches. This operation basically relies on
boosting the control gate voltage of a single-transistor NMOS
switch beyond the power supply voltage value (VDD). As a
major consequence, the reliability constraints of the technology have to be taken into account, avoiding over-stressing the
CMOS devices by applying large voltages (higher than VDD)
to the gates of the transistors. This paper addresses these
challenges, using a simple SC linearization control circuit
(SLC) that generates suitable gate control voltages to drive a
CMOS transmission-gate, within the maximum allowed
technology limits. The proposed circuit can be readily used in
any advanced CMOS technologies for improving the dynamic
linearity of low-voltage high-swing CMOS switches.
Section 2 reviews the traditional clock-bootstrapping
techniques and describes the main principle behind the new
switch linearization circuit solution proposed in this paper.
Section 3 describes a practical design methodology for the
optimum sizing of the proposed switch-linearization circuits.
Section 4 shows exhaustive simulation results over processsupply and temperature (PVT) corners and discusses about
reliability related issues. Finally, Sect. 5 describes the integrated prototypes and the corresponding experimental
evaluation and, Sect. 6 draws the main conclusions.

123

Analog Integr Circ Sig Process

2 Review of the existing switch-linearization

techniques and proposed circuit solution

90

In CMOS technology a switch can be built by paralleling a

NMOS and a PMOS device [1]. The first advantage of
having a CMOS switch (also known as a CMOS transmission gate) rather than a single-channel MOS switch is that
the dynamic analog signal range in the ON state is greatly
increased as illustrated by the conductance curves (dashed
lines) in Fig. 1. These conductance curves are obtained from
an electrical simulation using a standard 1.2 V 130 nm
CMOS technology and BSIM3v3 models, with VTN &
0.38 V, |VTP| & 0.33 V. The NMOS and PMOS devices are
respectively sized with aspect ratios of 20/0.13 and 80/0.13.
A CMOS switch allows a full signal-swing. However, in
deep submicron CMOS technologies and at low voltage, the
equivalent switch conductance, gEQ, has a huge variation,
which translates in a significant harmonic distortion. One of
the reasons relies on the fact that, the drain-to-source conductance, gDS, of a single MOS switch (NMOS or PMOS)
operating in the linear region is a function of the mobility in
the channel, l, the oxide capacitance per unit area, Cox, the
gate width and length, W and L, the gate-to-source voltage,
vGS, the threshold voltage, VT, as represented by gDS
lCox W vGS  VT =L: Scaling the device and lowering the
oxide thickness, the capacitance per unit area is increased
resulting in an increased conductance. However, that is
canceled out by the variation of the effective gate overdrive
voltage vGS  VT : Considering the scaling factor k [2], and
that both the gate-to-source and the threshold voltages are
lowered by 1/k, the conductance is also lowered by 1/k. On
the other hand, as the threshold voltage is not scaling as fast
as the supply and available gate-to-source voltages, the
conductance is deteriorating with scaling. Not only the
maximum achievable conductance is reduced, but also the
linearity of the conductance is highly reduced with supply
voltage, as the relatively increased threshold voltage is
shrinking even more the signal amplitude span. As a consequence, the use of very low signal levels and the use of
common-mode signal levels close to one of the supply rails
become mandatory. Furthermore, the body effect implies a
threshold voltage variation, additionally increasing it for
signal (source-to-bulk) increased voltages, and shrinking
even more the signal swing.
The traditional approach to obtain a nearly constant
conductance is to maintain the gate-to-channel voltage
constant during the ON state. This can achieved using the
clock-boosting techniques (CBT), which consist of using
dedicated SC circuits for boosting the gate voltage of a single
NMOS switch (CBTn case) beyond the power supply to
vg = VDD ? vin [3]. Alternatively, the gate voltage of a
PMOS switch (CBTp case) [4] can also be adjusted to
vg = vin - VDD. This approach has the disadvantage of

70

123

conductance, mS

80

attenuation

60

EQ

linearization

attenuation

50
40
30
20

amplification

amplification

10

pmos
0
0

0.2

0.4

0.6

0.8

nmos
1

1.2

v in , V

Fig. 1 Changes in the NMOS, PMOS and equivalent (gEQ) switches

conductances using the proposed technique versus input signal

applying a voltage larger than VDD to the gate of the transistors; this large voltage over-stress the dielectric of the gate
capacitances potentially causing oxide reliability problems
in long term. Different versions of CBT circuits can be found
in [59] but it is out of the scope of this work, to cover all
types of CBT circuits.
The basic idea behind the SLC circuits, initially described
by the authors in [10], consists of attenuating the gate-tosource voltage and conductance of the NMOS switch (gnmos)
when a low voltage is applied to the input (vin), and amplifying them for higher voltages in the input (solid lines shown
in Fig. 1). The SLCn circuit, driving the NMOS switch (M1),
shown in the bottom part of Fig. 2(a), operates as follows.
When the M1 is ON and the input signal vin is close to VSS,
the n-type SLC block reduces the gate voltage that is applied
to the NMOS switch to a value lower than VDD. As a consequence its conductance is reduced. When vin is close to
VDD, the SLCn circuit increases (softly boosts) the gate
voltage of M1, overcoming the zero-conductance problem of
the NMOS transistors when vin [ VDD - VTN. For the
PMOS switch the process is similar and, instead, a dedicated
SLCp circuit is used (top of Fig. 2(a)). The main goal is to
obtain a nearly constant equivalent conductance gEQ, independent from the voltage variations present in vin.

3 Design methodology for optimum sizing of switch

linearization control (SLC) circuits
3.1 Improved circuit description
As stated in the previous section, the practical implementation of the technique described in the previous section
can be done using the two dedicated SLC circuits (N-type

Analog Integr Circ Sig Process

Fig. 2 N-type and P-type SLC
circuits used for improving the
linearity of the main NMOS
(M1) and PMOS (M2) switches;
(a) simplified schematic; (b)
practical realization

(a)

V DD

(b)

VDD

C2p

VDD

SLCp

2 S3p

S1p

2 S7p

S 2p

C1p

1
C3p

M1p
1n

2 S5p

M2

VDD

2 S5n

2 S6n

C2n

S1n

S 2n

1 S3n

SLCn and P-type SLCp) shown in Fig. 2(b). When compared with the first generation of SLC circuits described by
the authors in [10], the new SLC-BS circuit has been significantly improved. By applying the bulk switching (BS)
technique [11] to the PMOS main switch M2, the body
effect is reduced and the conductance has consequently
increased. On the other hand, adding extra capacitors C3p
and C3n has also made easier, by introducing an extra
degree of freedom to the circuit, the linearization of the
CMOS switch equivalent conductance.
The generated output voltage vgn driving switch M1, is
approximately given by (1) (neglecting parasitic effects),
where C1n, C2n and C3n are small-sized capacitors. Linear
capacitors provided by the technology (either metal-insulator-metal, MiM, or poly1poly2, P1-P2 types) should be
used.
C1n
2C2n C3n
VDD
C1n C2n C3n
C1n C2n C3n

Notice that parasitic capacitances are not considered in this

expression. The main reason is because most technologies
provide good quality linear capacitors with low bottomplate parasitic capacitance (BPPC). This is the case for
example for MiM capacitors (BPPC \ 5%). If other types
of capacitors with large BPPC have to be used instead, the
referred expression has limited accuracy and some fine

2n

M11n 1
2 S7n

C3n

M2
vout

M6n

C1n

M5p

2n

VDD

VDD
1n

C2n

2
M4n
1n

M2n

C1n

M1

M3n

M5n

M1n
1n

2 S 4n

C3p

vin

VDD
M1

M7p

M2p

M6p

VDD
VDD

2n

1
C1p

M11p 1
vout

vin

M3p
M4p

1
2 S6p

vgn vin

2n

C2p
1 S4p

VDD

C3n

2
M7n

SLCn

tuning has to be performed through electrical simulations.

However, expression (1) as well as the other expressions
throughout this section can still provide a quite useful
initial sizing of the capacitance values used in the design of
the SLC circuits.
In the case of the P-type SLC circuit (used to provide
the suitable gate voltage to the PMOS switch) shown in the
upper part of Fig. 2(b), a slightly different linearization
circuit is used to provide the suitable gate voltage vgp,
defined approximately by (2), where C1p, C2p and C3p
represent small capacitors, the smaller one being C1p.
vgp vin

C1p
C2p
VDD
C1p C2p C3p
C1p C2p C3p

In order to keep the capacitance values of the auxiliary

capacitors used in the SLC circuits as low as possible and
within a practical range, the effect of the gate capacitance
of the main switches, Cgn and Cgp, must be taken into
account. The weight of the gate capacitances should be
added to the first terms in (1) and (2). The second terms
should be corrected with the added charge, approximately
the gate capacitance charge at VDD/2. Hence, the SLCn
circuit generates an output voltage vgn to drive the switch,
which is approximately given by (3). The capacitance
ratios K1n and K2n, defined in (3), will be used later for
simplicity.

123

Analog Integr Circ Sig Process

vgn vin

C1n Cgn
2C2n C3n Cgn =2
VDD
C1n C2n C3n Cgn
C1n C2n C3n Cgn
|{z}
|{z}
K1n

K2n

3
The output voltage vgp to drive the PMOS switch, M2, is
given by (4), where the capacitance ratios K1p and K2p are
set.
vgp vin

C1p Cgp
C2p Cgp =2
VDD
C1p C2p C3p Cgp
C1p C2p C3p Cgp
|{z}
|{z}
K1p

K2p

4
Notice that the bulk switching (BS) technique is also
applied to the main PMOS switch, M2, but no additional
switches are required since the SLCn circuit provides, in a
direct way, the required voltage to the bulk of M2.
Although this is a minor modification with insignificant
hardware costs, when applied to the original circuit
described in [10], linearity enhancements of the order of
four times are achieved.
3.2 Practical implementation
The complete SLC circuit was optimized based on the
previous analytical expressions (3 and 4), following the
five steps methodology (a simplified flow-chart of the
several steps is provided in Fig. 3) described next. All
auxiliary NMOS and PMOS devices were respectively
sized with aspect ratios of 1/0.13 and 4/0.13, and the main
switches (M1 and M2) as in Sect. 2.
STEP 1: Definition of the lowest practical capacitance
value to be used, which will be initially applied to C3n. It
was assumed 30 fF. Likewise, for the initial SLCp block

calculations (described later), a similar initial value is set

for capacitor C1p.
STEP 2: Definition of the maximum value allowed for
vin. It was defined as 90% of VDD. This value will
determine the maximum value of vgn, which should be
lower than the sum of the supply and junction voltages.
In order to reduce the leakage currents, avoid latch-up
and the need of adding any protection circuits, a
conservative value VDD ? VTN is used. Replacing these
values in (3), and using the computed gate capacitance
values, a first relation between C1n and C2n is obtained.
STEP 3: Taking into account the slope of vgn as a
function of vin, the K1n factor should cause an amplification for low vin values and an attenuation for high
values. If this factor is close to one, this circuit will be
similar to a conventional CBT switch; if it is zero in the
circuit will culminate in a conventional NMOS switch.
The targeted value for K1n term is 0.5. As a consequence,
a second relation between C1n and C2n is obtained.
Hence, C1n and C2n can be computed and sized to be 100
and 80 fF, respectively. The sum of these values should
be sized one order of magnitude higher than the gate
capacitance of the main device, Cgn, attenuating its
nonlinear influence and ensuring an effective control of
the gate voltage, vgn. Otherwise, the initial capacitance
value set for C3n must be higher.
STEP 4: The maximum conductance value of the NMOS
switch, is about 65 mS for vin & 0, as depicted in Fig. 1.
This conductance should be made equal to the maximum
conductance of the PMOS switch, for vin & 0.9VDD.
Being the CMOS switch sized asymmetrically, the
effective gate voltage absolute value of the NMOS and
PMOS switches should be the same in these two
conditions. Then (5) is obtained, which sets implicitly
a first relation between C2p and C3p.
0:9K1p K2p 0:9  K2n VTN0 =VDD  jVTP0 j=VDD

Def. min . used capa cita nce

C3n and C1p

C1n and C2n

STEP 5: The slopes of gnmos and gpmos, as a function of

vin, should be symmetrical as seen in Fig. 1. The gnmos
slope is affected by the body factor cn, surface potential
|UF| and input signal. Hence, the slope of vgp will have a
lower value than the slope of vgn (in absolute value). A
second implicitly relation between C2p and C3p can be
set by (6).
p
K1p K1n  cn =2 vin 2jUF j
6

D e f . ma x . a l l o w e d v o l t a g e
Def.
f slope of gnmos vs. vin
i
Max. gnmos
Slope of gpmos vs. vin

Max. gpmos

C2p and C3p

Fig. 3 Simplified flow-chart of the main steps to optimize the sizing
the auxiliary capacitors used in the SLCn and SLCp circuits

123

The value found for K1p is 0.24 for a vin DC level value
of VDD/2. The C2p and C3p capacitance values are then
computed to be 150 and 330 fF, respectively, and C1p is
sized to 30 fF, as previously stated. These values are higher
than the gate capacitance of the main device, Cgp, and,
therefore, are acceptable.

Analog Integr Circ Sig Process

4 Simulated results and reliability

4.1 Distortion
For comparison purposes, a complete 50 MS/s flippedaround and fully-differential sample-and-hold (S/H) circuit,
as shown in Fig. 4, was designed. The SLC switches and
circuits are sized as stated in the previous section. The VCMI
voltage is 0.8 V, switches S3p and S3n are implemented with
PMOS switches with an aspect ratio of 40/0.13.
Normalized sampling-capacitors, Csn and Csp, equal to
4 pF are used. The output common-mode is set to 0.55 V.
Figure 5 displays the simulated total harmonic distortion
(THD) for the output signal (voutp - voutn) of the S/H circuit
with a sampling frequency of Fs = 50 MS/s. Four different
linearization techniques are considered: (1) conventional
CMOS (conv. CMOS); (2) CBTn; (3) SLC-BS; (4) CBTp

4.2 Scalability and spread

2
S2p

VCMI
SLC

vinp

S3p

voutp

Csp
1

vinn

SLC

S1p
S1n

+
_

Csn

1 S3n

SLC

voutn

S2n

Figure 7 displays THD simulations of the S/H for sampling

capacitors (Csn and Csp) with different sizing, and for main
switches S1p and S1n with multiplying factors of 0.25, 0.5, 2
and 4. The set of capacitors used in the corresponding SLCBS circuits were calculated strictly following the design
methodology described in Sect. 3.2. The maximum spread
of the capacitance values was kept the same (around 11).
4.3 Corner analysis

SLC

VCMI

with bulk switching (CBTp-BS). A differential input signal

amplitude of 0.5Vpp, for six different frequencies (4.7,
7.7, 9.7, 11, 17 and 23 MHz), is used. For comparison
purposes, the sums of the auxiliary capacitors used in the
four techniques circuits, have been set to the same value.
As it can be observed, using the proposed SLC-BS circuits, there is a significant improvement in the THD, when
comparing with conventional CMOS switches. The THD
performance of the SLC-BS circuit is nearly constant
above Fs/4 (similar to the CBTp-BS), showing the influence of the applied bulk switching technique to the PMOS
element. Increasing the input signal amplitude to a real railto-rail swing, the SLC-BS circuit shows an improved THD
behavior over the CBT circuits, as presented in Fig. 6 for
an input signal with a frequency of 4.7 MHz. The reason is
due to the fact that a transmission-gate is being used rather
than a single NMOS or PMOS switch.

Fig. 4 Flipped-around S/H circuit. Four different SLC or CBT

circuits are needed to drive the four switches in the signal path

Table 1 shows the simulated THD for five different corners

(considered the most critical ones), using the typical (TT),
slow (SS) and fast (FF) models provided by the foundry.
Parameters VDD, temperature and capacitors tolerance
(xcap) were also considered. The circuit was simulated

60
65

65

conv CMOS
70

70

CBTpBS
75

75

80

SLC BS

85

CBTp BS

THD, dB

THD, dB

CBTn

SLCBS

80

CBTn
85

90

90

95
4.7

7.7

9.7 11

17

23

freq, MHz

Fig. 5 THD of a fully-differential flip-around S/H circuit for the four

different techniques versus input signal frequency

95
0.8

1.0

1.2

1.4

in

1.6

1.8

2.0

2.2

,V

pp diff.

Fig. 6 THD obtained for 4.7 MHz and large amplitude input signal

123

Analog Integr Circ Sig Process

70

vgn

1.4

THD, dB

x1
x2

80

x4
85

90

1.2

signal and gate voltages, V

x0.25
x0.5

75

vin

0.8
0.6
0.4
0.2
0

vgp

0.2
95
4.7

7.7

9.7 11

17

23

Table 1 Simulated THD for different process corners

TT, VDD = 1.2 V

-87 -83

7.7

9.7

11

17

23

-80.5 -78.5 -77.5 -77

xcap = 0, ?25C
SS, VDD = 1.08 V

-80 -77.5 -77

1.5

2
7

x 10

Fig. 8 Gate voltages applied to the main switches for a 0.5Vpp

input signal amplitude

Fig. 7 THD obtained for different main switches size

4.7

time, s

freq, MHz

fin (MHz)

0.5

-76.5 -75

-74

-87 -84

-82.5 -79.5 -77

-76

-92 -89

-87

When CBTn and CBTp-BS circuits are used these values

increase to about ?186 and -76% of VDD, respectively.
Hence, the reliability and lifetime projection are significantly
improved using the proposed SLC-BS circuit technique over
any CBT solution.

xcap = ?15%, ?85C

SS, VDD = 1.32 V
xcap = ?15%, ?85C
FF, VDD = 1.32 V

-85

-82.5 -81.5

xcap = -15%, -40C

with an input signal amplitude of 1 Vppdiff and the simulations were repeated for six different frequencies.
As expected, the worst-case THD is achieved at
Nyquist-rate and for a slow corner when VDD is reduced by
10% and capacitances values increased by 15%. However,
even for this worst-case, the THD is still compatible with
more than 12 bits of linearity.
4.4 Reliability issues
Considering reliability issues, we can claim that the
improved SLC-BS solution proposed in this paper is significantly better than the CBT ones. Figure 8 displays the gate
voltages delivered to main switches when a 4.7 MHz input
signal with 0.5Vpp amplitude is applied. The values are
inside the range allowed by the used technology. Over-stress
and leakage are not present in the main switches or in any
other switch of the SLC circuits, and complex circuits necessary to prevent them are not necessary. As shown, the
highest NMOS gate voltage, vgn, is smaller than 1.38 V
(corresponding to 115% of the nominal VDD voltage), and the
lowest PMOS gate voltage, vgp, is -0.15 V (-13% of VDD).

123

5 Integrated prototype and measured results

An integrated prototype of a 1.2 V, 10-bit, 32 MS/s pipelined ADC, using the proposed SLC circuit technique, was
fabricated in a 130 nm High-Speed CMOS process with
MiM capacitor option.
The system consists of an input front-end fully-differential S/H, followed by a cascade of eight stages, where
each stage comprises a 1.5-bit MDAC and a 1.5-bit flash
quantizer. At the end of the pipelined chain, there is a 2-bit
flash quantizer. The output bits of the different stages are
synchronized and, after digital correction, a net 10-bit
digital output is obtained. The circuit is controlled by two
non-overlapped control signals, /1 and /2, and their
complementary versions.
The design description presented here is mainly focused
on the front-end S/H circuit where the proposed new SLC
circuits are used. The implemented S/H block matches the
circuit shown in Fig. 4, only with a basic simplification in
the driving scheme of the feedback switches, S2p and S2n.
These feedback switches are simply made of asymmetric
transmission gates (ATG), with bulk-switching, being
directly controlled by holding phase, /2, and its complementary version (no additional SLC circuits were, therefore, found to be required for driving these two switches).
The NMOS and PMOS devices are then sized with
aspect ratios of 10/0.13 and 36.5/0.13, respectively. The

Analog Integr Circ Sig Process

sized with 1 pF (corresponding to a maximum equivalent

sampling capacitance of 4 pF). The sampling switches are
controlled, two by two, by one single SLC circuit, resulting
in a total of four SLC circuits implemented. The re-sizing
of the SLC circuits is done following the design procedure
described in Sect. 3.2. The capacitors C1n, C2n, C3n, C1p,
C2p and C3p are then sized, respectively with 420, 240, 200,
40, 190 and 1000 fF.
Figure 9 shows the die microphotograph (with overlaid
layout plot) of the integrated ADC prototype and S/H
block. The ADC (S/H included) occupies an area below
0.29 mm2, and the front-end S/H occupies less than
0.052 mm2. The area of each pair of SLC circuits is
approximately a square (for convenience of layout), and
occupies less than 0.005 mm2, i.e. 9% of the S/H area. For
shielding reasons (mainly related with possible substrate
noise), all transistors used in the two SLC circuits were
enclosed within a total of 12 capacitors employed.
Figure 10 shows the static DNL and INL measurements
of the 10-bit ADC, for the ADC input set to 1.1 Vppdiff

bulk-switching feature is ensured by two extra PMOS

switches per each ATG, both sized with aspect ratios of 4/
0.13. Sampling switches, S1p and S1n, are made of ATGs
controlled by a SLC circuit, with bulk switching control, as
described in Sect. 3.1. For sub-sampling operation and
programmable-gain flexibility purposes, each signal path of
the S/H circuit comprises four equally sized sampling and
feedback switches, and four sampling capacitors, each one

Fig. 9 Die microphotograph of the ADC, with front-end S/H block

Fig. 10 Measured DNL and

INL of the 10-bit ADC in
typical conditions and at
32 MS/s sampling rate

DNL - Sample=TT, Vdd=1.2V, PG=+6dB

1

LSB

0.5

-0.5

-1
0

200

400

600

800

1000

800

1000

DIGITAL OUTPUT CODE

INL - Sample=TT, Vdd=1.2V, PG=+6dB
2
1.5
1

LSB

0.5
0
-0.5
-1
-1.5
-2
0

200

400

600

DIGITAL OUTPUT CODE

123

Analog Integr Circ Sig Process

(saturating the ADC) and using a classical histogram testing method. Measured results demonstrate that the circuit
exhibits DNL (small signal behaviour) and INL (strong
signal behaviour) errors compatible with, 10 and 9 bits of
static accuracy, respectively.
The measured FFTs of the ADC for 4096 bins and 20
averages, clocked at 32 MS/s and when input signals with
31 and 63 MHz are applied, are shown in Figs. 11 and 12,
respectively.
The measured results of the ADC, for input frequencies,
fin, of 1, 31 and 63 MHz, are then summarized in Table 2.
The dynamic ADC performance achieves a peak SNR of
55.3 dB, a THD of -62.5 dB, a SFDR of 65 dB and an

amplitude, dB

20

40

60

80

100

120

1.9

3.9

5.9

7.9

9.9

11.9

13.9

15.9

freq, MHz

Fig. 11 Measured FFT spectrum of the output of the ADC in subsampling, for a 31 MHz input signal

Table 2 Measured results for different input frequencies

fin (MHz)
SFDR (dBc)

31 (sub-sampling)
65

63 (sub-sampling)

63.8

61.6

THD (dB)

-62.5

-61.4

-58.4

SNR (dB)

55.3

53.7

52.9

SINAD (dB)

54.5

53.1

51.8

ENOB (bit)

8.8

8.5

8.3

ENOB of 8.8 bits at Nyquist rate and for a 1 MHz input.

The SFDR measured results (with low frequencies input
signals) are fully compatible with the static DNL measurements (10-bit linearity). Likewise, the THD results are
also fully compatible with the INL results. Hence, as
expected, both, static and dynamic performance parameters
are limited by the maximum achievable matching accuracy
of this 130 nm CMOS process (accordingly with the
MiM capacitors matching parameters), which is bounded to
10-bits. As a consequence, it would be expected for this
ADC that the SFDR and THD will be limited to 65 to
68 dB and -60 to 65 dB, respectively. Hence, it can be
concluded that, the SLC circuits used in the front-end S/H
of the referred ADC do not add any significant dynamic
error, since both, the SFDR and the THD results exhibit a
reasonable flat behaviour over an entire bandwidth of
63 MHz.
The SFDR and the THD (module) results for different
input frequencies, of the simulated S/H and of the overall
implemented circuit, are shown in Fig. 13. As previously
referred and expected, only at very high input signal
frequencies (in sub-sampling mode) the SLC circuits start
degrading the SFDR and the THD performance of the
ADC.

100

95
20

SFDR
simulated (S/H)

SFDR & |THD|, dB

90

40

amplitude, dB

60

80

85
80
75
70
65
60

100

|THD|
simulated (S/H)
SFDR
measured (S/H + ADC)
|THD|
measured (S/H + ADC)

55
120

50
1.9

3.9

5.9

7.9

9.9

11.9

13.9

15.9

freq, MHz

Fig. 12 Measured FFT spectrum of the output of the ADC in subsampling, for a 63 MHz input signal

123

31

63

freq, MHz

Fig. 13 SFDR and |THD| of output of the complete ADC (measured)

and of the S/H (simulated), for different input signal frequency

Analog Integr Circ Sig Process

6 Conclusions
This paper described a design methodology for designing
dedicated switch-linearization control circuits to properly
drive CMOS switches when very low distortions levels are
targeted. The described circuit has the advantage over
conventional clock-bootstrapping circuits of being more
reliable due to the low-stress over the gate capacitances.
The design and the experimental evaluation of a 10-bit
pipelined ADC, with the sampling switches of the differential S/H employing the proposed SLC linearization circuits to guarantee linearity without over-stress, is also
presented. The measured results prove the functionality and
the efficiency of the proposed technique. These experimental results show that the adopted SLC technique is
capable to overcome the challenges existing in the design
of the S/H of a medium/high resolution ADC, allowing
high input signal bandwidths. Furthermore, the life span of
the circuit will be certainly improved, as reduced gate
voltages are applied, smaller than ?112 and -6% of the
nominal VDD, over the rail-to-rail input voltage swings.
Acknowledgment The research work that led to this implementation was supported by the Portuguese Foundation for Science and
Technology under LEADER and SPEED Projects.

References
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3. Abo, A. (1999). Design for reliability of low-voltage, switchedcapacitor circuits. PhD Thesis, Berkeley.
4. Steensgaard, J. (1999). Bootstrapped low-voltage, analog switches.
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8. Aksin, D., Al-Shyoukh, M., & Maloberti, F. (2006). Switch bootstrapping for precise sampling beyond supply voltage. IEEE Journal
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10. Galhardo, A., et al. (2006). Novel linearization technique for lowdistortion high-swing CMOS switches with improved reliability.
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Editions.
A. Galhardo was born in Castelo Branco, Portugal, in 1953.
He graduated from Instituto
Superior Tecnico (IST), Lisbon,
in 1976. He obtained the M.Sc.
degree in 2000, from the Technical University of Lisbon. He
has been with the Department of
Electrical Engineering and
Automation (DEEA) of the Instituto Superior Engenharia de
Lisboa (ISEL) of the Instituto
Politecnico de Lisboa (IPL),
since 1977, where he is currently an Assistant Professor. He has actively participated and led
several projects, at request and together with private institutions, in
science and technology. His current research interests are in lowvoltage, high-performance and high-frequency data-converters. He is
currently pursuing the Ph.D. degree in Faculdade de Ciencias e
Tecnologia (FCT) of Universidade Nova de Lisboa (UNL). He is also
a Member of the Portuguese Professional Association of Engineers
since 1978.
J. Goes (S95M00) was born
in Vidigueira, Portugal, in 1969.
He graduated from Instituto
Superior Tecnico (IST), Lisbon,
in 1992. He obtained the M.Sc.
and the Ph.D. degrees, respectively, in 1996 and 2000, from
the Technical University of
Lisbon. He has been with the
Department of Electrical Engineering (DEE) of the Faculdade
de Ciencias e Tecnologia (FCT)
of Universidade Nova de Lisboa, since 1998 where he is
currently an Assistant Professor.
Since 1998 he has been also working as a Senior Researcher of the
Centre for Technology and Systems (CTS) at UNINOVA. In 2003 he
co-founded ACACIA Semiconductor, a Portuguese engineering
company specialized in high-performance data converter and analog
front-end products (acquired by Silicon and Software Systems, S3, in
Oct. 2007). Since 1992 he has actively participated and led several
National and joint European cooperative projects in science, technology and training. His scientific interests are in the areas of the
design of low-power and low-voltage analog integrated circuits, dataconverters, built-in self-testing and self-calibrating techniques and
design methodologies for optimization and automatic sizing of analog
circuits. Dr. Goes has published over 60 papers in international
journals and leading conferences and he is co-author of Systematic
Design for Optimization of Pipelined ADCs (Springer, 2001), Low
Power UWB CMOS Radar Sensors (Springer, 2008) and VLSI
Circuits for Biomedical Applications (Springer, 2008). He is also a
Member of the Portuguese Professional Association of Engineers
since 1992.

123

Analog Integr Circ Sig Process

N. Paulino was born in Beja,
Portugal, in 1969. He graduated
from Instituto Superior Tecnico
(IST), Lisbon, in 1992. He
obtained a M.Sc. degree, in
1996 from the Technical University of Lisbon and a PhD in
electrical engineering in 2008
from the Universidade Nova de
Lisboa. He has been with the
Department of Electrical Engineering (DEE) of the Faculdade
de Ciencias e Tecnologia
(FCT), New University of Lisbon (UNL), since 1999. Since
1999 he has been also working as a Senior Researcher of the Micro-

123

Electronics and Signal-Processing group (MESP) at UNINOVA. In

2003 he co-founded ACACIA Semiconductor, a Portuguese engineering company specialized in high-performance data converter and
analog front-end products, this company was acquired by S3 Ltd. in
2007. From 1996 to 1999 he worked as Analog Design Engineer at
Rockwell Semiconductor, USA. His scientific interests are in the
areas of the design of CMOS circuits for UWB imaging systems,
signal-processing, data-converters, self-testing and self-calibrating
techniques and optimization tools for assisting the design of analog
circuits. Mr. Paulino is a Member of the Portuguese Professional
Association of Engineers since 1992.