Sect 8

Section 8: 1+1 UPS System Control
Chapter 1 - "1+1" Configured Systems

1.1 Introduction .............................................................................................. 8-1
1.1.1 1+1 Power circuit considerations ............................................. 8-1
1.1.2 1+1 Control circuit considerations ........................................... 8-1
Chapter 2 - Parallel Logic Board 4520075B
2.1 Chapter Overview. .................................................................................... 8-5
2.2 General Description .................................................................................. 8-5
2.2.1 Input/Output connections ............................................................. 8-5
2.2.2 Circuit board functions .............................................................. 8-10
2.3 General module output control ............................................................... 8-12
2.3.1 Inverter ON/OFF request [OFF_INV> ........................................ 8-12
Selective shutdown .......................................................... 8-13
2.3.2 Load transfer control .................................................................. 8-15
Load-on-inverter request [C_L_INV> .......................... 8-16
Load-on-bypass request [O_BUS_INV_L> ................. 8-17
2.4 Frequency synchronisation principles .................................................... 8-19
2.4.1 Introduction ................................................................................ 8-19
Inverter frequency control overview ............................. 8-19
Basic GVCO sync principles on module start-up ............ 8-20
2.4.2 GVCO Detailed description of operation .................................. 8-23
2.4.3 PLL Phase Comparator (D29) ................................................... 8-26
2.4.4 D30 Parallel Control Functions ................................................. 8-26
Bypass validation ............................................................. 8-27
Sync source selector ......................................................... 8-27
Sync bus comparator ........................................................ 8-28
VCO-in-loop relay control ............................................... 8-28
Internal Sync Logic .......................................................... 8-29
2.5 Output current sharing ............................................................................ 8-31
2.5.1 Introduction ................................................................................ 8-31
2.5.2 Current sharing error detection principles ................................. 8-31
2.5.3 Current-sharing relay control (K3/K4) ...................................... 8-33
2.5.4 Selective shutdown .................................................................... 8-34
Current-sharing error ....................................................... 8-34
Reverse Power detector .................................................... 8-35
Forward Power detector ................................................... 8-35
2.5.5 On-line module counter ............................................................. 8-35
2.6 Parallel rectifier operation ...................................................................... 8-36
2.6.1 Rectifier current-sharing control ................................................ 8-36
2.6.2 Boost charge control .................................................................. 8-37
2.6.3 Battery test control ..................................................................... 8-37
11pm.fm5 - Issue 2 Dated 21/08/97
SECTION 8 - 1+1 UPS System Control
7200 Series UPS Service Manual
2.7 Other Features and functions .................................................................. 8-38

2.7.1 Ribbon cable connection monitor .............................................. 8-38
2.8 Parallel Logic Board circuit operation during start-up ........................... 8-39
2.8.1 Initialisation/reset ....................................................................... 8-39
2.8.2 Inverter run-up and synchronisation .......................................... 8-39
2.8.3 Connecting to the parallel control bus ....................................... 8-40
2.8.4 Load transfer to inverter ............................................................. 8-40
2.8.5 Load retransfer back to bypass .................................................. 8-42
2.9 Test mode of operation: .......................................................................... 8-42
ii
11pm.fm5 - Issue 2 Dated 21/08/97
Section 8: "1+1" Configured Systems
Chapter 1 - "1+1" Configured Systems
1.1
Introduction
A basic description of the principles of a 1+1 configured system is provided in
section 1 (see paragraph 1.4 on page 1-7) the basic block diagram is repeated
in Figure 8-1, below.
Figure 8-1: 1+1 System configuration block diagram
RECTIFIER
INVERTER
Rectifier
Control Logic
Inverter
Control Logic
INV (SS)
Static
Bypass
BYP (SS)
Static Switch
Control Logic
Inter-Module Parallel Control Logic
Maint. Bypass
Output
(LOAD)
PowerSupply
Maint. Bypass
Static Switch
Control Logic
Inter-Module Parallel Control Logic
Rectifier
Control Logic
Inverter
Control Logic
RECTIFIER
INVERTER
Static
Bypass
BYP (SS)
INV (SS)
1.1.1
1+1 Power circuit considerations

As the above diagram shows, in a 1+1 system the power outputs from the two
modules are connected to an external common output busbar from where it is
routed to the critical load equipment using normal distribution methods. Therefore, from a power point of view there are no modifications required to the
standard single-module UPS.
1.1.2
1+1 Control circuit considerations

The extra control requirements of a 1+1 system over that of a single-module
are quite extensive due to the fact that the UPS output power terminals are connected to a common bus. The additional features require an exchange of various
control and status signals, both analogue and digital, to pass between the two
modules. Such signals are connected via the Parallel Logic Boards which are connected together by cross-connected ribbon cables which form a Parallel Control
Bus (See Figure 8-2).
11pm-c1.fm5 - Issue 2 Dated 21/08/97
8-1
SECTION 8 - "1+1" Configured Systems

CHAPTER 1 - "1+1" Configured Systems
Figure 8-2: 1+1 Control Logic
MODULE 1
X3
Parallel
Bus
Parallel
Logic
Board
X1 X2
Rect. Logic Bd
X1
MODULE 2
X3
Parallel
Logic
Board
X2 X1
X7
X7
UPS
Logic
Board
UPS
Logic
Board
X3
Inv. Logic Bd
Static Sw. Drv. Bd
X1
Rect. Logic Bd
X3
Inv. Logic Bd
Static Sw. Drv. Bd
X5
X5
X2
X2
High Voltage I/F Bd
High Voltage I/F Bd
These inter-module control functions fall into the following broad categories:
Balanced output requirements
It is crucial that the modules outputs are balanced in order to prevent a circulating
current flowing from one module to the other, as such an event could cause significant module damage and invalidate the critical load supply. Balanced conditions are achieved by ensuring that the inverters are always fully synchronised to
each other and their output voltages are equal. As with the case of the singlemodule it is also necessary to synchronise the inverters to the bypass supply in
order facilitate a no-break load transfer when required.
Transfer control requirements
Once again due to the paralleled nature of the modules outputs, it is crucial that
the load transfer control mechanisms in each module are controlled from a
common point. That is, to prevent equipment damage due to one module transferring its output to bypass whilst the other is on inverter. A common control
system is therefore used which manages the load transfer according whether the
system is configured as redundant or non-redundant.
Redundant vs Non-Redundant configuration
Redundant system. In a redundant system, if one module fails the remaining

module will remain on-line to maintain the critical load; therefore if a module
goes faulty its output contactor is tripped to take it off-line but its static bypass is
not activated. The static bypass circuit is only triggered if a fault develops in the
second module which requires it also to be taken off-line.
In a redundant system the modules are thus sized such that the potential maximum load can be powered by just one of the two modules. Under normal circumstances both modules are operational and share the load current equally i.e.
under full load conditions both modules operate at 50% of their nominal rating.
8-2

Non-redundant system. In a non-redundant configuration, if one module

fails then both modules are taken off-line (by opening their output contactors) and
the load transferred to the static bypass. The load will not re-transfer to the inverters until both inverters are fully operational and fully synchronised etc.
In a non-redundant system each modules nominal rating must be at least 50% of
the potential maximum load.
Inter-module power rectifier control
The power rectifier is only affected by the parallel control bus in a 1+1 system
if a common battery is used i.e. if both UPS modules are connected to a single
battery bank (via separate battery isolators of course). In this type of installation
the power rectifiers in each module are effectively connected in parallel and must
be controlled such that the battery charge current is shared equally between them.
A common battery option kit is available. This contains DCCTs (DC Current
Transformers) which are fitted to the battery power lines and connected via the
parallel control bus to a sharing circuit in the rectifier control block.
See the Options section in the relevant system IOM user manual for full details.
8-3

8-4
Section 8:
Chapter 2 - Parallel Logic Board 4520075B
2.1
Chapter Overview.
This chapter contains a circuit description of the Parallel Logic Board used across
the whole 7200 Series UPS model range when configured to operate as a 1+1
system, and should be read in conjunction with circuit diagram SE-4520075-B (4
pages). Signal annotations shown on the circuit diagrams are shown in italics in
the following text e.g. [SYN_INT>.
2.2
2.2.1
General Description
Input/Output connections
Connectors X2 & X3
As mentioned above, connectors X2 & X3 are cross-connected from one module

to the other i.e. X2 on one module is connected to X3 on the other, and viceversa. The signals passing between these connectors are therefore bi-directional.
Table 8-1:
Pin
Signal
1
2
A_CON / 0V
B_CON / 0V
Used to detect that the ribbon cable is connected

(See paragraph 2.7.1)
B_BLK_SW
If a module applies an [O_BLK_SW> signal to X1-43 it

is passed to both modules via this line, and thereby
turns off the inverters in both modules by driving the
[OFF_INV> output at D31-19 high. (see page 8-12)
B_MNS_L_SS
If a module applies an [O_MNS_L_SS> signal to X144 it is passed to both modules via this line. This is
used by the load transfer control logic when the board
is fitted in a multi-module MSS cabinet only, and is
overridden in a 1+1 system by jumper X6-4(see page
8-16).
B_MNS_D_SS
If a module applies an [O_MNS_D_SS> signal to X1

pin 45 it inhibits the passage of the mains frequency
signal [F-IN> through D31 (See paragraph 2.4.4.1).
This signal is coupled to the second module via the
parallel bus X2/X3 pin 5 (inhibit = low).
Signal Function
B_PAR_SYN
This is taken high when the VCO-in-loop relay (K1) is

closed in either module, and is used to inform the
GVCO whether to start in the master or slave mode
during turn-on (See paragraph 2.4.4.4).
B_MNS_SYN_OK
The [O_MNS_SYN_OK> signal to X1-48 informs the

Parallel Logic Board when the Inverter Logic Boards
master oscillator is internally synchronised. This is
applied to the bypass validation circuit in both modules (See paragraph 2.4.4.1)
8-5
SECTION 8 - "1+1" Configured UPS System Control

CHAPTER 2 - Parallel Logic Board
Pin
Signal
B_BST_BAT
Used when common battery system is used to force

both modules into boost mode if selected in either
module (See paragraph 2.6.2).
B_MNS_DIS
This line couples together the [O_MNS_DIS> input to

X1-49. When [O_MNS_DIS> is low in both modules
the bus line goes high and feeds back a logic high to
the UPSLB via X1-37 [MNS_DIS>
B_INV_LOD
This line couples the load-on-bypass request and is

logic high (requesting load on inverter) only when neither module is calling for load on inverter. This line
affects the output on X1-32 (See paragraph 2.3.2.2)
B_FREQ_PAR
This line is connected to the GVCO [FRQ_OSC> output if relay K1 is closed (in either module,) and thereby
forms the parallel GVCO sync bus (See paragraph
2.4.1.1).
10
11
Signal Function
12
B_INV_IND
This line, goes low only when the VCO in loop relay
(K1) is closed in both modules, and is used to signal
the availability of both modules in a non-redundant
system.
13
B_TST_BAT
Used when common battery system is used to force

both modules into TEST mode if selected in either
module (See paragraph 2.6.3).
14
B_SW_BYP
High when Maintenance Bypass Switch is closed in

either module (see X1 - 34).
15
B_FREQ_MNS
1618
NIU
19
20
0V
21
COMM_P
22
I_B_P
24
O_N_INV
23
25
26
27
28
29
30
B_IM_0
B_IM_C
B_IM_R
B_IM_A
B_IM_B
B_C_0
B_C_P
31
32
8-6
This line carries the bypass (mains) frequency signal

between the modules when it has been accepted by
the bypass validation circuit (See paragraph 2.4.4.1).
These two lines are used to parallel the battery current

sense signals when required. Not used for a particular
purpose on this board. input via X1 18/19.
This line connects the available module counter circuits together to allow the number of available modules to be detected (See paragraph 2.5.5).
These lines carry the current sharing sense signals

(See paragraph 2.5)
0V
33
34
B_GND
NIU
Parallel bus ground connection

Connector X1
Table 8-2:
Pin
Signal
Signal Function
1-4
0V
5-8
+12V
9 - 10
-12V
11
VO_A
12
VO_B
13
VO_C
14
COM
15
IO_A
16
IO_B
17
IO_C
18
I_B_P
19
COMM_P
20
DV_A
21
DV_B
22
DV_C
23
DV_0
Output voltage sense signals derived on the High

Voltage Interface Board. Used by the selective shutdown circuit (See paragraph 2.5.4).
Analogue sense signal common
Output current sense signals derived on the High
Voltage Interface Board. Used by the current sharing
and selective shutdown circuits (See paragraph 2.5).
These two inputs are used to parallel the battery current sense signals when required. Not used for a particular purpose on this board but connected directly to
second module via parallel bus X2/X3 pins 21/22.
These outputs are generated by the current sharing
circuit and go to the Inverter Logic Board (via UPSLB)
where they perform individual fine adjustment of each
output line voltage to balance the line currents
between the two paralleled machines. DV-0 is a neutral point for these signals (See paragraph 2.5.2).
IREC_T
Input from rectifier current sense amp on Rectifier

Logic Board. This represents the rectifier current
taken by this module and is used by the current sharing circuit if a common battery system is used (See
paragraph 2.6.1).
25
DB
This output is the result of the rectifier current sharing

circuit and passes to the Rectifier Logic Board in the
form of a correction signal to ensure balanced input
currents to both modules when a common battery
system is used (See paragraph 2.6.1).
26
24
27-28
NIU
0V
29-30
+5V
31
NIU
32
I_BUS_INV_L
This is a logic low load-on-bypass request to the control logic on UPSLB. Due to the parallel bus connection (X2/3 - 10) the output is low only when load-onbypass is requested by both modules (See paragraph
2.3.2.2).
33
SW_OUT
This is an input via HVIB which is low when the Output Switch is closed (see page 8-13).
8-7

Pin
Signal
Signal Function
34
SW_BYP
This is an input via HVIB which is low when the Maintenance Bypass Switch is closed in either module
(see page 8-13).
35
I_BST_BAT
Output to UPSLB which, when high, initiates Battery

Boost. Used in common battery system only and is
enabled by jumper X6-2.(See paragraph 2.6.2)
36
I_TST_BAT
Output to UPSLB which, when high, initiates Battery

Test. Used in common battery system only and is
enabled by jumper X6-2. (See paragraph 2.6.3)
37
MNS_DIS
The input to X1-49 from the UPSLB goes high.

This input is coupled together via the parallel control
bus (X2/3 - 9), and when [O_MNS_DIS> is low in
both modules a logic high is fed back to the UPSLB
via X1-37 [MNS_DIS>
38
BLK_SEL
Output to the UPSLB which is high when the selective shutdown circuit is active (led H1 illuminated)
(See paragraph 2.3.1.1).
39
OFF_INV
Output to inverter ON/OFF control logic on UPSLB.

Turns OFF inverter if high. (See paragraph 2.3.1)
40
C_L_INV
Output to load-on-inverter control logic on UPSLB.

Requests load on inverter selection if high (See paragraph 2.3.2.1).
41
RES_EXT
Input from the reset circuit on the UPSLB which,

when high, resets several functions within the Parallel
Logic Board ASIC devices.
42
V_AUX
Input from the UPSLB reset generator chip which

resets various latches within D39 and D31on powerup. The signal is a 1 second logic high pulse.
O_BLK_SW
Input from the UPSLB software-controlled inverter off

signal [O_BLK_SW>. The signal is also coupled to
the second module via X2/X3 pin 3 which enables the
inverters in both modules to be turned off if a
[O_BLK_SW> signal is generated in either module
(See paragraph 2.3.1)
O_MNS_L_SS
This input is used by the load transfer control logic

when the board is fitted in a multi-module MSS cabinet, it is not functional in a 1+1 system due to configuration jumper X6-4. (see page 8-16).
45
O_MNS_D_SS
Input from the UPSLB processor system. When high,

it inhibits the passage of the mains frequency signal
[F-IN> through the bypass validation circuit. This signal is coupled to the second module via the parallel
bus X2/X3 pin 5 (See paragraph 2.4.4.1).
46
O_TST_BAT
Input from the UPSLB processor system which goes

high when it calls for a battery test sequence (See
paragraph 2.6.3).
47
O_BST_BAT
Input from UPSLB which, when high, requests Battery Boost (See paragraph 2.6.2).
43
44
8-8

Pin
Signal
Signal Function
48
O_MNS_SYN_OK
Input from UPSLB which is low when the Inverter

Logic Boards master oscillator has achieved internal
synchronisation (See paragraph 2.4.4.1).
49
O_MNS_DIS
The input to X1-49 from the UPSLB goes high.

This input is coupled together via the parallel control
bus (X2/3 - 9), and when [O_MNS_DIS> is low in
both modules a logic high is fed back to the UPSLB
via X1-37 [MNS_DIS>.
50
BLK_INV
This input is driven by the fault output on the Inverter

Logic Board and provides an input to the sync source
selector circuit (See paragraph 2.4.4.2)
51
PAR_REC
Input from the UPS Logic Board Processor system

which is high when it is programmed with parallel rectifier operation (See paragraph 2.6).
52
INV_L
This input from the UPS Logic Board goes high when
the load is on-inverter and is used to validate the
selective shutdown circuit (See paragraph 2.3.1.1).
53
FRQ_SYN
This is connected to the GVCO output [FRQ_OSC>

and thereby represents the reference frequency to
which the UPS inverter synchronises (See Figure 85).
54
FRQ_PAR
This output passes the parallel sync bus frequency to

the UPS Logic Board (See Figure 8-5).
55
F_IN
This input is a squarewave at the incoming mains Rphase frequency, used as the bypass reference frequency is accepted by the bypass validation circuit
(See paragraph 2.4.4.1).
56
57
58
59
60
NIU
INV_OK
This input is high when the UPS Logic Board determines that the inverter is operating normally and is
used by the synchronisation control logic within D30
during start-up (See paragraph 2.4.4).
CON_SEL
This input is generated on the UPS Logic Board and

is logic high when the battery is low or the bus voltage is 150% of nominal charge voltage. This is used
by the selective shutdown circuit (See paragraph
2.3.1.1)
I_SW_BYP
This output goes low when the [SWBYP> input to X134 is low in either module (i.e. when Maintenance
Bypass Switch is closed in either module) (see page
8-13).
N_AUX_CONT
This input is generated by the UPS Logic Board and

is low, to disable the load on bypass request, if the
inverter output contactor is closed (See paragraph
2.3.2.2).
8-9

2.2.2
Circuit board functions

Figure 8-2 illustrates the position of the Parallel Logic Board in a 1+1 configured module. The inter-module control signals pass from one module to the other
by means of the ribbon-cables fitted to the boards X2 and X3 connectors, which
are cross-coupled i.e. X2 on one Parallel Logic Board is connected to X3 on the
other. Due to their function, the ribbon cables connecting the two boards together
are referred to in this manual as the parallel control bus. The parallel control
functions will be maintained if one of the two cables is disconnected but for safety
reasons both cables should normally be connected led H2 illuminates if one
cable becomes disconnected, but the system is not otherwise affected.
The third connector (X1) on the Parallel Logic Board is connected to the UPS
Logic Board from where it has access to the remaining module control boards.
This topology allows any control board in one module to communicate with any
control board in the second module, as required by the control regime.
In addition to its role in providing a parallel control bus, the Parallel Logic Board
contains a number of active circuits whose functions are summarised below.
Note: each of the following categories are assigned major section headings in the
remainder of this chapter:
General module output control
The Parallel Logic Board generates control logic signals which:

provides an Inverter Start/Stop command signal which is connected as an
input to the Inverter Start/Stop control logic on the UPS Logic Board.
provides the static switch control section of the UPS Logic Board with
load transfer control signals which determine whether the load is connected to the inverter (output contactor closed) or static bypass supply.
monitors the number of available modules and shuts-down the inverter
(via the UPS Logic Board) if the system redundancy is exceeded.
Module frequency control and synchronisation control
Although each UPS module ultimately operates at a frequency determined by its

Inverter Logic Boards master oscillator, in a 1+1 system the Parallel Logic Board
provides a complex synchronisation function which operates between the two
modules and also between the modules and the bypass supply. This ensures that
the two modules are frequency-locked together at all times when the inverters are
operating in parallel, and also locked to the bypass supply provided it remains
healthy.
Output current control
When both modules are on-line and feeding a common load, their power inverter
sections are effectively operating in parallel and should share the load current
equally. It is especially important that circulating currents are not allowed to
appear in the UPS output stages, whereby one module attempts to reverse-feed the
other.
The Parallel Logic Board contains analogue circuits which:
provide an output current-sharing function by using fine control of the
Inverter Logic Board voltage regulation circuit in such a manner as to
ensure that both UPS modules produce an equal output current.
provide protection against current sharing failure and trip the module off-
8-10

line if it detects that one module is feeding reverse current into the other.
This function is called Selective Shutdown in this manual.
Common battery control
In installations where a common battery is used by both modules, the Parallel

Logic Board provides a rectifier current-sharing function whereby is finely adjusts the rectifier voltage to obtain balanced rectifier input currents. If both modules produce the same output current and take the same input current this implies
that they are also (within limits) providing the same amount of battery charge current.
When a common battery is used, the Parallel Logic Board also controls the rectifier float/boost charge mode selection in both modules to ensure they operate in
the same mode at all times.
Miscellaneous functions
In addition to the easily categorised functions mentioned above, the Parallel

Logic Board also provides other minor functions which are mainly associated
with its role of providing the parallel control bus.
The digital control element of the above functions are carried out by two ASIC
circuits shown on page 1 of the circuit diagram D30 and D31. The internal logic
of these devices is not described in detail in this chapter; however an appreciation
of their input/output conditional relationships is essential to understand the wider
functionality of the circuits which they control, therefore internal block diagrams
of these devices are used to aid explanation where necessary.
8-11

Section 8:
2.3
General module output control

The signals described in this sub-section are concerned with turning ON/OFF the
inverter in the local module and controlling the load transfer between the inverter
and bypass supplies these signals are developed by D31, as described below.
2.3.1
Inverter ON/OFF request [OFF_INV>

Figure 8-3: Inverter ON/OFF & Selective Shutdown
X1
D31
19
[OFF_INV>
X7
39
39
X3
D88
33
1=OFF
[ON_INV>
X4
36
39
13
D11
1=ON
Parallel Logic Board
[BLK>
1=OFF
UPS Logic Board
Inverter Logic Board
D31 Internal Block Diagram
[RIT_INV_L>
[C_N_INV>
[CON_SEL>
31
27
11
Selective
Shutdoown
Logic
37
[BLK_SEL>
43
[TEST>
[BLK_SW> (mm only)
[I_SW_BYP>
[SW_OUT>
[CONN_A>
[CONN_B>
26
6
14
17
Inverter
ON/OFF
Logic
19
[OFF_INV>
18
An inverter ON/OFF control signal [OFF_INV> is produced by D31 pin 19 and

applied to the inverter inhibit logic on the Inverter Logic Board (D11) via the
path shown above in Figure 8-3. The [OFF_INV> signal at D31-19 goes high to inhibit the inverter and low to enable it. Note that the signal does not pass straight
through D88 on the UPS Logic Board, but is combined with several other inverter
inhibit logic signals at that point. It is therefore quite possible for the signal at
D31-19 to call for the inverter to be enabled ([OFF_INV> = low) but for some other
input to D88 to override this request on the UPS Logic Board ([ON_INV> = stays
low). Similarly, there are other inputs to D11 on the Inverter Logic Board which
can override an [ON_INV> request.
The [OFF_INV> signal logic state at D31-19 depends upon a complex combination
of the inputs to D31, as described below, and it is driven high (turning off the inverter) if any of the following conditions are true:
Selective shutdown. (D31 pin 37 high)
The selective shutdown function is concerned with a current sharing problem. The error detection circuit, which is explained in paragraph 2.5.4, is part
of the current sharing control description; however the effects of the selective shutdown error signal within D31 is described below in paragraph
2.3.1.1. In summary, if the selective shutdown logic within D31 becomes
active D31-37 ([BLK_SEL>) will switch high (illuminating H1) in addition to
driving D31-19 ([OFF_INV>) high.
8-12

Software block. (D31 pin 26 high)
Note: in a 1+1 configured system this input is overridden internally due to

jumper X6-4 being made (pulling D31-1 permanently low). Therefore, the
described affects of this signal on the Inverter ON/OFF control signal apply
only when the board is fitted in a multi-module inverter system.
A logic high signal applied to X1-43 from the UPS Logic Board
([O_BLK_SW>) is inverted by a section of D23 from where it is connected to
the parallel control bus (X2/3 pin 3). The signal at this point ([B_BLK_SW>) is
also reinverted at D26 pin 6 to provide the high [BLK_SW> signal to D31-26
which turns off the inverter. This means that in a multi-module system all the
modules are affected by the software block signal if it is generated in any
module.
Maintenance bypass interlock. (D31 pin 6 high and pin 14 low)
If the Maintenance Bypass Switch is closed (D31-6 is high) at the same time
as the modules Output Switch (D31-14 is low) it will drive D31-19 high,
turning off the inverter to prevent damage occurring due to reverse power
flow from the mains into the inverter.
Note: the Maintenance Bypass switch contacts are sensed by both modules
via the parallel control bus X2/3 pin 14. Thus, the inverter is shut down in
both modules if the maintenance bypass switch is closed in either module.
Output switch interlock. (D31 pin 43 high)
When operating in a 1+1 configuration, it is required that the inverter is

allowed to operate only if the UPS output switch is closed. This ensures that
the parallel current-sharing and frequency control systems are enabled. There
is however a TEST facility which is invoked by jumper X6-8 on the Parallel
Logic Board which, when closed, overrides this interlock to allow the
inverter to be run-up for test purposes with the output switch open.
When the module is not operating in the TEST mode i.e jumper X6-8 is
open (D31-43 high) the inverter will be turned off by the input to D31 pin
14 which is driven high when the output switch is open.
Test mode interlock. (D31 pin 43 low)
When the UPS is running in the TEST mode, jumper X6-8 is fitted (D31-43 is
low), the inverter will be turned OFF if the modules Output Switch is closed
(D31-14 is low).
Open circuit parallel control bus. (D31 pins 17 and 18 high)
If both ribbon cables that form the parallel control bus (to connectors X2 and
X3) are improperly connected (D31-17 & D31-18 both high) the inverter will
be shut down for safety reasons due to the loss of the parallel control bus.
Note: led H2 will illuminate when either one of these cables are disconnected,
driven by a logic high output on D31-32.
2.3.1.1
Selective shutdown
This paragraph considers the actions of the selective shutdown circuit within
D31 (See Figure 8-3), and its effects on the [OFF_INV> inverter ON/OFF command at D31-19.
8-13

The Selective Shutdown circuit detects various forms of current sharing faults
and is shown on page 3 of the circuit diagram (see paragraph 2.5.4 on page 8-34).
The detectors output signal [IN_SEL> goes high in a current-related fault event
and is inverted to a low at D31 pin 4 which:
Turns off the inverter (drives D31-19 [OFF_INV> high).
Sends a [BLK_SEL> status signal to the UPS Logic Board (from D31-37
and X1-38) to inform that board of the current conditions.
Illuminates H1.
Drives the output on D31-13 high.
This output is debounced and inverted, and fed back to D31-9 as a logic
low signal which latches the above signals in their fault state. Once activated, the latch must be reset by pressing the RESET push-button on the
UPS Logic Board, which applies a logic high [RES_EXT> input to D31-8
via X1-41. Note that when the module is first started the power-supply
monitor on the UPS Logic Board applies a 1 second logic high [V_AUX>
reset pulse to D31-5 which initially holds off the selective shutdown
latch (connected via X1-42).
In order for the [IN_SEL> selective shutdown signal to produce the above outputs
from D31, the following conditions have to be satisfied on other D31 inputs.
If any of these conditions are not satisfied the selective shutdown signal
[IN_SEL> is ignored by D31 internally.
Load on inverter (D31 pin 31 low).
The UPS Logic Board must be commanding load on-inverter. This is validated as a logic low on D31 pin 31.
UPS Not in Test mode (D31 in 43 high).
The UPS must not be operating in the Test mode. Jumper X6-8 must therefore be open, providing a logic high at D31 pin 43.
Two modules on line (D31 in 27 high).
In a non-redundant system the [C_N_INV> input to D31 pin 27, generated by

the module counter circuit (see paragraph 2.5.5 on page 8-35), is logic high
when both modules are on line, which is a requirement for the selective shutdown circuit output to be valid.
In a redundant module system it is permissible for one module to operate
alone, and where this is the case the selective shutdown circuit is irrelevant.
The [C_N_INV> input to D31 pin 27 is overridden in this case by making
jumper X6-3.
DC Bus above Vmin & Load below 150% nominal (D31 pin 11 high).
These two conditions are detected by the UPS Logic Board and a single signal ([CON_SEL>) is connected to D31 pin 11 which is high when both conditions are satisfactory.
8-14
2.3.2

Load transfer control

Figure 8-4: Load Transfer control logic
X1
18 [O_BUS_INV_L>
[I_BUS_INV_L>
32
X7
X5
[INV_DIS>
32
38
[MNS_L>
X3
17
[MNS_L>
17
1=turn on
static bypass
1=load on bypass
0=enable load on byp

D31
D88
12
40
[C_L_INV>
40
[C_L_INV>
36
1=turn close inv

output contactor
[INV_L>
15
15
[INV_L>
1=load on inv
0=enable load on inv
Static Switch
Driver Board
UPS Logic Board
[O_PAR_SYN>
[TEST>
[PAR_INV>
[MNS_L_SS> (mm only)
[C_N_INV>
[N_AUX_CON>
[INV_L>
Jumper X6-4 (made)
Jumper X6-1
(made = non-redundant)
[INV_IND>
24
VCO-in-loop
Control
21
[RIP>
To Relay
K1/K2
43
18
28
[O_BUS_INV_L>
27
34
25
1
Load
Transfer
logic
12
[C_L_INV>
44
44
20
[O_INV_IND>
Load transfer control is based on several complex circuits which are interlocked
in such a way as to avoid the bypass static switch being activated while the inverter output contactor is closed, and vice versa, to prevent back-feeding the UPS inverter from the mains supply.
In a single-module installation this function is performed by the UPS Logic
Boards micro-controller system in conjunction with other status signals applied
to D88. However, when the module is connected in a 1+1 configuration it requires
additional circuitry to cater for the parallel control elements of the load transfer
operation i.e. to ensure that both modules transfer the load between inverter and
bypass simultaneously, and also to manage the transfer-to-bypass requirements in
a redundant-module situation. These additional parallel control functions are
provided by the Parallel Logic Board, based on the logic operation within D31.
As illustrated in Figure 8-4, D31 on the Parallel Logic Board produces two signals
associated with load transfer control. The [C_L_INV> output from D31-12 informs
the UPS Logic Board that it is safe (from a paralleling point of view) to transfer
the load to the inverter; and the [O_BUS_INV_L> output from D31-18, which is interlocked with [C_L_INV> within D31, informs the UPS Logic Board whether or
not it is safe to transfer the load to the bypass supply. Both these signals are described in more detail below.
Note: A detailed description of the load transfer control operation during module
start-up is provided in paragraph 2.8.
8-15

2.3.2.1
Load-on-inverter request [C_L_INV>
The [C_L_INV> output from D31 pin 12 goes low when the logic within D31
deems it safe to transfer the load to the inverter, and can be viewed as a load on
inverter request. This is applied to D88 on the UPS Logic Board and, provided
other inputs to D88 are valid, produces a logic high [INV_L> output at D88 pin 36.
This is connected to the Static Switch Driver Board where it activates the inverter
output contactor close circuit; thereby connecting the load to the inverter. To
drive [C_L_INV> low (to request load-on-inverter) all the conditions described
immediately below must be valid.
Module synchronisation validation (D31 pin 7 low)
D30-14 applies a logic high [O_PAR_SYN> signal to D31 pin 24 when it

detects that the module synchronisation conditions are valid. This drives
D31-21 low ([RIP>) which is debounced and inverted at D28-4 to appear as a
logic high [PAR_INV> input to D31-7.
Note 1: the [RIP> signal also energises the VCO-in-loop relays (K1/K2)
which connect the modules synchronisation control circuits to the parallel
frequency control bus (See paragraph 2.4).
Note 2: the [PAR_INV> signal is also used by the available module counter
circuit (See paragraph 2.5.5) and current-sharing relay control circuit (K3/
K4) (See paragraph 2.5.3).
When the TEST mode jumper X6-8 is made (D31-43=low) the [O_PAR_SYN>
signal has no affect on D31, and D31-21 [RIP> is held permanently high.
Valid Available module counter output (D31 pin 27 high)
In a non-redundant system the available module counter is configured to

produce a logic high [C_N_INV> signal only when both modules are available.
In a redundant module system [C_N_INV> goes high when the local module
is available irrespective of the state of the second module.
No load-on-bypass request from system (D31 pin 28 low)
This input is overridden in a 1+1 module due to jumper X6-4 being fitted; the
following description thus applies only when the board is fitted to a module
forming part of a multi-module system.
In a multi-module system, the decision whether to connect the load to the
inverter or bypass supply rests with the UPS Logic Boards micro-controller
system. When it decides to connect the load to the bypass supply, the UPS
Logic Board sends a logic high [O_MNS_L_SS> signal to the Parallel Logic
Board X1 pin 44. This is inverted to a logic low at D23 pin 11
([B_MNS_L_SS>) and connected to the parallel control bus via X2/3 pin 4, and
also reinverted at D26 pin 8 to provide a logic high [MNS_L_SS> input to D31
pin 28 i.e. when the UPS Logic Board is calling for load-on-bypass, the
logic high [MNS_L_SS> input to D31 pin 28 forces D31-12 high to prevent it
from signalling a load-on-inverter request.
Note: due to the fact that the load-on-bypass request from the UPS Logic
Board is connected to the parallel control bus X2/3 pin 4 ([B_MNS_L_SS>), it
affects all modules when either of them is calling for load-on-bypass.
8-16

Non-redundant module conditional logic (D31 pin 29 low)
In a non-redundant system the load must not be transferred to the inverters

unless both inverters are fully operational and connected to the parallel control sync and current-sharing busses. Therefore a circuit is required which
prevents [C_L_INV> requesting load-on-inverter until these conditions are
satisfied.
The circuit which performs this task is again within D31, and acts in response
to the [PAR_INV> signal applied to D31-7 (which is high when the module is
connected to the parallel control bus), and the [C_N_INV> signal from the
available module counter circuit applied to D31-28 (which is high when
both modules are running.
When both these conditions are satisfied, the [O_INV_IND> output from D3120 is driven low. This is inverted to a high at D24 pin 17 and connected to the
parallel control bus (X2/X3-12), and then reinverted to a low at D26 pin 12
([INV_IND>) and applied to D31 pin 29. D31-29 must be low to enable the
[C_L_INV> output from D31 pin 12 to go low and request load-on-inverter.
Note that the parallel control bus action means that these conditions must be
valid in both modules before either module is allowed to request load-oninverter.
In a redundant-module system the [INV_IND> input to D31-29 is overridden
by the removal of the configuration jumper X6-1 and the input to D31-29 has
no effect. (X6-1 must be fitted to obtain non-redundant operation.)
TEST mode of operation
When the TEST mode is selected (jumper X6-8 made) the [C_L_INV> output
at D31-12 is forced low irrespective of the state of the other conditions
described above. This allows the inverter output contactor operation to be
tested while the load is isolated from the inverter through opening the output
power switch.
2.3.2.2
Load-on-bypass request [O_BUS_INV_L>
The [O_BUS_INV_L> output from D31 pin 18 goes low when the logic within D31
deems it unsafe to power the load from the inverter. It can therefore be viewed as
a load on bypass request as, under normal conditions, the UPS system should
always attempt to transfer the load to the bypass supply whenever the inverter
supply becomes invalid (See Figure 8-4).
When requesting load-on-bypass, the low [O_BUS_INV_L> output is inverted to
a high [B_INV_LOAD> at D24-18 from where it is connected to the second module
via the parallel control bus X2/X3 pin 10. It is then re-inverted to a low
[I_BUS_INV_L> at D26-10 from where it is connected to D88 on the UPS Logic
Board. The parallel control bus thus couples together this signal between the two
modules in such a way that both modules will detect the load on bypass request
when it is generated by either module. This is crucial to avoid a potentially catastrophic situation if one module only were to transfer to bypass while the other
remained on inverter.
On the UPS Logic Board, D88 produces a logic high [MNS_L> output at pin 38
provided other inputs to D88 are valid. This is then connected to the Static Switch
Driver Board where it activates the static bypass SCR driver circuit.
8-17

D31 pin 18 [O_BUS_INV_L> is driven low (to request load-on-bypass) if any of

the four conditions described immediately below are valid:
Load-on-bypass request from system (D31 pin 28 high.)
As described above, this input is overridden in a 1+1 module due to jumper

X6-4 being fitted; the following description thus applies only when the board
is fitted to a module forming part of a multi-module system.
The decision whether to connect the load to the inverter or bypass supplies
rests with the UPS Logic Boards micro-controller system. When it decides to
connect the load to the bypass supply, the UPS Logic Board sends a logic
high [O_MNS_L_SS> signal to the Parallel Logic Board X1 pin 44. This is
inverted to a logic low at D23 pin 11 ([B_MNS_L_SS>) from where it is connected to the parallel control bus via X2/X3 pin 4, and also reinverted at D26
pin 8 to provide a logic high [MNS_L_SS> input to D31 pin 28.
Note 1: the [O_MNS_L_SS> signal also inhibits the load on inverter request
from within D31 as described earlier.
Note 2: due to the fact that the load-on-bypass command from the UPS
Logic Board is connected to the parallel control bus ([B_MNS_L_SS>), it
affects both modules when either one of them is calling for load-on-bypass.
UPS Logic Board not commanding load on inverter (D31 pin 25 low.)
D31 pin 25 input is connected to the [INV_L> signal applied to X1 pin 52 and
is logic low when the UPS Logic Board is not commanding the Static Switch
Driver Board to close the output contactor i.e. not commanding load-oninverter.
Module synchronisation invalid (D31 pin 7 low.)
This input is driven low when the [RIP> output from D31 pin 21 is high,
which occurs when there is a sync error between the modules or bypass supply. Also used by the load on inverter request signal [C_L_INV> described
above (See paragraph 2.3.2.1).
In practice this input is normally effective only while the module is being
started, and is unlikely to appear once the modules have achieved initial synchronisation.
When the TEST mode jumper X6-8 is made (D31-43=low) D31-21 is held
permanently high, which allows the load transfer circuit to be tested while the
module is isolated from the load by means of opening the output switch.
Output contactor auxiliary (D31 pin 34 high).
The [N_AUX_CONT> input to D31-34 is controlled by the UPS Logic Board

processor system and is driven high when the output contactor auxiliary contacts are open.
8-18

CHAPTER 2 - "1+1" Configuration Control Principles
Section 8:
2.4
Frequency synchronisation principles
2.4.1
Introduction
When two UPS modules are operating with their outputs connected in parallel,
such as in the case of a 1+1 system, it is of paramount importance that their outputs are synchronised in both phase and frequency to prevent large, damaging,
circulating currents appearing.
Not only must the two modules be synchronised to each other, but they must also
be synchronised to the bypass supply in order to allow a no-break transfer to take
place between the UPS and bypass supplies when called for. The system synchronisation control circuitry is therefore necessarily complex.
This section begins by providing a fairly detailed overview of the frequency control and synchronisation principles and continues with a full description of the
major signals and components employed by this function
2.4.1.1
Inverter frequency control overview
Figure 8-5: Frequency control block diagram

X2/
X3
X1
K1/K2
11
54
54
53
53
[FRQ_PAR>
[FRQ_SYN>
33
3
Micro Controller System
48
48
55
55
[O_MNS
_D_SS>
25
[O_MNS 8
_SYN_OK>
[F_IN>
[FRQ_REF>
D30
ASIC
D29
(PLL)
[FRQ_OSC>
31
13
[PH_COM_2>
5
GVCO
[SYN_INT>
[FRQ_
MNS>
45
FRQ_PAR>
14
45
Parallel Sync Bus
X7
X2
[F_IN>
15
(Bypass Frequency
Single module)
X7
X1
[BACK>
34
34
[INV_F>
Select 50/60Hz
Base Frequency
32
32
[SYNC>
40
UPS Logic Board
[BACK>
[INV_F>
Master
Oscillator
40
[SYNC>
44
27
D1
(Divider)
Osc O/P
Reference
Sinewave
Generator
Clk
14
D6
(PLL)
Inverter Logic Board
In each module the inverter frequency is controlled directly by the master oscillator section of the Inverter Logic Board. As shown in Figure 8-5, the master oscillator comprises a phase-locked-loop (PLL) integrated circuit (D6) and a
frequency divider (D1), both of which are controlled by the UPS Logic Board
micro-control system. The nominal 50/60 Hz oscillator output from D1 pin 27
controls the reference sinewave generator circuits and thus controls the inverter
operating frequency.
8-19

In practice, the VCO section of D6 clocks D1 which divides the clock pulses by
a factor determined by the [INV_F> signal to D1 pin 44. This input thus determines
whether the master oscillator operates at a base frequency of 50Hz or 60 Hz, as
programmed into the UPS Logic Board micro controller system.
The phase comparator section of the PLL (D6) compares the oscillator output (pin
3) with a frequency reference signal ([SYNC> pin 14) which is again supplied by
the UPS Logic Board micro controller system. Any detected phase error between
these two signals will amend the VCO output to the frequency divider which has
the effect of correcting the oscillator output frequency and make it track the
[SYNC> reference frequency. Thus the [SYNC> signal indirectly determines the inverter frequency through its effect on the master oscillator. Note that the UPS
Logic Board also monitors the master oscillator frequency via the [BACK> signal
connected via X1 in 34.
Sync operation in a single-module system
As explained in the Inverter Logic Board detailed description, in the case of a

single-module system the [SYNC> reference signal is made to track a bypass frequency signal [F_IN> which is derived from the bypass R-phase supply via X2 pin
15. Such tracking is performed in software by comparing [F_IN> with [BACK> and
adjusting the [SYNC> reference frequency accordingly. Thus in the simple singlemodule the master oscillator effectively functions within two nested phaselocked loops; the outer one being software controlled and the other being part of
the master oscillator itself.
Sync operation in a 1+1 system
In a 1+1 system, the Inverter Logic Boards master oscillator functions in the
same manner as for a single-module system; however, due to the complex parallel-operating requirements, the [SYNC> reference signal is made to track the
[FRQ_SYN> output of the Governing Voltage Controlled Oscillator (GVCO) on
the Parallel Logic Board, rather than the bypass frequency directly.
The reason for adding this extra layer of complexity to the synchronisation regime
is that it allows the GVCO outputs from both modules to be directly coupled together via the parallel control bus and thereby ensure that the [SYNC> reference
signals are locked together in both modules.
2.4.1.2
Basic GVCO sync principles on module start-up
As shown in Figure 8-5, the GVCO is synchronised to the [FRQ_REF> signal produced at D30 pin 31 via a phase-locked-loop (PLL) circuit (D29). The phase detector section of the PLL detects any phase difference between the [FRQ_REF>
signal (D29-14) and the GVCO [FRQ_SYN> output (D29-3), and produces a frequency correction signal ([PH_COM_2>) which makes the GVCO track the
[FRQ_REF> signal frequency.
The [FRQ_REF> signal itself can be derived from one of two sources i.e. to the
bypass frequency [F_IN> or the parallel sync bus frequency [FRQ_PAR>, as determined by the sync-source selector circuit within D30. Alternatively, if neither
of these signals are present, the PLL can be disabled and the GVCO made to operate at its base frequency (i.e. 50/60Hz).
The selected sync source depends on whether or not the bypass supply is available and the sequence in which the modules are started. A brief description of the
various options is given below:
8-20

Bypass supply present & first module to be started
When the first module is started, the sync source selector circuit within D30
connects the bypass frequency signal [F_IN> present at D30 pin 5 through to D30
pin 31 ([FRQ_REF>). Thus, due to the action of the PLL described above, in this
situation the GVCO synchronises the bypass mains frequency.
When the UPS Logic Board micro controller system detects that the Inverter
Logic Board has gained internal synchronism (i.e. the Inverter Logic Boards
master oscillator PLL is phase-locked) its sends a logic high [O_MNS_SYN_OK>
signal to D30 pin 18 which energises the VCO-in-loop relay (K1/K2).
Note; for reasons of clarity the relay energising circuit is not shown in Figure 8-5.
This relay has several contacts, which are described in detail later: however, the
primary contact, shown in the block diagram, connects the GVCO [FRQ_PAR>
output to the parallel sync bus. This in effect connects the GVCO output of the
first module to be started to the corresponding point (X2/X3 pin 11) in the second
module (which is not yet running).
To summarize the circuit action; at the end of the start-up sequence of the first
module:
its GVCO is synchronised to the bypass supply.
its Inverter Logic Board master oscillator is synchronised to the GVCO
output (therefore the inverter is also indirectly synchronised to the bypass
supply).
the VCO-in-loop relay is energised and the GVCO output is placed onto
the parallel sync bus.
Bypass supply present & second module to be started
When the second module is started, its sync source selector within D30 initially
connects its [FRQ_REF> output (D30-31) to the parallel sync bus frequency reference signal [FRQ_PAR> (D30-6). Thus the action of the PLL phase comparator
effectively synchronises the GVCO of the second module to track the parallel
sync bus frequency (which is in fact derived from the GVCO output from the first
module). This condition can be looked upon at as being a master/slave situation;
whereby the GVCO of the on-coming module is slaved to that of the module already running.
A sync bus comparator circuit within D30 compares the local GVCOs
output with the parallel sync bus signal ([FRQ_PAR> from the first
module), and detects when the local (slave) GVCO is fully synchronised to the
parallel sync bus (master). Notice that this comparator actually monitors the frequency at either side of the VCO-in-loop relay contact which is still open in
the second module at this time.
[FRQ_SYN>
When the sync bus comparator detects that the local GVCO is properly synchronised and UPS Logic Board micro controller system detects that the Inverter
Logic Board has achieved internal sync (i.e. a logic high [O_MNS_SYN_OK>
signal to D30 pin 8), D30 will energise the VCO-in-loop relay (K1/K2) in the
second module.
This has two major affects:
1. It connects the second modules GVCO output to the sync bus in parallel with
the existing GVCO signal from the first module; thus ensuring that both
GVCOs remain fully synchronised from this point onwards.
8-21

2. It makes the sync source selector logic within D30 now select the bypass
frequency [F_IN> as the sync reference source ([FRQ_REF>) instead of the
parallel sync bus [FRQ_PAR> signal. This means that the local GVCO now
tracks the bypass supply frequency directly and is no longer seen as being
slaved to the first module but is in fact acting as a master GCVO in its
own right.
To summarize the circuit action; at the end of the start-up sequence of the second
module:
the GVCO of the first module is synchronised to the bypass frequency.
the GVCO of the second module is also synchronised to the bypass frequency.
the VCO-in-loop relay is energised in both modules, connecting the outputs from both GVCOs together via the parallel sync bus.
Starting a module while the bypass supply is missing
On start-up, if the bypass supply is missing, D30 produces an internal sync command signal ([SYN_INT>) which inhibits the GVCO synchronisation circuit, and
forces it to operate at its base frequency (i.e. 50/60Hz).
In the first module to be started, the VCO-in-loop relay (K1/K2) will be energised when the UPS Logic Board micro controller system detects that the Inverter
Logic Board has achieved internal sync (i.e. a logic high [O_MNS_SYN_OK>
signal to D30 pin 8). This then places the GVCO output (still operating at its base
frequency) onto the parallel sync bus in the same way as described on the previous pages.
When the second module is started it operates in its slave mode, as before, and
initially synchronises to the parallel sync bus (which is at the base frequency of
the first modules GVCO). However, once the sync bus comparator within D30
detects synchronism between the local GVCO and the parallel sync bus, it will energise the VCO-in-loop relay whereupon the module changes over from slave
to master mode.
This situation now presents a problem which must be overcome. That is, both
modules are now operating independently at their base frequency yet connected
together via the parallel sync bus; and no matter how closely the two GVCOs are
matched, their base frequencies are certain to drift apart and thus cause a non-synchronous condition. This potential problem is overcome by a second parallel sync
bus line, (not shown in Figure 8-5), which connects together the integrator sections of both GVCOs via a second contact of the VCO-in-loop relay. This absolutely locks together the GVCOs and ensures they both operate at exactly the
same frequency i.e. act as one. This is explained in more detail in the GVCO
functional description below.
Note: in practice they will adopt the frequency of the fastest running oscillator.
If either module detects that the bypass supply becomes available, the sync
source selector within D30 will remove the GVCO inhibit and connect the
bypass [F_IN> signal through to both modules. Under these circumstances both
GVCOs, acting as one, remain fully synchronised together while they seek and
then track the bypass frequency.
8-22
2.4.2

GVCO Detailed description of operation

Figure 8-6:
Governing VCO Block Diagram
Sync Inhibit
from D30
[FRQ_SYN>
[SYN_INT>
[FRQ_PAR>
Angle
Regulator
Integrator
Comparator
(Schmitt)
[FRQ_OSC>
[PH_COM_2>
X2/
X3
11
From PLL
K2
[C_P>
Frequency
correction
signal
Reference
Voltage
30
Parallel Sync Bus
K1
VCO-in-loop
relays
R18/
R20
Figure 8-6 illustrates a detailed block diagram of the GVCO block shown in
Figure 8-5 complete with its major input/output signal annotations. The complete
circuit is shown on page 2 of the circuit diagram.
The above diagram shows that the GCVO comprises four functional sub-blocks;
namely, the angle regulator, reference voltage, integrator and comparator.
Overview description
Basically, the oscillator function is satisfied by the integrator and comparator

blocks i.e. the integrator provides the comparator with an ramp signal which
causes the comparator output ([FRQ_OSC>) to switch logic states when the ramp
reaches the comparator threshold. This is then fed back to the integrator
([FRQ_SYN>) making the integrator ramp in the opposite direction. Once again
when the ramp reaches the comparators threshold the comparator output
([FRQ_OSC>) switches back to its original state and the integrator ramp is made
to reverse once more. This sequence of events is regenerative and leads to a
square waveform at [FRQ_OSC> and a triangular waveform at the integrator output.
The oscillator frequency is determined by the integrators ramp-rate i.e. if the
ramp rate is increased, it takes less time for the comparator to reach its switching
threshold which results in an increased frequency. The ramp rate is voltage-controlled by the output of the reference voltage block which, in the absence of any
synchronising signal, is set by R18/R20 to produce an oscillator output of 50/
60Hz this is described as the GVCO base frequency. When the GVCO is synchronised to a reference frequency (e.g. bypass supply) an additional correction
voltage is superimposed upon the reference voltage which modifies the GVCO
frequency and makes it track the desired frequency reference.
The angle regulator circuit provides signal conditioning to the correction voltage ([PH_COMP_2>), which is produced by the phase comparator section of PLL
D29 (See Figure 8-5), to control its slew-rate etc.
Each of the sub-blocks mentioned are described in more detail below.
8-23

Reference voltage
The reference voltage circuit comprises a three-terminal regulator (N12) and

four sections of N8.
N12 provides a stable +2.5V at its cathode. This is connected to N8a/b via variable resistor R18, and to N8c/d via R20. Considering N8c/d; N8c inverts the +2.5V
stabilised voltage such that a negative reference voltage appears at D22 pin 3, and
this is again inverted by N8d (unity gain) which provides a positive voltage at D22
pin 5. R20 should be adjusted for -4V at D22-3 and +4V at D22-5. N8a/b operate
in a similar manner to provide positive and negative reference voltages to D22
pins 1 and 2 respectively calibration of R18 is described later.
Integrator & Comparator
These two sub-blocks are so inter-dependant that their operation is best described
together. The integrator comprises N7a-c and the comparator N7d
The circuits operation is best understood by considering one cycle of its operating sequence, beginning with the analogue switches in their states shown in the
diagram as follows:
1. The negative reference voltage on IC22 pin 2 passes through IC29 and is
inverted to a positive voltage at N7a pin 1, which charges C76 via R119. The
output from N7b follows the capacitor voltage and therefore ramps in a positive direction.
2. N7d compares the positive-ramping signal from N7b pin 7 with the positive
threshold present on IC22 pin 4 (set by R20).
3. When the positive-going ramp on N7d pin 12 rises above the positive threshold on pin 13 (which is set by R20 and applied through D22 pins 5-4), its output pin 14 ([FRQ_OSC>) switches from logic low to high, with the following
effects:
a) It drives D23-14 low (sheet 4) which is connected to the parallel sync bus
via X2/X3 pin 11 ([B_FRQ_PAR>) provided the VCO-in-loop relay K1 is
closed. If K1 is closed the [B_FRQ_PAR> signal is also inverted to a high at
D26-2 ([F_PAR>) and fed to D30 pin 6 (sheet 1) from where it is connected
to the internal sync bus comparator.
Note: [F_PAR> is also fed to the UPS Logic Board micro controller system
via X1-54 (sheet 4).
b) The low from D23-14 is inverted to a high at D25-12 ([FRQ_SYN>) which
is fed back to the UPS Logic Board micro controller system (X7-53) as the
frequency reference pulse to which the Inverter Logic Boards master
oscillator is ultimately synchronised.
c) The high [FRQ_SYN> at D25-12 is also fed to D30 pin 33 from where it is
connected to the internal sync bus comparator.
d) Finally, the high [FRQ_SYN> at D25-12 is connected to the control gate of
solid-state switches D22 pins 9 & 10, which makes the switches changeover from their state shown on the diagram.
4. With solid state switches D22 in their new positions, N7a pin 1 now switches
low and discharges C76 through R119.
5. The output from N7b pin 7 follows the capacitor discharge and thus now
ramps in a negative direction.
8-24

6. When the negative-going ramp on IC16 pin 12 falls below the negative
threshold now applied to pin 13 (which is once again set by R20 but now
applied through D22 pins 3-4) the [FRQ_OSC> output at N7d pin 14 switches
from a logic high to logic low.
7. This reverses the signals described in 3a to 3d above, which now revert to
their original logic state. This includes the control gate signals to D22 pins 9
& 10, which now open and cause the above sequence to be repeated.
Frequency calibration. The above sequence shows that the circuit is self oscillating at a rate determined by the voltages set by R18 and R20 as these affect
the ramp rate of the integrator and the comparators switching threshold.
Calibrate R18 and R20 should be calibrated to obtain the GVCO base frequency
as follows:
1. Ensure there are no external sync sources (turn off bypass supply).
2. Adjust R20 to obtain 4.0Vdc at test point X8 pin 3.
3. If necessary adjust R18 to obtain 50Hz (60Hz) at test point X8 pin 2.
Note: jumper X7 shunts R108, which is in R18s resistor chin, and should be
positioned 2-3 (open) when operating at 50Hz and 1-2 (closed) at 60Hz.
Integrator phase locking. In the overview description of the frequency synchronisation principles it was stated that the GVCO will operate at its base frequency if the bypass supply is unavailable. It also explained that under these
circumstances the GVCO integrator sections were locked together between the
two modules to ensure that both GVCOs adopt a common frequency and phase.
In practice, this is achieved by a set of the VCO-in-loop relay contacts (K2) which
directly connect the integrator outputs together on both modules when the relays
are energised. With reference to the circuit diagram, the points in question are annotated <C_P> and <C_0> on page 2, which are connected to the parallel control
bus X2/X3 pins 29 & 30 when K2 is closed (see sheet 4). The effectively connects
together the top of the integrator capacitors (C76) in both modules which ensures
that the integrators in both modules change direction simultaneously thereby
locking the oscillators together absolutely once the VCO-in-loop relay has closed.
Angle Regulator
The angle regulator circuit integrates the [PH_COM_2> frequency error signal
produced by the PLL D29, to provide the GVCO with a suitable frequency correction signal to keep it synchronised to the selected sync source.
The frequency correction signal is applied to N8a, via R104, where it is added to
the reference voltage set by R18. In this way the correction signal is able to
modify the integrator ramp-rate, and thereby modify the GVCO output frequency
in order to synchronise the GVCO to the bypass (or parallel sync bus) frequency.
The correction signal takes the form of an analogue voltage which goes positive
to increase the GVCO frequency and vice-versa.
Relating this to the diagram (sheet 1), the [PH_COM_2> error signal produced at
D29 pin 13 takes the form of a series of positive or negative going pulses of varying width depending on the polarity and magnitude of the detected phase error.
These pulses are converted to an analogue voltage by a complex 4-pole filter
(sheet 2) comprising N9a, D22 (normally made 12 to 14), N10a, IN10b, N10c,
and N10d. N8a ultimately sums the correction signal (via R104) with the reference voltage set by R18.
8-25

The correction signal is inhibited when the bypass supply is unavailable. This is
achieved by the [SYN_INT> output from D30 pin 29 which goes high if the bypass
is missing (or out of limits). This energises D22 control gate (pin 11) which disconnects the [PH_COM_2> from the filter input and replaces it with a 0V level referenced through R84. Under these conditions the correction signal emerging from
N10d pin 14 ramps back to 0V which therefore applies zero frequency correction
to the GVCO which allows it to operate at its base frequency as set by R18.
2.4.3
PLL Phase Comparator (D29)

This circuit is based on the phase-comparator section of a type 4046 phase locked
loop integrated circuit which monitors the GVCO output waveform [FRQ_SYN>
at pin 3 and the selected sync source waveform [FRQ_REF> at pin 14. If these
waveforms are unsynchronised the [PH_COM_2> output at pin 13 exhibits either a
positive or negative going pulse of a width proportional to the detected phase difference. A positive pulse is produced if [FRQ_SYN> leads [FRQ_REF> (i.e. the
GVCO frequency is the greater) and vice versa.
The [PH_COM_2> output pulses are integrated by the angle regulator circuit and
then applied to the GVCO as an analogue error correction signal which modifies
the GVCO operating frequency. Thus if the PLL phase comparator detects an
error it ultimately modifies the GVCO frequency to make it track the [FRQ_REF>
reference frequency.
2.4.4
D30 Parallel Control Functions

Figure 8-7:
[MNS_SYN_OK>
[38] [T>
[37] [SYN_PAR_KO>
[PAR_SYN>
(Reset) [V-AUX>
[BLK_INV>
[INV_OK>
[SYN_PAR>
[FRQ_SYN>
[FRQ_PAR>
18
Internal
Sync
Logic
41
40
29
14
VCO-in-loop
Relay Control
20
38
[O_MNS_SYN_OK>
[F_IN>
[MNS_D_SS>
[O_PAR_SYN>
[CON_PAR> [41]
4
34
39
27
33
Sync Bus
Comparator
28
Sync Source
Selector
37
31
[11] [I_FRQ_MNS>
[SYN_INT>
27
[PH_COM> [40]
[FRQ_REF>
[SYN_PAR>
8
5
25
Bypass
Validation
11
[O_FRQ_MNS> [28]
D30 is an ASIC device containing numerous static logic gates which serve several
functions associated with the frequency synchronisation control; most of which
have been mentioned earlier. For reasons of clarity these are shown in block diagram form in Figure 8-7, although in reality many of these blocks are to some
extent interactive, and share some of the input signals shown.
8-26
2.4.4.1

Bypass validation
This block validates the bypass frequency signal [F_IN> to determine if it is suitable for use by the sync source selector circuit.
The bypass frequency sense signal [F_IN> is connected to D30-5 and is allowed
through D30, to appear at D30-11 as [O_FRQ_MNS> provided both the following
conditions are satisfied:
1. The Inverter Logic Boards master oscillator is phase-locked. Sensed by a
logic low [O_MNS_SYN_OK> input to D30-8.
2. The UPS Logic Board micro controller system has determined that the bypass
supply is within the programmed voltage and frequency limitation. Sensed by
a logic high [MNS_D_SS> input to D30-25.
Note: in each case, these input signals are coupled to both modules via the parallel
control bus via X2/3 pins 7 & 5 respectively; therefore the frequency validation
function of D30 will be affected in both modules if an invalid condition is present
in either module.
Provided the above conditions are satisfactory, the [O_FRQ_MNS> bypass frequency signal output at D30-11 is inverted by D23-13 and reinverted by D26-4
and then reapplied to D30-28 as [I_FRQ_MNS> from where it is internally connected to the sync source selector circuit. The reason for this double-inversion is to
allow the signal at D23-13 to be coupled to the second module via the parallel
control bus via X2/X3 in 15. Thus, once again the [I_FRQ_MNS> input to D30-28
is applied to both modules even if the bypass frequency is being sensed by one
module only.
2.4.4.2
Sync source selector
This circuit determines whether the bypass frequency signal [I_FRQ_MNS> (pin
28) or parallel sync bus signal [FRQ_PAR> (pin 6) is allowed through D30 to
appear at pin 31 as the frequency reference signal [FRQ_REF>. Whichever is the
case, the [FRQ_REF> signal produced at D30-31 provides the main frequency reference signal to the PLL phase comparator and therefore dictates the GVCO operating frequency.
Under normal circumstances the circuit selects the bypass frequency reference
signal [I_FRQ_MNS> except for the case where the module is the second to be started, whereupon it momentarily selects the parallel sync bus signal [FRQ_PAR> until
it becomes fully synchronised i.e. during the period of slave operation (See
paragraph 2.4.1.2).
A second output from the sync source selector, at D30-27, goes high when the
parallel sync bus is the selected frequency reference and illuminates led H3.
Under normal circumstances, LED H3 should therefore illuminate briefly when
the second module is started and then remain extinguished while the module is
synchronised to the bypass supply.
The external conditions necessary to select the parallel sync bus as the reference
signal, and illuminate H3, are as follows (all conditions must be valid):
1. External reset signal is not applied (D30-4 = low).
2. VCO-in-loop relay K1 is closed in the first module (D30-4 = low).
3. VCO-in-loop relay K1 is open in the local module (D30-14 = low).
4. [BLK_INV> signal to D30-34 = high (no inverter problem).
8-27

5. [INV_OK> signal to D30-39 = high (no inverter problem).

Note: once the VCO in loop relay becomes energised in the local module, the
[PAR_INV> signal from D28-4 to D30-26 goes high and overrides the effects
of the [INV_OK> signal within D30.
2.4.4.3
Sync bus comparator
The sync bus comparator circuit monitors the frequency of the local GVCO
output ([FRQ_SYN> applied to D30-33) and the parallel sync bus ([FRQ_PAR> applied to D30-6) and drives the [PH_COMP> output at D30 pin 37 low when the two
monitored signals are in-phase. This output is inverted and debounced by D27 and
its associated R-C components, and then fed back to D30 pin 40 as a logic high
[SYN_PAR_KO> signal which is then internally connected to the VCO-in-loop
relay control circuit.
In practice the two monitored signals are taken from either side of the VCO-inloop relay contacts and therefore indicate when it is safe to close the relay (K1/
K2) from a parallelling viewpoint.
2.4.4.4
VCO-in-loop relay control
This circuit determines when it is safe to close the VCO-in-loop relay (K1/K2),
by driving [O_PAR_SYN> (D30-14) high, and thus connect the GVCO output to
the parallel sync bus.
The circuits internal logic is affected by the following signals:
External reset [V_AUX> at D30-4.
[PAR_SYN> at D30-20.
[BLK_INV> at D30-34
[INV_OK> at D30-39
Note: once the VCO in loop relay becomes energised in the local module,
the [PAR_INV> signal from D28-4 to D30-26 goes high and overrides the
effects of the [INV_OK> signal within D30.
[SYN_PAR_KO> at D30-40
The logic state (and sequence) of these signals required to energise K1 depends
on whether the module in question is the first or second module to be started, as
described below:
First module to be started
1. As there is no module yet connected to the parallel sync bus, the [PAR_SYN>
input to pin 20 is high.
2. Provided there is no problem with the inverter control, the [INV_OK> and
[SYN_PAR_KO> status signals to pins 34 and 39 are both high once the
inverter has run-up.
3. The above conditions drives the [CON_PAR> output on pin 38 high, which is
then inverted, debounced and delayed by R151/C107/D27, and applied to pin
41 as a logic low ([T1>).
4. Provided there is no reset applied to pin 4 (low) and the inverter status signals
to pins 34 and 39 are still both valid (high), the logic low [T1> input to pin 41
will drive pin 14 high and energise the VCO-in-loop relay (K1/K2) via
[O_PAR_SYN> and one section of D24 (test point X12-1 = low).
5. When the VCO-in-loop relay energises:
8-28

a) It connects the GVCO (and integrator) output to the parallel sync bus.
b) A further contact closes and places a logic low signal to D30 pin 20 in
both modules (via the parallel control bus). This has no effect on the current module, but will inform the second module (when it is started) that
the first module is already running.
6. In addition to energising the VCO-in-loop relays (K1/K2), the [O_PAR_SYN>
output from D30-14 also signals the parallel status to D31-24 which drives
D31-21 low (provide not in test mode). (See paragraph 2.3.2.1). One effect
of this is that D31 applies a logic high [PAR_INV> signal to D30 pin 26 which
overrides the [INV_OK> signal.
7. The [O_PAR_SYN> output at pin 14 will remain high, holding-on relay K1/K2
unless one of the following conditions occur:
a) The reset signal is applied to D30 pin 4 (high).
b) The [BLK_INV> signal to pin 39 goes to an invalid state (low).
c) Both the [INV_OK> signal to pin 34 and the [PAR_INV> signal to pin 26 go
simultaneously low
d) The sync bus comparator detects a problem [SYN_BUS_KO> to pin 40
goes low. This is unlikely to occur in the first module unless K1 is faulty,
or the is a printed circuit board fault.
Second module to be started
1. As the first module is already running and its VCO-in-loop relay is closed,
connecting its GVCO output to the parallel sync bus, the [PAR_SYN> input to
pin 20 is low.
2. Provided there is no problem with the inverter control, the [INV_OK> and
[SYN_PAR_KO> status signals to pins 34 and 39 are both high.
3. When the sync bus comparator detects that the local GVCO and the parallel
synch bus are in-phase, the [SYN_PAR_KO> input to pin 40 will go high.
4. The above conditions drives the [CON_PAR> output on pin 38 high, which is
then inverted, debounced and delayed by R151/C107/D27, and applied to pin
41 as a logic low ([T1>).
5. Provided there is no reset applied to pin 4 (low) and the inverter status signals
to pins 34 and 39 are still both valid (high), the logic low [T1> input to pin 41
will drive pin 14 high and energise the VCO-in-loop relay (K1/K2) via
[O_PAR_SYN> and one section of D24 (test point X12-1 = low).
6. When the VCO-in-loop relay energises, the GVCO output is connected to the
parallel sync bus via one contact of K1. A second K1 contact closes which
reinforces the logic low signal to D30 pin 20 in both modules (via the parallel
control bus).
7. The [O_PAR_SYN> output at pin 14 will remain high to hold on relay K1/K2
unless the conditions described above with respect to the first module occur.
2.4.4.5
Internal Sync Logic
This logic block is responsible for detecting when it is unsafe to synchronise the
GCVO to the [FRQ_REF> signal, but instead make it operate at its base frequency (See paragraph 2.4.2).
8-29

The [SYN_INT> output at pin 29 goes high to invoke the GVCO base-frequency
operation (also described as internal sync), and can be brought about by any one
of the following four logic combinations:
Reset
1. If an external reset [V_AUX> signal (high) is applied to pin 4. Note that this is
sourced from the software reset circuit on the UPS Logic Board.
Inverter problem
2. If either of the inverter status signals to D30 pins 34 and 39 are invalid (low),
while the local module is not connected to the parallel sync bus (pin 14 low)
but the second module is connected to the parallel sync bus (pin 20 low).
Note: if such an inverter problem occurs at D30-34 it will trip the local modules VCO-in-loop relay, as described above, therefore driving pin 14 low
automatically.
Inverter Logic Board loses internal sync
3. If the Inverter Logic Board master oscillator loses sync ([MNS_SYN_OK> pin
18 high) when either module is connected to the parallel sync bus
([PAR_SYN> pin 20 low OR [O_PAR_SYN> pin 14 high). Note that if such a
situation occurs it should affect both modules in an identical manner as both
are connected via the parallel control bus via X2/X3 pin 7 (low).
8-30

Section 8:
2.5
Output current sharing
2.5.1
Introduction
Figure 8-8: Simplified current-sharing circuit (R-phase)
R1
X1
CT Neutral 14
LOCAL
15
R-ph current
R1
R1
R42
N1a
R30
R36
X1 Current
N1c
R48
3
10
DV-A
20
R21
X2/3
Current
sharing 27
RL-K3/4
bus
3
2
N4a
R11
5
6
R11
D21
N1b
12
7
R1
R31 13
14
To Selective
shutdown
circuit
sharing error
signal
[ DV-A >
To Inverter
Logic Board
(via UPS Logic
Board)
11
0
ABIL_RIP
The current sharing circuit is shown on sheet 3 of the circuit diagram.

In a 1+1system the inverters should share the load current equally when both
modules are connected to the critical bus.
The current sharing circuit shown above controls this function by comparing the
two modules currents via a current sharing line of the parallel control bus and
generating an error signal if a difference is detected. The error signal is passed to
the Inverter Logic Board where it modifies the local inverters output voltage, by
up to 5%, in order to restore a balanced current sharing condition. This action is
undertaken on an individual phase basis and an error signal is thus produced for
each of the three inverter phases.
The following text describes the operation of the R phase current sharing circuit
in detail the other two phases work in an identical manner. Figure 8-8 shows a
simplified diagram of the R-phase circuit used in the description.
2.5.2
Current sharing error detection principles

The local modules R phase output current sense signal ([IO_A>) enters X1 pins 15
(signal) and 14 (neutral) and is buffered by N1a. The ac signal at N1 pin 1 is thus
proportional to the current being drawn from the local module, and connected to
N1c pin 9, via R30/R36, and also to N4a pin 3, via R21/R24.
RL-K3 energises when the [PAR_INV> signal from IC31 pin 7 goes high, which
occurs just after the VCO-in-loop relay is energised. RL-K3 contacts connect the
local current sense signal passing through R21 onto the parallel control bus at X2/
3 pin 27. Notice that due to the parallel bus connection, X2/3 pin 27 is connected
directly to the corresponding point on the Parallel Logic Board in the second module.
Circuit operation when one module only is running
When a module is shut-down (off-line) its RL-K3 is de-energised and solid state
switch D21 is open (contacts as shown) because [ABIL_RIP> is low due to the fact
that the inverter output contactor is open. These conditions force the current sharing error signal [Dv-R> to zero volts, as the current sense signal from N1a is fed to
8-31

N1c pins 9 and 10 in anti-phase and are self cancelling.

Note: R10 and R11 are of equal value (3k9).
In a redundant-module configured 1+1 system it is permissible to operate on
one module only (i.e. with the second module shut down). Under these conditions
D21s contacts change over when the inverter output contactor is closed
([ABIL_RIP> = 1) and the current sense signal at N1a pin 1 is now buffered by N4a
and N1b and connected to N1c pin 10 via R31, D21 and R37.
However, R31 is of equal value to R30 (6K8), and once again the anti-phase signals applied to IC1c pins 9 and 10 will be of equal magnitude and keep the error
signal at 0V. Put simply, under these conditions the lone module attempts to current-share with itself and is therefore never in error.
Note: In this scenario RL-K3 energises, and connects the current sense signal to
the current sharing bus line once the module is synchronised, but this has no affect
on the current sharing circuits operation at this time as RL-K3 remains open in
the second (shut-down) module.
Current sharing operating under balanced conditions
When the second module is started, its current sense signal is applied to the current sharing parallel control bus X2/3 pin 27 (via its RL-K3).
Assuming that both modules are supplying exactly the same amount of load current, the current sense signal produced by N1a will be of the same amplitude and
phase in both modules; therefore there will be no net current flow through R21 in
either module and thus no net voltage dropped across it.
Figure 8-9:
Module 1
X1
Sense
Amp
15
N1a
8
Error
Amp
1Vac
1
X2/X3
X2/X3
R21
9
N1a
1Vac
N1c
Dv-R 20
Module 2
RL-K3
10
27
1Vac
9
10
Unbalanced current
15
N1c
R21
RL-K3
27
CN1
Sense
Amp
20 Dv-R
Error
Amp
This is illustrated in Figure 8-9, where a current sense signal of 1Vac is assumed
in both modules. Under these conditions the input signals to the error amplifier
(N1c) are equal and produce zero [Dv-R> error signals to the Inverter Logic
Board these conditions are the same in both modules.
8-32

Current sharing operating under unbalanced conditions
Figure 8-10:
Module 1
X1
Sense
Amp
15
N1a
8
Error
Amp
N1a
1
1Vac
2Vac
X2/X3
N1c
Dv-R 20
Module 2
R21
9
RL-K3
10
Unbalanced current
27
X2/X3
1.5Vac
CN1
Sense
Amp
15
N1c
R21
RL-K3
27
9
10
20 Dv-R
Error
Amp
If the two modules supply different amounts of load current their current sense
signals at N1a will be different and there will be a net current flow along the current sharing parallel control bus, resulting in a voltage drop across R21 in each
module proportional to the degree of current imbalance.
This is depicted in Figure 8-10, which shows the situation where Module 1 is supplying more current than module 2.
In this case the current sharing control bus voltage (1.5Vac) is less than the current sense signal (2Vac) in module 1 but greater than the current sense signal
(1Vac) in module 2. In Module 1 the voltage dropped across R1 produces a greater voltage at N1c inverting input with respect to its non-inverting input and the
[Dv-R> error signal (X1-20) will be a sinusoidal signal in anti-phase with the current sense signal.
In Module 2 however these conditions are reversed, with the greater voltage being
applied to the non-inverting input of N1c, resulting in a [Dv-R> error signal which
is in-phase with the current sense signal.
The respective [Dv-R> error signals are applied to each modules Inverter Logic
Board; and in this case the signal to Module 1 will cause a reduction of the output
voltage and that to Module 2 will cause a corresponding increase thus restoring
a balanced load current condition.
Note: the above action is dynamic in operation and in practice the circuit effectively maintains a balanced state, with zero current flowing along the current sharing bus, at all times.
2.5.3
Current-sharing relay control (K3/K4)

Under normal circumstances, relays K3 and K4 are energised and de-energised at
the same time as the VCO-in-loop relays (K1/K2); in fact all four relay share a
common control signal i.e. the [O_PAR_SYN> output from D30 pin 14 (see paragraph 2.4.4.4 on page 8-28).
The only control difference between these two relay groups is that in the case of
the current-sharing relays the [O_PAR_SYN> signal is gated with the TEST mode
logic within D31 and the ultimate relay control signal ([PAR_INV>) is produced at
D31 pin 7. [PAR_INV> is driven to a logic high to energise K3/K4 this is inverted
to a logic low at the relay driver D24 pin 13.
When the Parallel Logic Board is placed in its TEST mode (D31 in 43 taken low)
the [PAR_INV> control signal at D31 pin 7 is forced to a permanent low logic state
to prevent the current sharing relays being energised. This is required in a redun-
8-33

dant module system to allow an off-line module to be tested without affecting the
current-sharing function of the second (on-line) module.
2.5.4
Selective shutdown
The Selective Shutdown circuit, which is shown on sheet 3 of the circuit diagrams, monitors the current-sharing circuit output signals together with output
phase voltage sense signals and detects three types of current-related fault conditions:
1. It detects when the current sharing is in error and calling for the local module
to provide an excessive amount of current in comparison to the other module.
2. It detects an excess reverse power condition whereby a fault in the local
module is causing it to draw current into its output terminals from the other
module.
3. It detects an excess forward power condition whereby a fault in the local
module is causing it to feed current into the output terminals of the other
module.
Considering the R phase circuit: the current error signal produced at N1c pin 8
([Dv-A>), described on the previous pages, is fed to N1d pin 13 via R48 where it
is summed with a sense signal proportional to the modules output R-phase voltage ([VO_A>). The VA-proportional output from N1d pin 14 is connected to a
three-phase full-wave rectifier, along with the corresponding S and T phase signals (V1-V6), which then produces a single VA-related signal across R61 which
is proportional to the modules three phase output.
Under balanced conditions the current error signal [Dv-A> is negligible; and the
output from N1 pin 14 is directly proportional to the voltage sense signal. Under
such circumstances the bridge rectifier produces approximately 4.1V at N5 pin 1.
2.5.4.1
Current-sharing error
If the current sharing function fails to operate correctly and calls for this module
to produce an excessive amount of current in comparison to the second module,
the [DV-R> [DV-S> [DV-T> signal(s) add to the voltage-related signals and result in
an increased output from IC5a pin 1.
This is monitored by N5d whose output goes high if N5a pin 1 rises above 5.0V
(equivalent to 30% of nominal current sharing imbalance) i.e. if the module is
being asked to produce 30% of nominal load capacity more than the second module. The resulting logic high [IN_SEL> signal flags D31 pin 4 which turns off the
inverter and trips the output contactor (see paragraph 2.3.1.1 on page 8-13).
Calibration
N5ds switching threshold is determined by a reference voltage generator (N11)

whose output voltage is calibrated by R19. This resistor should be adjusted according to the modules working voltage to obtain the following dc voltage at the
top of R68 (junction with R72):
380V = 5.0 Vdc
400V = 5.26 Vdc
415V = 5.46 Vdc
8-34
2.5.4.2

Reverse Power detector
If the local modules output voltage suddenly decreases due to an internal fault
condition it will begin to take reverse current from the second module. Under
these circumstances the current sense signals will be out of phase with, and therefore subtract from, the voltage sense signals. The VA signal at N5a pin 1 will
therefore reduce and ultimately fall below the operating threshold of N5c, whose
output will in turn go high and invoke the [IN_SEL> shutdown signal with the same
results as the current error situation described above.
Due to the current imbalance, the current-sharing circuit in the second module
will call for it to reduce its output voltage, and the falling voltage sense signals
will cancel out the increasing forward current signals. Thus the [IN_SEL> signal is
not triggered in the second module and the healthy module will not be tripped offline in a redundant module system. However, in a non-redundant system the
second module will trip of line automatically along with the faulty local module.
Calibration
This function shares the same calibration features as the current-sharing error circuit described previously.
2.5.4.3
Forward Power detector
If the local modules output voltage suddenly increases due to an internal fault
condition it will attempt to supply all the load current and also feed a reverse current into the second module. Under these circumstances, in the local module, the
summation of the VA signals at N5 pin 1 triggers the upper level detector N5d and
the [IN_SEL> signal is activated in the same manner as described for a currentsharing fault.
Due to the current imbalance, the current sharing circuit in the second module will
call for it to increase its output voltage and the rising voltage sense signals will
cancel out the decreasing reverse current signals. Thus the [IN_SEL> signal is not
triggered in the second module and the healthy module is not tripped off-line in a
redundant module system.
In a non-redundant system the second module will trip of line automatically along
with the faulty local module. However, in a non-redundant system the second
module will trip of line automatically along with the faulty local module.
2.5.5
On-line module counter

This circuit, shown on sheet 2 of the circuit diagrams, detects the number of online modules and is used in a redundant system to inhibit the selective shutdown
circuit within D31 when only one module is on-line i.e. if only one module is
running, and by definition providing all the load current, there is no valid reason
to allow its current sharing circuit to produce a selective shutdown and trip the
module off-line (see paragraph 2.3.1.1 on page 8-13).
When a module is brought on-line, the signal used to energise the VCO-in-loop
relays (K1/K2) is also fed to the module counter circuit as [PAR_INV>. This signal
goes high when the module is on-line, whereupon it turns on V43 and V42 which
provides a current source whatever resistance value is selected by jumpers X5. In
a standard configuration X5 jumpers 1/2/3 are made. This in turn causes a voltage
rise to the non-inverting input of comparator N9b (pin 5) via R130.
is connected to the parallel control bus via X2/3 pin 24, therefore
when both modules are on-line the current passing through the selected resistance
doubles, with a corresponding increase to the voltage offered to the comparator.
<O_N_INV>
8-35

The comparators operating threshold is determined by the resistance selected by

X4. In a standard 1+1 configuration X4 jumper 1 only is fitted, which sets the circuit operation such that [C_N_INV> switches high only when both modules are on
line, and is low at all other times.
Note: the reason for the additional jumper positions on X4 and X5 is to allow this
board to be used in a multi-module system, where up to six modules can co connected in a parallel-operating configuration. Where such a system is used, X4 and
X5 permit the minimum number of on-line modules necessary to retain system integrity to be programmed.
2.6
Parallel rectifier operation
2.6.1
Rectifier current-sharing control

If a single stand-by battery bank is used by both modules the installation is described as having a common battery, and in this situation steps are taken to
ensure that both modules contribute an equal amount of battery charge current.
A current sharing circuit, similar to that used to control the output current sharing,
is employed to ensure that both modules rectifiers take an equal amount of input
current. Consequently, if the modules input currents are equal and their output
currents are equal this implies that they are properly sharing the battery charge
current.
The local modules input current sense signal ([I_RECT_T>) enters X1 pin 24 and
is buffered by N6a. The signal at N6a pin 1, is then connected to N6b pin 6 and
also to N6c pin 10 via R66.
If the local module is the only module on-line, as part of a redundant module system, the inputs to N6b pins 5 and 6 will cancel each other as they are both obtained
from the same source e.g. pin 6 monitors the current sense signal from N6 pin
1 and pin 5 monitors the same signal via a second buffer (N6c). Under such circumstances the output from N6b pin 7 is zero, which then produces a zero error
signal output ([DB>) at X1 pin 25. X1 pin 25 is connected to the voltage regulation
control circuit on the Rectifier Logic Board, via a through connection on the UPS
Logic Board, and trims the rectifier voltage as necessary to adjust its input current.
Rectifier current sharing is enabled by energising relay K5. This removes the
ground inhibit from N6d non-inverting input and also connects the local current
sense signal (<IM_R>) passing through R66 to the current sharing bus connected
to X2/3 pin 26.
When the second module is started, its input current sense signal is applied to the
parallel control bus X2/3 pin 26 in the same manner as described for the local
module. Assuming that both modules are drawing exactly the same amount of
input current, there will be no net current flow through R55 in either module, resulting in zero output from IC8b pin 7.
If the modules draw different amounts of input current their current sense signals
differ and there will be a net current flow along the parallel control bus resulting
in a volts drop across R66 proportional to the current imbalance in each module.
This will be detected by N6c, whose output will increase [DB> in the module
drawing less current and decrease [DB> in the other. This processes is continuous
and results in close input current sharing between the two modules at all times
under normal conditions.
8-36

Relay K5 control
As mentioned above, relay K5 must be energised in order to activate the rectifier

current sharing function; this is achieved by the [O_PAR_REC> output from D30
pin 17 going high. D30 pin 17 is itself controlled by the [PAR_REC> input to D30
pin 32 which is derived from the UPS Logic Board micro controller system and
goes high to select parallel rectifier operation i.e. when the UPS Logic Board is
programmed to invoke rectifier current sharing (common battery) it sends a logic
high [PAR_REC> signal to D30 pin 32 whose [O_PAR_REC> output then switches
high to energise relay K5. This can be overridden by jumper X6-2 which, when
made, clamps [O_PAR_REC> to a logic low. X6-2 is used to select parallel or
non-parallel rectifier operation (open for non-parallel operation) and also affects
the boost charge and battery test functions as described below.
2.6.2
Boost charge control

In a common battery system it is not permissible to have one module operating in
the boost charge mode while the other is in float charge, otherwise they will be
unable to share the battery charge current.
Boost charge is requested by the UPS Logic Boards micro controller system
which applies a logic high [O_BST_BAT> input to X1 pin 47. This is connected to
the parallel control bus via X2/3 pin 8 ([B_BST_BAT>), and also to D30 pin 24
([BST_BAT>). Sending the signal through the parallel control bus thus drives the
[BST_BAT> signal high in both modules if either module requests boost charge.
When [BST_BAT> goes high it drives D30 pin 16 high, which is then connected
back to the UPS Logic Board via X1 pin 35 ([I_BST_BAT>) to inform the UPS
Logic Board that the request has been acknowledged. The UPS Logic Board will
then initiate the boost charge mode via appropriate signalling to the Rectifier
Logic Board. Therefore, in a parallel rectifier configured system both rectifiers
are triggered into the boost mode.
If parallel rectifier operation is not required then jumper X6-2, when fitted, will
override the boost charge request logic within D30 and clamp the output on D30
pin 16 at logic low. In this situation the signal passed along the parallel control
bus will have no effect in either module and the boost mode will be independently
controlled for each rectifier.
2.6.3
Battery test control

In a common battery system it is not permissible to have one module operating in
the battery mode without the other, otherwise they will be unable to share the battery charge current. A control mechanism similar to the boost charge circuit described immediately above is therefore used to prevent this from happening.
Battery Test is requested by the UPS Logic Boards micro controller system
which applies a logic high [O_TST_BAT> input to X1 pin 46. This is connected to
the parallel control bus via X2/3 pin 13 ([B_TST_BAT>), and also to D30 pin 21
([TST_BAT>). Sending the signal through the parallel control bus thus drives the
[TST_BAT> signal high in both modules if either module requests a Battery Test.
When [TST_BAT> goes high it drives D30 pin 19 high, which is then connected
back to the UPS Logic Board via X1 pin 36 ([I_TST_BAT>) to inform the UPS
Logic Board that the request has been acknowledged. The UPS Logic Board will
then initiate the Battery Test via appropriate signalling to the Rectifier Logic
Board. Therefore, in a parallel rectifier configured system both rectifiers are triggered into the Test mode.
8-37

If parallel rectifier operation is not required then jumper X6-2, when fitted, will
override the Battery Test request logic within D30 and clamp the output on D30
pin 19 at logic low. In this situation the signal passed along the parallel control
bus will have no effect in either module and the Battery Test mode will be independently controlled for each rectifier.
2.7
Other Features and functions
2.7.1
Ribbon cable connection monitor

As mentioned on page 8-13, the Parallel Logic Board senses the parallel control
bus integrity by monitoring the continuity of the two ribbon cables fitted X2 and
X3, which are cross connected between the two modules. The modules parallel
operation can be maintained if one of these cables becomes disconnected (in
which event Led H2 illuminates), but if both cables become disconnected then the
Parallel Logic Board demands that the module inverters are shut-down and the
load transferred to bypass.
Monitoring the cables continuity is made possible due to the way that the cables
are cross-connected between the two modules; the error detection signals are annotated [A_CON> and [B_CON> (see page 4 of the circuit diagrams). For example,
the [A_CON> signal at X2 pin 1 is held at 0V due to the fact that pin 1 of X3 in the
second module is grounded the same principle applies to the [B_CON> signal at
X3 pin 2. Thus, the Parallel Logic Board can detect if a ribbon cable is disconnected at either end.
8-38

Section 8:
2.8
Parallel Logic Board circuit operation during start-up

When the UPS system is started, there are distinct phases that the module goes
through before the load is connected to the inverter(s). These can broadly be described as:
Initialisation/reset
Run-up & inverter synchronisation
Connecting to the parallel control bus
Load transfer procedure (depending on system redundancy)
These phases are described in detail below and aims to give a full understanding
of the system start-up process to facilitate system troubleshooting.
2.8.1
Initialisation/reset
When a module is first started, its UPS Logic Board micro-system goes through
a power-up reset and initialisation routine which applies a 1-second logic high
pulse to X1-42 ([V_AUX>). The effects of this are:
1. D31-5 goes high to reset the selective shutdown circuit latch (D31-37 set
low and led H1 = off) (See paragraph 2.3.1.1)
2. D30-4 goes high which:
a) drives D30-29 ([SYN_INT>) high which forces the GVCO to its internal
sync mode (See paragraph 2.4.4.5).
b) drives D30-38 & D30-14 low to reset the VCO-in-loop control logic and
ensure the VCO-in-loop relays (K1/K2) are de-energised ([O_PAR_SYN> =
low) (See paragraph 2.4.4.4).
3. D30-14 ([O_PAR_SYN>) going low is connected to D31-24 where it drives
D31-21 ([RIP>) high which is inverted to a logic low [PAR_INV> at D28-4
which then:
a) de-energises the current-sharing relays (K3/K4).
b) informs the available modules counter circuit that the module is off-line.
c) places a logic low input to D31-7 which enables the load-on-bypass
request from D31-18 (low) and disables the load-on-inverter request
from D31-12 (high) (See paragraph 2.3.2).
d) feeds a logic low input to D30-26 which enables the [INV_OK> signal
applied to D31-39 within D31.
2.8.2
Inverter run-up and synchronisation

1. Provided the UPS power switches and parallel bus cables are positioned correctly, at the culmination of the reset action D31-19 ([OFF_INV>) should go
low, requesting the inverter to run (See paragraph 2.3.1)
2. If other parameter on the UPS Logic Board are satisfactory, the inverter
should now start and its voltage should begin to rise to nominal value; during
which time the following events occur:
a) [O_MNS_SYN> to D30 pins 8 and 18 go low when the Inverter Logic
Boards master oscillator gains internal sync. The input to pin 8 is associ-
8-39

ated with the bypass frequency validation circuit (See paragraph 2.4.4.1)
and the input to pin 18 with the GVCO internal sync logic although
[SYN_INT> is still high, requesting internal sync at this time due to the
still logic low [INV_OK> input to D30 pin 34 (See paragraph 2.4.4.5).
b) The [BLK_INV> input to D30 pin 34 is high, indicating that there is no fault
detected on the Inverter Logic Board once again this has no effect on
D31 internal operation due to the logic low [INV_OK> input to D30 pin 34.
2.8.3
Connecting to the parallel control bus

When the inverter output voltage rises to its nominal value the [INV_OK> input to
D30 pin 39 will go high, and initiate the following sequence of events:
1. The [SYN_INT> output from D30-29 will go low to enable the GVCOs angle
regulator circuit, allowing the GVCO to synchronise to the selected
[FRQ_REF> signal (See paragraph 2.4.4.5).
2. Provided the synchronisation functions are satisfied, the VCO-in-loop relays
(K1/K2) will be energised by D30-14 ([O_PAR_SYN>) going high. The synchronisation functions vary according to whether the module is the first or
second module to be started and is described in details in paragraph 2.4.4.4.
If K1/K2 fail to energise at this stage it is recommended that you read and
thoroughly understand paragraph 2.4.4.4 before going further.
3. D30-14 ([O_PAR_SYN>) going high is connected to D31-24 where it drives
D31-21 ([RIP>) low which is inverted to a logic high [PAR_INV> at D28-4
which then:
a) energises the current-sharing relays (K3/K4).
b) feeds a logic high input to D30-26 which disables the effects of the
[INV_OK> input to D31-39 within D31.
c) informs the available modules counter circuit that the module is connected to the parallel control bus and available for use.
d) places a logic high [PAR_INV> input to D31-7 which disables the load-onbypass request from D31-18 (now switches high) and enables the loadon-inverter request from D31-12 (although D31-12 is not driven low due
to this signal at this point see below).
2.8.4
Load transfer to inverter

The point at which the load is transferred to the inverter depends on whether the
Parallel Logic Board is configured for a redundant or non-redundant system
operation i.e. jumper X6-3 closed = redundant configuration and X6-1 closed
= non-redundant.
The difference between these configuration is that in a redundant system the
load can be allowed to transfer to inverter when only one module is running, but
in a non-redundant system both modules have to be running before the load is
allowed to transfer. The effects of the configuration on the transfer circuit operation are described below.
Redundant system transfer operation
1. In a redundant module configuration the available module counter circuit

is configured such that its [C_N_INV> output switches high when only one
module is connected to the parallel control bus. Thus, in such a system this
8-40

occurs at this point in the start-up sequence.

2. The effects of the logic high [C_N_INV> input to D31-27, coupled with the
logic high [PAR_INV> input to D31-7 now make D31-12 ([C_L_INV>) switch
low, sending a load-on-inverter request to the UPS Logic Board.
3. If the UPS Logic Board conditions are normal it should now send a transfer
to inverter command to the Static Switch Driver Board which will closed the
inverter output contactor and turn off the static bypass SCRs.
Non-redundant system transfer operation
4. In a non-redundant system two sets of signals, each of which detects the

availability of both modules on the parallel control bus, are required by the
transfer control logic before the load is allowed to transfer to the inverter.
a) In a non-redundant module configuration the available module counter
circuit is configured such that its [C_N_INV> output switches high only
when both modules are connected to the parallel control bus
b) The logic high [PAR_INV> input to D31-7 is inverted to a logic low
[O_INV_IND> at D31-8. This is inverted to a high at D24-17 from where it
is connected to the parallel control bus via X2/X3 pin 12. Due to the parallel control bus, the [INV_IND> input to D31-29 is thus logic low only if
both modules are available (i.e. if [O_INV_IND> is low in both modules).
5. The effects of the logic high [C_N_INV> input to D31-27, coupled with the
logic high [PAR_INV> input to D31-7 and low [INV_IND> input to D31-29, now
make D31-12 ([C_L_INV>) switch low, sending a load-on-inverter request to
the UPS Logic Board.
6. If the UPS Logic Board conditions are normal it should now send a transfer
to inverter command to the Static Switch Driver Board which will closed the
inverter output contactor and turn off the static bypass SCRs.
Applicable to both system configurations
7. Once the load has transferred to the inverter two key signals are sent back
from the UPS Logic Board to the Parallel Logic Board:
a) First, a lockout signal slaved to the inverter output contactor auxiliary contacts applies a logic high [N_AUX_CONT> input to D31-34 which prevents
the load on bypass request from being generated at D31-18 while the
contactor is closed.
b) Second, a logic high inverter on load status signal ([INV_L>) is fed back
to X1-52 which is connected to:
D31-31 (low) to enable the selective shutdown circuit within D31.
D31-25 (high) to provide a second lockout to the load on bypass
request circuit within D31 in the same manner as [N_AUX_CONT>
described above.
via a debounce circuit, [INV_L> produces a logic high [ABIL_RIP> signal
which energises the current-sharing circuit solid-state switches to activate
the current-sharing facility (See paragraph 2.5.2).
8. The UPS Module is now running and on-line, and its synchronisation and
load-sharing signals are connected to the second module via the parallel control bus.
8-41

2.8.5
Load retransfer back to bypass

Under normal circumstances the load should remain on inverter at all times, and
transfer back to the bypass supply only if inverter is no longer available. There are
several mechanisms which can initiate a transfer to bypass request, as outlined
below.
Loss of one module in a non-redundant system
This condition will be detected by the available module counter circuit

([C_N_INV> = low) and once the faulty module has tripped off-line, also by the
parallel bus line X2/X3-12 which will produce a low [INV_IND> to D31-29.
Either of these signals will send D31-12 high, removing the load on inverter request to the UPS Logic Board which will respond by providing a logic low
[INV_L> signal to D31-25 which drives D31-18 low to produce a load on bypass
request.
Note: Once the inverter output contactor opens the load on bypass request is sustained by the inverter output contactor auxiliary contacts which now hold D31-34
high.
Inverter Block [BLK_INV>
If the [BLK_INV> input to D30-34 is driven low by the UPS Logic Board, either
due to an inverter fault or selected shutdown etc, it drives D30-14 ([O_PAR_SYN>)
low which then drives D31-21 ([RIP>) high and releases K1/K2 (and by association also K3/K4) to trip the module off the parallel control bus.
This also provides a low [PAR_INV> input to D31-7 which disables the load on
inverter request. The effects of this are as described above.
Note: if any of the signals which affect the [O_PAR_SYN> output from D30-12
switch to a fault level it has the same effects as the [BLK_INV> signal going low, as
described,
2.9
Test mode of operation:

A test facility is built into the Parallel Logic Board control system which allows
the module to be fully run up without its output being connected to the system
i.e. in a redundant module system this facilitates the full testing of one module
whilst the other remains on-line to provide the load supply.
The test mode is activated by fitting jumper X6-1, which pulls D31-43 down to
0v (logic low) with the following affects:
1. It interlocks with the [SW_OUT> input to D31-14 such that the [OFF_INV> output at D31-19 is allowed to turn the inverter on (low) only if the modules
output switch is open.
2. It forces D31-21 ([RIP>) high which ensures that relays K1/K2 (and by association K3/K4) remain open. This prevents placing a faulty module onto the
parallel control bus synchronisation and current-sharing lines.
3. If forces D31-12 ([C_L_INV>) low to provide the UPS Logic Board with a
continuous load on inverter request. This overrides all other inputs to D31
normally required to generate such a request.
4. It disables the selective shutdown logic within D31.
8-42

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Section 8: 1+1 UPS System Control

Chapter 1 - "1+1" Configured Systems

11pm.fm5 - Issue 2 Dated 21/08/97

SECTION 8 - 1+1 UPS System Control

7200 Series UPS Service Manual

2.7 Other Features and functions .................................................................. 8-38

11pm.fm5 - Issue 2 Dated 21/08/97

Section 8: "1+1" Configured Systems

Chapter 1 - "1+1" Configured Systems

Inter-Module Parallel Control Logic

Inter-Module Parallel Control Logic

1+1 Power circuit considerations

1+1 Control circuit considerations

11pm-c1.fm5 - Issue 2 Dated 21/08/97

SECTION 8 - "1+1" Configured Systems

7200 Series UPS Service Manual

Figure 8-2: 1+1 Control Logic

High Voltage I/F Bd

High Voltage I/F Bd

Redundant system. In a redundant system, if one module fails the remaining

11pm-c1.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual

SECTION 8 - "1+1" Configured Systems

Non-redundant system. In a non-redundant configuration, if one module

11pm-c1.fm5 - Issue 2 Dated 21/08/97

SECTION 8 - "1+1" Configured Systems

7200 Series UPS Service Manual

11pm-c1.fm5 - Issue 2 Dated 21/08/97

Chapter 2 - Parallel Logic Board 4520075B

As mentioned above, connectors X2 & X3 are cross-connected from one module

Used to detect that the ribbon cable is connected

If a module applies an [O_BLK_SW> signal to X1-43 it

If a module applies an [O_MNS_D_SS> signal to X1

This is taken high when the VCO-in-loop relay (K1) is

The [O_MNS_SYN_OK> signal to X1-48 informs the

11pm-c2.fm5 - Issue 2 Dated 21/08/97

SECTION 8 - "1+1" Configured UPS System Control

Used when common battery system is used to force

This line couples together the [O_MNS_DIS> input to

This line couples the load-on-bypass request and is

Used when common battery system is used to force

High when Maintenance Bypass Switch is closed in

7200 Series UPS Service Manual

This line carries the bypass (mains) frequency signal

These two lines are used to parallel the battery current

These lines carry the current sharing sense signals

11pm-c2.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual

SECTION 8 - "1+1" Configured UPS System Control

Output voltage sense signals derived on the High

Input from rectifier current sense amp on Rectifier

This output is the result of the rectifier current sharing

11pm-c2.fm5 - Issue 2 Dated 21/08/97

SECTION 8 - "1+1" Configured UPS System Control

Output to UPSLB which, when high, initiates Battery

Output to UPSLB which, when high, initiates Battery

The input to X1-49 from the UPSLB goes high.

Output to inverter ON/OFF control logic on UPSLB.

Output to load-on-inverter control logic on UPSLB.

Input from the reset circuit on the UPSLB which,

Input from the UPSLB reset generator chip which

Input from the UPSLB software-controlled inverter off

This input is used by the load transfer control logic