Experiment 1

Aim:-Layout of Resistor for given value.

Circuit Diagram:-

Theory: - Software Used is L-edit

L-edit: L-Edit, meets needs by combining the fastest rendering available with powerful features
that exceed the needs of the most demanding user. Whether you are creating analog or mixed
signal ICs, MEMS, or sensors, this leading design tool enables you to get started with minimal
training.
We have designed 1k and 10k resistances using L-edit.

Calculation:-R=PL/A
Where A=W.t , P/t=23.6 thus while making 1k resistance L=85 um
Making 10k resistance L=850um

Observation and Result:-

L-edit Fig for 1k resistance

R1 1 2 R=1.003k
* R1 PLUS MINUS (1 23 41 29)
* Total Nodes: 2
* Total Elements: 1
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VLSI Design & Simulation Lab 2

* Total Number of Shorted Elements not written to the SPICE file: 0

L-edit Fig for 10k Resistance

Result:-R1 1 2 R=10.005k

Learning Outcome:Thus we learned to make two different resistance of 1k and 10k using W=2u=2 lambda and
P/t=23.6 i.e. for poly metal. Further e can design different valued resistance.

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VLSI Design & Simulation Lab 2

Experiment 2
Aim:- Plot the static voltage transfer characteristics of a symmetric CMOS inverter utilizing the
data points of drain current vs drain to source voltage (Vds) for NMOS and PMOS.

Circuit Diagram:-

Theory:- CMOS is short for Complementary Metal-Oxide Semiconductor. CMOS is an onboard, battery powered semiconductor chip inside computers that stores information.
So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
I = C (DV/Dt) -> Dt = (C/I) DV
Calculation:- To Plot Id vs. Vds characteristic in first quadrant calculation required is:- Level 1
Parameters
Vgsn=Vin
Vgsp=Vin-Vdd
Vdsn=Vout
Vdsp=Vout-Vdd

Vgsn=Vin
Vgsp+Vdd=Vin
Vdsn=Vout
Vdsp+vdd=Vout

Observation & Results

Tspice Code for Nmos and Pmos
For Nmos
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VLSI Design & Simulation Lab 2

.model nmos nmos Level=1

+ Vto=1.0

Kp=3.0E-5

Phi=0.65

Lambda=0.02

Nsub=1.0E+15

+ Tpg=1.00

Gamma=0.35
Tox=0.1u

Nss=1.0E+10

Uo=700.0

Ld=0.8u

Af=1.2

Kf=1.0E-26

Is=1.0E-15

Js=1.0E-8

Pb=0.75

Cjsw=1.00E-9

Mjsw=0.33

Cgbo=2.0E-10

Cgdo=4.00E-11 Cgso=4.00E-11

Rd=10.0

Cj=2.0E-4

Rs=10.0

Mj=0.5
Fc=0.5

Rsh=30.0

.model pmos pmos Level=1

+ Vto=-1.0

Kp=3.0E-5

Phi=0.65

Lambda=0.02

Nsub=1.0E+15

+ Tpg=1.00

Gamma=0.35
Tox=0.1u

Nss=1.0E+10

Uo=700.0

Ld=0.8u

Af=1.2

Kf=1.0E-26

Is=1.0E-15

Js=1.0E-8

Pb=0.75

Cjsw=1.00E-9

Mjsw=0.33

Cgbo=2.0E-10

Cgdo=4.00E-11 Cgso=4.00E-11

Rd=10.0

Cj=2.0E-4

Rs=10.0

Mj=0.5
Fc=0.5

Rsh=30.0

m1 d1 g1 0 0 nmos w=10u l=10u

vgs g1 0
vds d1 0
.dc vds 0 5 0.1 vgs 0 5 1
.print I(m1,d1)
.end

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VLSI Design & Simulation Lab 2

T spice Fig For Nmos at different Vgs

Similarly For Pmos

m1 d1 g1 vdd vdd pmos w=10 l=10
vdd vdd 0 5
vgs g1 vdd
vds d1 vdd
.dc vds 0 -5 0.1 vgs 0 -5 1
.print I(m1,d1)
.end

T spice Fig of Pmos for different Vgs

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VLSI Design & Simulation Lab 2

Matlab Code
Nmos=[V I];
Pmos=[V I];

idn=nmos(:,2);
idp=pmos(:,2);
vdsn=nmos(:,1);
vdsp=pmos(:,1);

idp1=idp(1:51);
idp2=idp(52:102);
idp3=idp(103:153);
idp4=idp(154:204);
idp5=idp(205:255);
idp6=idp(256:306);

idn1=idn(1:51);
idn2=idn(52:102);
idn3=idn(103:153);
idn4=idn(154:204);
idn5=idn(205:255);
idn6=idn(256:306);

vdsp1=vdsp(1:51);
vdsp2=vdsp(52:102);
vdsp3=vdsp(103:153);
vdsp4=vdsp(154:204);
vdsp5=vdsp(205:255);
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VLSI Design & Simulation Lab 2

vdsp6=vdsp(256:306);

vdsn1=vdsn(1:51);
vdsn2=vdsn(52:102);
vdsn3=vdsn(103:153);
vdsn4=vdsn(154:204);
vdsn5=vdsn(205:255);
vdsn6=vdsn(256:306);

plot(vdsn1,id1n)
hold on
plot(vdsn2,id2n)
hold on
plot(vdsn3,id3n)
hold on
plot(vdsn4,id4n)
hold on
plot(vdsn5,id5n)
hold on
plot(vdsn6,id6n)
hold on
plot(5+vdsp1,-id1p,'r')
hold on
plot(5+vdsp2,-id2p,'r')
hold on
plot(5+vdsp3,-id3p,'r')
hold on
plot(5+vdsp4,-id4p,'r')
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VLSI Design & Simulation Lab 2

hold on
plot(5+vdsp5,-id5p,'r')
hold on
plot(5+vdsp6,-id6p,'r')
hold on
figure
vin=[0 1 2 3 4 5]
vout=[5 5 4.7 0.2 0 0];
plot(vin,vout)
Matlab Figures

Vin Vs. Vout charecteristics for Cmos

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VLSI Design & Simulation Lab 2

Vds Vs.Id Charecteristics For Cmos

Learning Outcome:We learn to plot nmos,pmos charestristics in Tspice and then using Tspice .out files in Matlab to
Check Id vs Vds and Vin vs Vout.Further Some modification done to hold the waveform and
plot both nmos and pmos Charesteristics in First Quadrant.

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VLSI Design & Simulation Lab 2

Experiment 3
Aim:- Analysis of switching point(switching threshold) of a cmos inverter and study its
variations with reference to transconductance parameter

Kr

and supply voltage

V DD

Circuit Diagram:-

Cmos Inverter
Vm is defined as the intersection of the line Vin = Vout and the inverter VTC. In this region, both
the NMOS and PMOS transistors are in saturation since VDS = VGS. The voltage dropped
across the NMOS device equals the voltage dropped across the PMOS device when the input
voltage is VM. For a very short time, both devices see enough forward bias voltage to drive
them to saturation.
In first graph, we plot drain voltage vs gate voltage at different nmos width in T-spice. Since all
Kr
other terms remains contant except width of nmos, so value of
changes. As we know
that

Kn

w n . un

Kp

w p. up

Kr

=Kn/Kp

.
C ox

C ox

/l

/l

The graph has two plots, and the intersection point gives value of input voltage at particular
Kr
Kr
width of nmos or at particular
. We repeat this experiment at different values of
and note the intersection point i.e vin.
Similarly,in second graph if we vary supply voltage i.e vdd we examine graphs the center point
Vm
or intersection point which is known as
.
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VLSI Design & Simulation Lab 2

Calulation
FOR KR
As we know that
Kr
Here,

Kn

w n . un

C ox

Kp

/l and

w p. up

C ox

/l

=kn/kp. So, we find vin at different value of k.

wp

remains constant

wn

10

20

30

40

50

Kr

Vin

2.5

2.25

2.11

2.01

1.94

2
1.05

1
0.43

For Vdd
Here at different Vdd we plot values of switching point i.e Vm.
Vdd
Vm

5
2.5

4
2

3
1.5

Obsevation and Results:Tspice nmos and pmos Level 1 parameters

.model nmos nmos Level=1
+ Vto=1.0
Kp=3.0E-5
Gamma=0.35
+ Phi=0.65
Lambda=0.02 Tox=0.1u
+ Nsub=1.0E+15 Nss=1.0E+10 Ld=0.8u
+ Tpg=1.00
Uo=700.0
Af=1.2
+ Kf=1.0E-26
Is=1.0E-15
Js=1.0E-8
+ Pb=0.75
Cj=2.0E-4
Mj=0.5
+ Cjsw=1.00E-9 Mjsw=0.33
Fc=0.5
+ Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11
+ Rd=10.0
Rs=10.0
Rsh=30.0
.model pmos pmos Level=1
+ Vto=-1.0
Kp=3.0E-5
Gamma=0.35
+ Phi=0.65
Lambda=0.02 Tox=0.1u
+ Nsub=1.0E+15 Nss=1.0E+10 Ld=0.8u
+ Tpg=1.00
Uo=700.0
Af=1.2
+ Kf=1.0E-26
Is=1.0E-15
Js=1.0E-8
+ Pb=0.75
Cj=2.0E-4
Mj=0.5
+ Cjsw=1.00E-9 Mjsw=0.33
Fc=0.5
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+
+

Cgbo=2.0E-10 Cgdo=4.00E-11 Cgso=4.00E-11

Rd=10.0
Rs=10.0
Rsh=30.0

Tspice code for Cmos

m1 d1 g1 0 0 nmos w=10u l=10u
m2 d1 g1 vdd vdd pmos w=10u l=10u
vin g1 0
vdd vdd 0 5
.dc vin 0 5 0.1
.plot v(d1) v(g1)

Cmos Charecteristics

we write matlab code of above readings and We get exponential graph between k and vin.
MATLAB CODE
Using above calculated Data
For Kr
k=[1 2 3 4 5];
vin= [2.5 2.25 2.11 2.01 1.94];
plot(kr,vin)

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VLSI Design & Simulation Lab 2

Kr vs vin plot

FOR VDD
MATLAB CODE
vm=[2.5 2 1.5 1.05 0.43];
vdd= [5 4 3 2 1];
plot(vdd,vm);

Learning outcomes: In this experiment I have learnt

Plot kr vs vin
Plot vdd vs vin

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Experiment 5
Aim: Measure the propagation delay of symmetric CMOS inverter and analyze its variation
with supply voltage.

Circuit Diagram:-

Theory:-Switching speed - limited by time taken to charge and discharge, CL.

Rise time, tr: waveform to rise from 10% to 90% of its steady state value.
Fall time tf: 90% to 10% of steady state value .
Delay time, td: time difference between input transition (50%) and 50% output level.

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Fig : Propagation delay graph

The propagation delay tp of a gate defines how quickly it responds to a change at its inputs, it
expresses the delay experienced by a signal when passing through a gate. It is measured between
the 50% transition points of the input and output waveforms as shown in the figure 16.1 for an
inverting gate. The defines the response time of the gate for a low to high output transition, while
refers to a high to low transition. The propagation delay as the average of the two.

Calculation:- No need to calculate any value Tspice itself shows the calculated result
As we vary the different value of input voltage, we get the following values:
Vdd
Tphl
Tplh

5
84.77
84.38

4.5
68.7
11.2

4
52.57
15.71

Observation and Results

.model nmos nmos Level=1
+ Vto=1.0

Kp=3.0E-5

Phi=0.65

Lambda=0.02

Nsub=1.0E+15

+ Tpg=1.00
+

Kf=1.0E-26

Pb=0.75

Gamma=0.35
Tox=0.1u

Nss=1.0E+10

Uo=700.0
Is=1.0E-15
Cj=2.0E-4

Ld=0.8u

Af=1.2
Js=1.0E-8
Mj=0.5

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VLSI Design & Simulation Lab 2

3.5
36.10
23.59

2.5
0.39
-500

Cjsw=1.00E-9

Mjsw=0.33

Cgbo=2.0E-10

Cgdo=4.00E-11 Cgso=4.00E-11

Rd=10.0

Rs=10.0

Fc=0.5

Rsh=30.0

.model pmos pmos Level=1

+ Vto=-1.0

Kp=3.0E-5

Phi=0.65

Lambda=0.02

Nsub=1.0E+15

+ Tpg=1.00

Gamma=0.35
Tox=0.1u

Nss=1.0E+10

Uo=700.0

Ld=0.8u

Af=1.2

Kf=1.0E-26

Is=1.0E-15

Js=1.0E-8

Pb=0.75

Cjsw=1.00E-9

Mjsw=0.33

Cgbo=2.0E-10

Cgdo=4.00E-11 Cgso=4.00E-11

Rd=10.0

Cj=2.0E-4

Rs=10.0

Mj=0.5
Fc=0.5

Rsh=30.0

m1 d1 g1 vdd vdd pmos w=10u l=10u

m2 d1 g1 0 0 nmos w=10u l=10u
c1 d1 0 10pf
vdd vdd 0 5
v1 g1 0 pulse(0 5 0 1fs 1fs 0.5us 1us)
.tran 0.01us 1us
.plot v(d1) v(g1)
.measure tran tphl trig v(g1) val=2.5 rise=1 targ v(d1) val=2.5 fall=1
.measure tran tplh trig v(g1) val=2.5 fall=1 targ v(d1) val=2.5 rise=1
.measure tran trise trig v(g1) val=2.5 rise=1 targ v(d1) val=2.5 rise=1
.measure tran tfall trig v(g1) val=2.5 fall=1 targ v(d1) val=2.5 fall=1
.end
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Measurement result summary

tphl = 8.4775e-008

tplh = 8.4388e-008

Similarly
trise = 5.8439e-007
tfall = -4.1523e-007
Matlab Code:vdd=[5 4.5 4 3.5 2.5];
tphl=[84.77 68.70 52.57 36.10 0.39];
plot(vdd,tphl);
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Vdd vs TpHL

Learning Outcome:We learn to check values of Tphl,TpLh,Trise,Tfall of an square pulse

input using the Ac Transient analysis.Further we ploted vdd vs delays using matlab.

Experiment 4
Aim:-Noise Margin of Inverter Based Circuits
a)Calculate Noise Margin for CMOS inverter when Vm=2.5
b)Calculate same noise margin Values for Nmos inverter with Resistance and Nmos Load

Circuit Diagram:-

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VLSI Design & Simulation Lab 2

a)Cmos Inverter

b)Resistance as Load

c)Nmos as Load

Theory:The transfer function of a digital inverter will typically look something like this:

Note that there are essentially three regions to this curve:

I.

The region where vI is relatively low, so that the output voltage vo is

high.

II.

The region where vI is relatively high, so that the output voltage vO is

low.

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VLSI Design & Simulation Lab 2

III.

The transition region, where the input/output voltage is in an

indeterminate state (i.e, an ambiguous region between high and
low.

Calculation:Noise Margin for Resistance as load in Nmos Inverter

VOH=4.92

VIL=1.22

VOL=1.11

VIH=2.50

NM(L)=VIL-VOL=0.11
NM(H)=VOH-VIH=2.42
Noise Margin for Cmos Inverter
VOH=4.96

VIL=1.52

VOL=1.51

VIH=3.233

NM(L)=VIL-VOL=0.01
NM(H)=VOH-VIH=1.73
Noise Margin for Nmos as Load
VOH=3.968
VOL=0.47

VIL=1.3
VOH=4.96

NM(L)=VIL-VOL=0.83
NM(H)=VOH-VIH=2.36

Observation & Results

T spice code for Cmos Inverter
m1 d1 g1 0 0 nmos w=10u l=10u
m2 d1 g1 vdd vdd pmos w=10u l=10u
vin g1 0
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VLSI Design & Simulation Lab 2

vdd vdd 0 5
.dc vin 0 5 0.005
.plot v(d1) v(g1)
.end

Fig for Cmos Inverter

MATLAB CODE:
cmos=[Vinput,Voutput];
vin=cmos(:,1);
vo=cmos(:,2);
y=diff(vo);
x=diff(vin);
z=y./x;
vin1=vin(2:51);
plot(vin1,z)
PLOT:

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For voh:
cmos=[Vinput,Voutput];
vin=cmos(:,1);
vo=cmos(:,2);
plot(vin,vo)

T spice code for Resistance as Load

m1 d1 g1 0 0 nmos w=10u l=10u
r1 vdd d1 100k
vin g1 0
vdd vdd 0 5
.dc vin 0 5 0.005
.plot v(d1) v(g1)
.end

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Fig for Resistance as Load

MATLAB CODE:
vin=cmos(:,1);
vo=cmos(:,2);
y=diff(vo);
x=diff(vin);
z=y./x;
vin1=vin(2:51);
plot(vin1,z)

cmos=[ Vinput,Voutput];
vin=cmos(:,1);
vo=cmos(:,2);
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plot(vin,vo)

WHEN NMOS IS AT LOAD:

******************************************************

.model nmos nmos Level=1

+ Vto=1.0

Kp=3.0E-5

Phi=0.65

Lambda=0.02

Nsub=1.0E+15

+ Tpg=1.00

Gamma=0.35
Tox=0.1u

Nss=1.0E+10

Uo=700.0

Ld=0.8u

Af=1.2

Kf=1.0E-26

Is=1.0E-15

Js=1.0E-8

Pb=0.75

Cjsw=1.00E-9

Mjsw=0.33

Cgbo=2.0E-10

Cgdo=4.00E-11 Cgso=4.00E-11

Rd=10.0

Cj=2.0E-4

Rs=10.0

Mj=0.5
Fc=0.5

Rsh=30.0

.model pmos pmos Level=1

+ Vto=-1.0

Kp=3.0E-5

Phi=0.65

Lambda=0.02

Nsub=1.0E+15

Gamma=0.35
Tox=0.1u

Nss=1.0E+10

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VLSI Design & Simulation Lab 2

Ld=0.8u

+ Tpg=1.00

Uo=700.0

Af=1.2

Kf=1.0E-26

Is=1.0E-15

Js=1.0E-8

Pb=0.75

Cjsw=1.00E-9

Mjsw=0.33

Cgbo=2.0E-10

Cgdo=4.00E-11 Cgso=4.00E-11

Rd=10.0

Cj=2.0E-4

Rs=10.0

Mj=0.5
Fc=0.5

Rsh=30.0

m1 d g 0 0 nmos w=10u l=10u

m2 vdd vdd d d nmos w=10u l=10u
vin g 0
vdd vdd 0 5
.dc vin 0 5 0.1
.plot v(d)v(vin)
.end

MATLAB CODE:
cmos=[ Vinput,Voutput];
vin=cmos(:,1);
vo=cmos(:,2);
y=diff(vo);
x=diff(vin);
z=y./x;
vin1=vin(2:51);
plot(vin1,z)

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cmos=[ Vinput,Voutput];

vin=cmos(:,1);
vo=cmos(:,2);
plot(vin,vo)

Learning Outcome:We learn the variation occurred due to change in Cmos inverter as resistance as a load & Nmos
as a Load.Thus we conclude Noise Margin of resistance is better than Cmos inverter and Nmos
as load

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