A

Low-Voltage High-Drive Differential Amplifier

For ISDN Applications
A. Gola'

L. Tomasini

R. Castello*

Abstract
A CMOS differential buffer amplifier for ISDN applications is reported. The chip operates from a
single 5 V power supply and can deliver a 6 Vpp 80 kHz signal into a load of 100 ohm and/or 300 pF
with a THD of about 0 25 % The circuit main feature is its PSRR which remain practically constant
from de to several hundred kHz around -75 dB for both positive and negative supplies with the
common mode voltage generated ou chip. The step response at
% for the same loading conditions
is less than 500 nsec for a step of +1.51' and less than 1 sec for a step of -f-GV. By using relatively
small devices at the output the amplifier occupies an area of only 1720 square mils in a 2.5 mi n-well
CMOS technology

Introduction

1
The

large majoiitv

of analog blocks have

traditionally been realized in bipolar technology which is

par

large capacitive and/or small resistive

loads. However, in recent years, CMOS has become the dominant technology for complex large digital
systems. This has resulted in a continuous increase in the level of performance required to the peripheral
analog cells \t the same time, due to technological constraints, the supply voltage for such circuits has
been reduced from 10 V to 5 V leading to possible further reductions to 3.3 V in the near future.
These characteristics are all present in the ISDN "U" interface system whose analog section is required to
drive a full swing signal of approximately 100 kHz into a load of 100 ohms or less and up to few hundreds
picofarad using a single 5 V supply with good linearity and maximum power efficiency
This paper reports on the first truly differential circuit of this kind which achieves levels of performance
comparable and in some cases superior to the characteristics of single ended amplifiers intended for sim
ilar applications [1,2,5]. In particular the circuit displays a supplv rejection that remains practically flat
ticularly advantageous when designing circuits required

in the range from

Different

to drive

to few hundred kHz.

Topologies

for CMOS Buffer

Amplifiers

Fully different ia! transe ondw tanc e op amps have been widely used for applications like switched capacitor
filters and A/D or D/A converters in mixed digital-analog systems [3]. Such amplifiers have a larger
dynamic range and have greater immunity to the digital noise which is always present in such systems
However, virtually all the circuits interfacing with the outside world have been realized in single ended
fashion [2,5] because the signals used in these circuits are generally referenced to ground Even circuits
which drive a differential load have been designed with two single ended circuits both referenced to an
intermediate voltage [1] instead of a trulv differential circuit.
The advantages of using a trulv differential amplifier are not immediately obvious without an extensive
circuit analysis nonetheless this solution offers some potential benefits in terms of noise immunity over
single ended amplifiers especially when a single supplv is used On the other hand the trulv diffrentixl
solution poses some new difficult design problems due to the interaction of the differential amplifiei and
the common mode feedback circuit This is a more severe problem than in transcondutance amplifiers
since in buffer amplifiers the differential and common mode loads can be very different.
In the design reported here the amplifier drives a purely differential load. We have adopted a truly
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ESSCIRC88

differential topology since it is the most natural choice and because the circuit must have a good supply
rejection in the 100 kHz range. This choice has, however, required using particular care to insure circuit
stability due to the large difference between the time constant of the differential load (i.e. 100 ohms in
parallel with few hundred pF) and the time constant of the common mode load (i.e. a resistance close to
an open circuit in parallel with few tens of pF). A description of the circuit solutions used is given next

Circuit Architecture

A block diagram of the overall circuit architecture is shown in Fig. 1. It consists of a folded cascode input
stage with its common mode feedback circuit, shown in Fig. 2, driving a class a/b differential intermediate
stage (Fig.3). This circuit provides a rail to rail signal at the gate of the output complementary devices
supplying the current drive for the load shown in Fig. 4 with its common mode feedback circuit.
This solution allows the use of reasonably small output transistors (P-channel of 2800/3 and n-channel
of 1000/3) when compared with other designs [2] while at the same time achieving a 6 Vpp output signal

into
One

differential load of less than 100 ohms.

disadvantage of the above solution is that the output transistors enter the linear region of operation,
resulting in large distortion, while they provide the peak current to the load, flowever, an important
advantage is the larger bandwidth,or larger gain at the frequency of the signal to be processed, due to the
non dominant pole located at higher frequency which is an inherent feature of the small output devices.
When used in a closed loop feedback configuration this circuit can take advantage of the larger available
gain to greatly reduce the open loop non linearities. Both simulations and measurements show that this
solution is a viable alternative to the more area intensive solution used elsewhere [2] at least up to an
overall linearity requirement in the 60 dB range around lOOkhz
Besides the differential amplifying path two common mode feedback circuits are necessary to establish
the proper common mode bias as shown in Fig. 1. Two distinct common mode circuits are necessary
because the signal runs differentially from input to output in order to avoid using the noisv analog grown
within the differential path.
Small signal stability is assured by using nested miller compensation [4] in the differential path and two
simple miller compensation in the two common mode cirruits

Experimental

Results

amplifier described in the previous section was realized using a 2.5/xm CMOS n-well technology
requiring active area of 1720 square mils A microphotograph of the chip prototype is shown in Fig.
5. The amplifier achieves a c gain of more than 110 dB, when driving a differential load of 100 ohm, and
an extrapolated gain band product of about 11 Mhz The circuit was compensated to give an adequate
stability when used in an inverting configuration with a gain of 1.5 therefore the closed loop bandwidth
is about 4.5 Mhz. All measured results reported below correspond to such a configuration. The amplifier
response to a small and large signal step is shown in Fig. 6. The settling time to 1 % is less than 500
nsec and l/jser respectively. It is important to point out that the settling time is basically unchanged
for any combination of 100 ohm and /or 300 pf differential load, demonstrating the very stable design
The slew rate is about l^V/fisec. The linearity of the circuit is depicted in Fig. 7 where the second and
third harmonics are plotted versus output signal amplitude for a 80 kHz sinusoidal input. A distortion
of about 0.25 % is achieved for a 6 V pp signal. The PSRR for both positive and negative supply versus
frequency is shown in Fig. 8 in the range from c to 1 Mhz. These measurements were taken with the
common mode signal generated on chip. The remarkable flatness of these curves well beyond 100 kHz is
one of the main features of this circuit and demonstrates the advantages of the fully differential approach
when high immunity to the supply noise is required especially at high frequency. A summary of the
amplifier performance is shown in Table I.
The buffer

an

Conclusions

truly differential CMOS buffer amplifier has been described. The circuit achieves excellent
power supply rejection, especially at high frequency, and good linearity while using <omparativelv small
size output devices. The circuit operates from a single 5 V supply and is intended for applications which
The first

ESSCIRC88

238

interface differentially with the load. Its ability to operate in noisy environments makes it particularly
suitable for applications where digital system and analog peripheral cells share the same substrate.
An improved version of the circuit is presently under developments with shorter (2.5 ^m) channel lengths
and using a modified common mode circuitry. Simulations predict a 40 to 50 % improvement in linearity
with the same power consumption and a 25 % reduction in the overall area.

Acknowledgment

The authors wish to thank S.Mariam* and S.Sala for the careful

layout

Reference
[1] D. Sallaerts,

D. H. Rabaey, R. F. Dierckx, J. Sevenhans, D. R. Haspeslagh and B. J. Ceulaer, "A

Single-Chip U-Interface Transceiver for ISDN", IEEE J. Solid-State Circuits, vol. SC-22, pp. 1011-

1021, December 1987.

[2]

J. A. Fisher and R. Koch, "A Highly Linear CMOS Buffer Amplifier" IEEE J. Solid-State Circuits,
vol. SC-22, pp. 330-334, June 1987.
H. Ohara, H. X. Ngo, M. J. Armstrong, C. F. Rahim and P. R. Gray, "A CMOS Programmable
Self-Calibrating 13-bit Eight-Channel Data Acquisition Pheripheral", IEEE J. Solid-State Circuits,
vol. SC-22, pp. 930-938, December 1987.
J. H. Huijsing and D. Linebarger "Low-Voltage Operational Amplifier with Rail-to-Rail Input and
Output Ranges" IEEE J. Solid-State Circuits, vol. SC-20, pp. 1144-1150 December 1985.
J. A. Fisher "A High-Performance CMOS Power Amplifier" IEEE J. Solid-State Circuits, vol. SC-20,

[3]
[4]
[5]

pp.

1200-1205,December

r-a^i
Cr\

1985

LC?
outp

rccT<

Fig.

tfrt.

rccT-

1 Block

diagram of the circuit

1,

Fig. 2 Input stage schematic

Ce,*

Fig. 3 Intermediate stage schematic

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Fig. 4 Output stage schematic

Fig. 5 Chip microphotography

U(32,58)

HOa

12

Tine

sec

>

7
8
*i6E-6.

e.ee a.se i.ee .sa a.ee a.se 3.ee 3.se 4.ee 4.se s.ae s.se .ae

Fig. 6 Ampi, step response

PiRRf

HD3

P3RR-

Fig.

7 Measured distortion

*\

TABLE 1

PERFORMANCE SUMMARY
(Power Supply -5V)
PARAMETERS

MEASURED RESULTS

Gain Band Product

Open Loop Geln
Power Dissipation

Voffset

11 MHz
>

3 S IV

Output swlnj, 1 I THO

(Rl> let Oh, CL. 366 pf)
Heraonlc Distorsion
Vout=6Vpp
(ft. <. KHz, RL-16 Oh.,C1
316 pF)

6 4 Vpp

HD I
NO3

Slew rite
CARR

1KHZ

Fig.

8 PSRR

1BKHZ

versus

frequency

leeKHZ

1MHZ

55 dB
56 dB
1

1 KHz

PSR

1 KHz
ne KHz
1 KHz
lee KHz

/ mee

lte dB
as da

IM KHz

PSR

l?e dB

16 aU

ae dB

ESSCIRC'88

7 dB
74 dB
7 dB

240