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BINARY
ARITHMETIC,
DECODING AND
MUX LOGIC UNITS
Lesson 7
Demultiplexer
• Demultiplexer
• 1 of 2 and 1 of 4 line demultiplexer
• 1 of 8
• Decoder from demultiplexer
• Demultiplexer
• 1 of 2 and 1 of 4 line
demultiplexers
• 1 of 8 line demultiplexer
• Decoder from demultiplexer
F0 I Y0
A Y1
* means tristate or 1 or 0. F0 is a
Boolean Function or logic circuit output
Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 10
1 of 2 Demultiplexer with inactive 0
output
Input Address-select input Outputs
I A Y0 Y1
F0 = 1 0 1 0
F0 = 1 1 0 1
1 I Y0
A Y1
0 I Y0
A Y1
Y0
F0 I Y1
Y2
Y3
A1
A0
* means tristate or 1 or 0
Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 14
Outline
• Demultiplexer
• 1 of 2 and 1 of 4 line
demultiplexers
• 1 of 8 line demultiplexer
• Decoder from demultiplexer
• Demultiplexer
• 1 of 2 and 1 of 4 line
demultiplexers
• 1 of 8 line demultiplexer
• Decoder from demultiplexer
Y0
Address A0 Y1
Select Y2
Input bits
A1
A2 Y3
Y4
0 I
Y5
G Y6
Y7
Ch10L7-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 19
Summary
Demultiplexer