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To extract circuit models from your layout, we need to run Extraction. For this, click on Verify->
Extract in the layout editing window. Extractor window will show as shown in figure below.
After running extraction operation, if there are no errors, we will see the result as below.
And also a new file will be made in your cell directory. This is the extraction file of the inverter you
draw as follows.
Open the extracted file. The file will be seen like this figure below. From this file, we are able to see all
electrical connections and all parameters like capacitance and transistor sizes in the layout. Just try to
click one node, then you will see all electrical connections of the node.
Now, you have electrically extracted data from your layout. What if you made any mistakes for
connection, cadence will show you error messages.
Figure below is one of the examples.
To correct these errors, you can also use find option in the same manner as DRC.
If you cannot find them using find option, there is the other way we can use.
Open the extracted file in the library manager window. And then click on a suspicious node. Here, I
click on vout node as error messages said. The extracted view highlights all connections from vout
node. Then we can see that vout is connected to gnd . To fix this, go to the layout editor, change the
layout.
schematic, the name is different with this. After checking the names, it turns out that the name in the
schematic is vout, not out. Thus, to fix this, go back to the layout, change the name, run DRC, run
extract, and do again LVS. If you pass LVS, you are done.