Create Custom Layout

To draw the layout of the circuit designed, open a new layout editor window.
Click on the File -> New -> Cell view in the Library Manager Window. A pop-up window will appear.

In the New File window, type in the Cell name and choose a View name as shown above. Note that
View name, layout, is a reserved word. And then click on OK.
The layout window will pop-up along with a LSW window. This LSW is a color palette with each
color corresponding to a different layer in the CMOS process.

In other words, the LSW window will be used to draw the masks in the layout editor window. To draw
a mask, say an nwell layer, first choose the corresponding layer in the LSW window by clicking on the
layer. Then, move your cursor into the layout window where you want to draw the nwell layer and
type r (rectangle) and move your mouse. A yellow box will appear indicating the boundary of the
nwell mask. Just click on the left mouse button to draw the nwell rectangle; we'll worry about the
actual dimension later. To change the dimension of the rectangle, move your cursor to the side where
you want to extend or shorten such that the side is highlighted and then type s (stretch). The side will
move with your cursor. You can use similar strategy to draw any layer (say metal1 or metal2 or poly

etc).
To simiplify the layout, the design kit comes with some built-in macros for standard constructs. For
example NMOS and PMOS are already built-in. So taking our example of an inverter layout, we can
instantiate one PMOS and one NMOS in our layout window. To do that, type i on your layout window,
click on Browse button, and choose NCSU_TechLib_ami06-> nmos4 -> layout in the Library Brower
as follows:

For PMOS, use same steps as well as NMOS case.

A figure below shows an example of NMOS and PMOS transistor layout. These cells will appear as a
black box. To see through the cell as shown in the figure, type "Shift -f".
If you want to change parameters of the transistor, use q command.
Select Parameter on taps.
As you can see above, you can change all parameters of the transistor in Edit Instance Properties. The
figure below is one of examples to increase the number of the transistors finger using Multiplier. This
is especially useful when you are trying to share drain and source regions for a compact realization of
a complex logic gate using eulers graph, or you you may use these fingers to make a wide
channel transistor more compact.
Once we layout the transistors, we need to make connections (aka routing). We will use metal1 layer to
connect the source and drain. And we will use the poly layer itself to make contact between the two
gate. Just pick metal1 from the LSW window and draw a rectangle from the drain/source region of one
transistor to the drain/source region of the other transistor to make the connection. Obviously you need
to make contacts (aka vias) between the metal1 and the underlying source/drain region.
The figure below shows the metal1 layer (blue line-shaded polygons) connected to the active region by
an active contact (a solid black square). Note that pmos and nmos come with built-in active contacts
and you dont need to make them yourselves. For connecting vdd and ground, you can place two
metal1 layers on top and bottom which are served as power rail and route the metal1 layer to respective
source/drain region of the transistor. For shorting the gates of the nmos and pmos, you could use the
same polysilicon gate (poly).
After you have connected the gate, source and drain regions, we need to think about where and how to
make the bulk connection. The bulk terminal for an NMOS is the p-type substrate shared by all, and the
bulk terminal for a PMOS is its nwell. For bulk connection for NMOS, you can instantiate a built-in
macro ptap and for the bulk connection of PMOS, you can instantiate a built-in macro ntap. To
do that, type i on your layout window, click on Browse button, and choose NCSU_TechLib_ami06>ntap or ptap->layout.
The power supply layer should be overlapped with ntap or ptap using metal1 so that the bulk of
transistors are connected.

The gate of the transistors needs to be connected to the metal1 lines for it to be accessed by other
gates. To do that you will be using a contact (another dark square) "cc.dg" to make a contact between
an overlapping metal1 and poly layer. This contact is also available as a built-in macro. Go to
'NCSU_TechLib_ami06 library' to select cell " m1_poly" (note capital letters), which means metal 1 to
poly,
Similarly, we desire to then connect the metal1 to metal2 (though it is not necessary) for pin
connections. For this purpose, we will make a contact between a metal1 and a metal2 using a "via". To
do that instantiate the cell "m2_m1" from the library. The figure below shows all such connections.
The red-shaded polygon with a black square at the center and blue borderline is the m1_poly contact.
The blue-shaded polygon with a pink square at the center and pink borderline is the m2_m1 contact.
For simulation purposes and standard cell design rules, it is necessary to add the pin (pn) layer. They
are identical in purpose to the vin/vout and vdd/gnd pins in the schematic view. Power and ground rail
pins should be declared as Inputoutput. Note that Input/output pins should be in metal2 while
power/ground rail pins should be in metal1. Click on metal2.dg in the LSW window. Then press
Ctrl-p in the layout editor window. A window will pop up. Enter the name 'vin' for labeling input.
Choose "Display pin name " option and define the pin as input.
Then click on the left mouse button with the cursor placed at the top left corner of the metal2 square to
be labeled. Then drag the mouse to the right bottom corner of the same metal2 square to be labeled.
Click one more time inside the metal2 square to place the text. Do the same steps for placing an "vout"
pin except for the fact that you declare the pin as "output". Note that the name and the type of the
pins must same as that of the schematic.
Here are some hotkeys that I have found to be very useful when designing layouts:
Move about the layout view screen keyboard arrows (up, down, left, right)
Fit entire layout onto screen f
Zoom in/out Ctrl/Shift z
Save design F2
Cancel previous command Esc
Reveal all mask layers within each layout cell Shift f (Use Ctrl f to hide these layers)
Properties q
Create path p (Convenient for making interconnections between I/O pins of layout cell; need to select
mask layer first from LSW window)
Create rectangle of mask layer r (Select .dg mask layer first from LSW)
Create pin Ctrl p (Select .pn mask layer first from LSW)
Instantiate layout cell i
Select more than one mask layer simultaneously Hold down Shift and click on each layer (Use Ctrl to
deselect a particular layer)
Undo - u
Copy c

Delete d
Move m
Stretch s (Point to edge of mask layer first using mouse cursor)
Ruler k (Erase ruler Shift k)