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Brief Contributions
NO. 6,
JUNE 1999
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VOL. 48,
INTRODUCTION
. The author is with the Signal Processing Center of Sanders, a LockheedMartin Company, Nashua, NH 03061. E-mail: pfiore@sanders.com.
Manuscript received 7 Mar. 1997; revised 29 Aug. 1997.
For information on obtaining reprints of this article, please send e-mail to:
tc@computer.org, and reference IEEECS Log Number 104114.
0018-9340/99/$10.00 1999 IEEE
JUNE 1999
641
Fig. 2. (a) Comparison-exchange circuit for one bit numbers. (b) Graphical
shorthand notation.
MULTIPLIER CONSTRUCTION
Fig. 3. Bitonic sorting network for N 16. The network is composed of 10 levels of parallel comparison-exchange circuits shown in Fig. 2.
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Fig. 4. Perfect shuffle bitonic sorting network for N 8. The network is composed of six level of parallel-exchange circuits shown in Fig. 2 and three levels of reordering.
TABLE 1
Asymptotic Multiplier Speeds
TABLE 2
Asymptotic Multiplier Sizes
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Fig. 5. Dadda 8 by 8 column reduction. Delay is two XOR delays per stage.
VARIATIONS
TABLE 3
Number of Gate Delays for Multiplication Methods (XOR 3 Gate
Delays)
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Fig. 6. Bitonic-detect 8 by 8 column reduction. Sorts of size 8, 4, and 3 are performed (6, 3, and 2 gate delays, respectively). Detection in each stage is two gate delays.
Fig. 7. Bit extraction circuit based on the half-cleaner. The half-cleaner converts
two bitonic sequences into one bitonic sequence and one clean sequence. The
OR gate detects which sequence is clean, extracts the single weighted bit, and
causes the 2-1 MUX to propagate the single remaining bitonic to the next stage.
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CONCLUSIONS
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REFERENCES
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[2]
[3]
[4]
[5]
[6]
[7]
[8]
ACKNOWLEDGMENTS
This work was supported by Sanders internal funding.
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