CMOS TIME RESPONSE

Nano107
Chapter 8

CMOS TIME RESPONSE

DC analysis tells us Vout if Vin is constant
Transient analysis tells us Vout(t) if Vin(t) changes
Requires solving differential equations
Input is usually considered to be a step or ramp
From 0 to VDD or vice versa

Vin(t)

Vout(t)
Cload
Idsn(t)

DELAY DEFINITIONS
tpdr: rising propagation delay
From input to rising output
crossing VDD/2
tpdf: falling propagation delay
From input to falling output
crossing VDD/2
tpd: average propagation delay
tpd = (tpdr + tpdf)/2
tr: rise time
From output crossing 0.2 VDD
to 0.8 VDD
tf: fall time
From output crossing 0.8 VDD
to 0.2 VDD

INVERTER DELAY CALCULATION

Solving differential equations by hand is too hard
SPICE simulator solves the equations numerically
Uses more accurate I-V models too!
But simulations take time to write, may hide insight
We will use simple equations that are inaccurate but provide
insight
2.0

1.5

1.0
(V)

Vin

tpdf = 66ps

tpdr = 83ps

Vout

0.5

0.0

0.0

200p

400p

600p
t(s)

800p

1n

Simple Case Example:

Resistive Pull-Up Inverter
Transient Response

INVERTER CAPACITANCES
Example: Resistive load inverter
Poly Load
VG

n
p

VDD

Output

Vss=Vs=0

CGS

n
CGB

Ci
CDS

Field
Oxide

List of Parasistic MOS Inverter Capacitances

CDS Cod
1. Drain Junction Capacitance of driver
2. Interconnect Capacitance Ci
Col
3. Capacitance Associated with load
4. Load Inverter Capacitance F=Fan Out
FCin
The inverter must therefore drive a capacitance CL Cod Col Ci FCin

INPUT CAPACITANCE
Poly Load

Output

Vss=Vs=0

V DD

VG

n
p

VDD

CGS

n
CGB

Ci
CDS

Field
Oxide

C in

The input capacitance Cin of the MOS inverter is the gate capacitance of the driver

Cin CGS CGB CGD WL

ox
tox

Capacitance at the output of a Resistive load MOS inverter

CL Cod Col Ci FCin

RISE AND FALL TIMES

Rise (toff or tr) and Fall Time (ton or tf)
Rise time (Turn-off Time ) is approximately the time
that the output voltage of the inverter
takes to increase from VOL to VOH

The Fall time (Turn-on -time ) is approximately the

time that the output voltage
takes to settle down from VOH to VOL
These transient times are governed by the capacitances and resistances in the circuit and
by the currents charging and discharging them to the desired voltage levels.
Dt = C(DV)/<I>
where < I > denotes average current

RISE TIME OF RESISTIVE PULL-UP INVERTER

I coff

MOSFET OFF

VDD

v DD

1 v
VDD 2R 0
2
out

VDD

v out
dv out
R

v DD
2R

Then,
tr

In general the rise time is given by

C L VDD
2RC L
VDD /2R

t r 2RC L

tr = 2.3 RC
tr is essentially governed by the pull-up conductance and by the load capacitance CL

FALL TIME OF A
RESISTIVE LOAD INVERTER
Fall Time
Fall time is affected by all 3 devices including the pull-down
The non linear behavior of the MOSFET requires piecewise linear
calculation of the solution by solving the relevant differential equation
with appropriate boundary conditions.
Instead Shockley model uses average current and plugs it into

Dt = C(DV)/<I>
2 2

Icon k VDD VT

tf

6CLVDD
kD

VT VDD

6VDD 2R

2 VT V V 2 3VDD
DD
T

VDD
B

CMOS Capacitances and delays

CMOS INVERTER INPUT AND OUTPUT CAPACITANCES

Vin
GND

CGSn

CGSp

Vout
n+

p+

n+
CGBn

CDSn

n
Cin.n CGSn CGBn CGDn Wn L

ox

Cin. p CGSp CGBp CGDp W p L

tox

ox

CDSp

VDD
p+

CGBp

But Wp~2Wn

Cin.CMOS Cin. p Cin.n 3Wn L

tox

ox
tox

CL 3CDS . NMOS Ci 3FCin. NMOS

Input and output capacitance of a CMOS inverter

n+

Fall time
VDD

Rise time
VDD

VinL=0

CMOS FALL TIME

In CMOS the turn-off time is totally governed by the load, whereas the turn-on time is totally
governed by the driver. Using Shockleys approach
V DD V TD

c(on)

V TD

k V
2
D

V TD
DD

dV O

V DD V TD

k D 2 V DD V TD V O dVo

dV

k V
V
D

DD

VDD

Dt = C(DV)/Icon
resulting in
2

on

3CV
k V V 2V
DD

DD

TD

DD

V TD

DD

V TD 2V DD V TD
3

CMOS RISE TIME

VDD VT L

k
2 V -V dV
2

DD

c(r)

TL

VDD

VDD VT L
VDD

k L V DD-V TL (V -V DD )
O

dV

k V -V 2V
3
V
2

DD

TL

DD

VDD

+ V TL

3CV
k V -V 2V
DD

VinL=0

DD

DD

TL

DD

-V TL

One obtains an identical equation form

for toff by replacing kD by kL and VTD by VTL

dV

IMPORTANT SIMPLIFICATIONS

Note that when VDD>>VT than

ton = toff= C/kVDD
If kL = kD (symmetric inverter) then ton = toff and the time response
of CMOS inverter will be symmetric as well
The inverter propagation delay is than
tp= (ton+toff)/2= C/kVDD

CMOS FANOUT and CMOS LOGIC GATE RESPONSE

CMOS FANOUT
limited by maximum propagation delay tpmax that is allowed

tpmax= Cmax/kVDD

Cmax= tpmax kVDD

If input capacitance of load inverter is Cin than

Fmax=Cmax/Cin = tpmax kVDD / Cin

CMOS LOGIC GATE DYNAMIC RESPONSE
2

3CV
nk V -V 2V

DD

DD

DD

TD

3CV
t
mk V -V 2V

DD

-V TD

DD

TL

DD

-V TL

Where nkD and mkL are the effective transconductance parameters

of the NMOS path and PMOS paths.
The capacitance C must include the effective Drain capacitances of NMOS and PMOS
transistors

CMOS POWER DISSIPATION

Ptotal = Pdynamic + Pstatic
Dynamic power: Pdynamic = Pswitching + Pshort circuit
Switching load capacitances
Short-circuit current

Static power: Pstatic = (Isub + Igate + Ijunct )VDD

Subthreshold leakage
Gate leakage
Junction leakage
[Contention current (two terminal pull-ups)]

POWER IN CIRCUIT ELEMENTS

PVDD t I DD t VDD

VR2 t
PR t
I R2 t R
R
Energy stored at a capacitor

dV
EC I t V t dt C V t dt
dt
0
0
VC

C V t dV 12 CVC2
0

Power removed from a capacitor when driven by frequency f

PC CVc 2 f

CHARGING A CAPACITOR
When the gate output rises
Energy stored in capacitor is
2
EC 12 CLVDD

But energy drawn from the supply is

EVDD I t VDD dt CL

dV
VDD dt
dt

VDD

dV C V
Half the energy from VDD is dissipated in the pMOS transistor as
heat, other half stored in capacitor
When the inverter output falls
Energy in capacitor is dumped to GND
Dissipated as heat in the nMOS transistor
CLVDD

2
L DD

Pswitching CVDD 2 f

SHORT CIRCUIT CURRENT

When transistors switch, both nMOS and
pMOS networks may be momentarily ON at
once
Leads to a blip of short circuit current.
< 10% of dynamic power if rise/fall times are
comparable for input and output
Edp=VDD (Ipeak.ton)/2+ VDD (Ipeak.toff)/2=>

Pdp= VDD Ipeak f tp

CMOS POWER DISSIPATION

STATIC POWER :
Due to Leakage:

Ps VDD.ILeakage

DYNAMIC POWER DISSIPATION:

Due to load capacitance
Each half cycle the energy stored on the C is with f = frequency
2
Pc CVDD
f

Due to Direct path transition currents

Pdp= VDD Ipeak f tp

SWITCHING POWER & ACTIVITY FACTOR

Suppose the system clock frequency = f

Let fsw = af, where a = activity factor
If the signal is a clock, a = 1
If the signal switches once per cycle, a =
Dynamic power:

PCMOS a (CVDD 2 VDD I peak t p ) f VDD I leak

VDD
iDD(t)

fsw