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KO, JEROME B.
12, 2015
3-ISA
BARIBAR
April
ENGR. AARON NATHANIEL
b. command decoding - I/O module accepts commands sent from the processor.
c. status reporting The device must be able to report its status to the processor,
2.
3.
4.
5.
d. Address recognition Each I/O device has a unique address and the I/O module
must recognize this address.
Device communication The I/O module must be able to perform device
communication such as status reporting.
Control & timing The I/O module must be able to co-ordinate the flow of data
between the internal resources (such as processor, memory) and external devices.
Data buffering This is necessary as there is a speed mismatch between speed of
data transfer between processor and memory and external devices. Data coming from
the main memory are sent to an I/O module in a rapid burst. The data is buffered in
the I/O module and then sent to the peripheral device at its rate.
Error detection The I/O module must also be able to detect errors and report them
to the processor.
CPU from one program to the other which is causing the interrupt.
When the processor receives the interrupt signal, it knows that the data is ready; it
suspends its current job and transfers data from buffer to its own registers.
a. When a read instruction is encountered, the processor sends the device address
via the Device Address Bus (DAB). This is decoded by the I/O controller and
the DMA interface of the appropriate device is selected. The processor also
sends the address (in RAM) where the data is to be stored. The READ
command is issued.
b. The processor continues with the next instruction in the program. It has no
further role to play in data transfer.
c. The DMA status register is set to 1 to indicate the BUSY status. Data is read
from the device and stored in the DMAs data register (buffer).
d. When data has been entered in the data register, the data ready flip-flop is set
to 1 and an interrupt is sent to the processor.
e. The processor completes the current instruction. It then gives control of MAB
and DB to the DMA interface. The DMA transfers data from its data registers
to the memory address specified.
7. Elaborate the role of the processor in interrupt-driven I/O.
a. The device issues an interrupt signal to the processor.
b. The processor finishes execution of the current instruction. It then responds to the
interrupt signal.
c. The processor sends an acknowledgement signal to the device that sent the interrupt.
address of the next instruction to be executed, etc). These are saved onto a stack.
e. The processor then attends to the device that issued to the interrupt signal.
f. When interrupt processing is over the saved registers are retrieved from the stack and
the processor continues its previous task from the point where it was last stopped.
8. What is cycle stealing? Which I/O technique uses this method?
The process of taking control of memory cycle to transfer data is known as cycle
stealing. The DMA transfers one data word at a time after which it must return
control of the buses to the CPU. The CPU delays its operations for 1 cycle to allow
the DMA to steal one memory cycle.
processor. The processor must continuously check an I/O device and hence it cannot
do another task. This method is hence inefficient (slow).
b. Interrupt-driven I/O
- The basic drawback of programmed I/O is that the speed of I/O devices is much
slower in comparison to that of CPU, and because the CPU has to repeatedly check
whether a device is free; or wait till the completion of I/O, therefore, the performance
of CPU in programmed I/O goes down tremendously. What is the solution? What
about CPU going back to do other useful work without waiting for the I/O device to
complete or get freed up. On completion of I/O, the I/O device interrupts the CPU to
tell it has finished the work.
c. Direct memory access
This method eliminates the need for the continuous involvement of the processor in
the I/O operations.
REFERENCE:
http://www.slideshare.net/mukeshnt/io-modules-24946158