VLSI design assignment (Submit before April 15, 2015)

1. Design a resistive-load inverter with R = 1 kQ, such that VOL = 0.6 V. The nhancementtype nMOS driver transistor has the following parameters:
VDD = 5 .0 V,
Vtn =1V, nCox = 22.0/V2
(a) Determine the required aspect ratio, W/L.
(b) Determine VIL and VIH.
(c) Determine noise margins NML and NMH.
2. Consider a CMOS inverter circuit with the following parameters: VDD =3 .3 V, V tn=
0.6 V, Vtn= -0.7 V, kn = 200 A/V2 , kp = 80 A/V2. Calculate the noise margins of the
circuit.
3. Design of a CMOS inverter circuit:
Use the same device parameters as Vtn = 0.6 V , Vt p = - 0.7 V, nCox = 60 uA/V 2 , pCox = 25A/V2
(WIL)n = 8 (W/L)p = 12. The power supply voltage is VDD =3.3 V. The channel length of both
transistors is Ln = Lp = 0.8m.
(a) Determine the (Wn/Wp) ratio so that the switching (inversion) threshold voltage of the circuit
is Vth = 1.4 V.
(b) The CMOS fabrication process used to manufacture this inverter allows a variation of the Vtn
value by 15% around its nominal value, and a variation of the Vtp value by 20% around its
nominal value. Assuming that all other parameters (such as n, p, Cox, Wn, Wp) always retain
their nominal values, find the upper and lower limits of the switching threshold voltage (Vth) of
this circuit.
4. With neat sketch explain the generalized fabrication sequence of n-well CMOS integrated
circuits.
5. Consider a CMOS inverter, with the following device parameters: VT0,n = 0.8 V,
VTP=- 1.0V, nCox. = 50 A/V2, pCox = 20 A/V2
The power supply voltage is VDD = 5 V. Both transistors have a channel length of Ln = Lp= 1m.
The total output load capacitance of this circuit is CL,= 2 pF, which is independent of transistor
dimensions.
(a) Determine the channel width of the nMOS and the pMOS transistors such that the switching
threshold voltage is equal to 2.2 V and the output rise time is rise =5 ns.
(b) Calculate the average propagation delay time p for the circuit designed in (a).
(c) How do the switching threshold Vth and the delay times change if the power supply voltage
is dropped from 5 V to 3.3 V. Provide an interpretation of the results.
+B
+ D
using complementary
) (C
+ ) + F)G
6. Implement the equation = ((A
MOS. Size the devices so that the output resistance is the same as that of an inverter with
an NMOS W/L = 2 and PMOS W/L = 6. Which input pattern(s) would give the worst and
best equivalent pull-up or pull-down resistance?
7. The simplified layout of the CMOS logic is given below. Draw the circuit stick diagram
and circuit diagram.

8. Draw the CMOS logic circuit and stick diagram for

i)
One bit half adder
ii)
One bit full adder
9. Design a 4 bit adder using CMOS logic using following method
i)
Ripple carry adder
ii)
Carry look-ahead adder
iii)
Carry select adder
iv)
Carry save adder
10.