Getting to

the Heart
of the
Matter
image licensed by ingram publishing

Anthony Parker

he field-effect transistor (FET) has just three

terminals. One is a gate that controls current flowing between the source and drain
terminals. It is simple enough, and so widely accepted as a workhorse in microwave
applications, that it must be fairly well understoodor
is it? Hidden between those terminals is a treasure trove
of complicated interactions that have taken years to sort
out. Just when we think we know all we need to know,
someone asks for double the power, to move up to the
next band, or even to do it all again in a new semiconductor material, and so the story continues.
Not surprisingly, FETs have not followed the basic
circuit design textbooks. Any attempt to measure
textbook characteristics is plagued by a dependence
on how they are measured and a seeming lack of

repeatability. Part of the problem is that we tend to

expedite the characterization by using limited frequency and time frames, and by choosing specific
bias conditions. This narrows our perspective such
that the results exhibit memory and anomalous traits.
Choosing which measurement to trust then becomes
a dilemma.
Another part of the story has been the challenge of
looking at the internal active part of the FET. It should
not surprise anyone dealing with microwave frequencies that the surrounding metal and connections are
significant and can mask the behavior of the active
region. There are other motivations for dealing with
this, driven by the desire to scale models to different
sizes or to push to higher frequencies where distributed effects arise [1].

Anthony Parker (tonyp@ieee.org) is with the Department of Engineering, Macquarie University, Sydney, Australia.
Digital Object Identifier 10.1109/MMM.2014.2385306
Date of publication: 6 March 2015

76

1527-3342/152015IEEE

April 2015

For the most part, it comes down to understanding the

dynamic processes behind the FETs eccentricities, which
this article will explore. Only the active part of the device
is considered here in the context of producing a compact
model. This is well described by nonlinear currents and
charge storage, with heating and trapping states. First,
lets explore how to get to the active heart of the device.

Active FET

Gat

in

Dra

Only the Active Part, Please

If we put heating and trapping effects aside for the
moment, an FETs active, or intrinsic, region is well
behaved across the frequency band. A good nonlinear
large-signal characteristic can be derived by integrating the small-signal data. This is a common approach
because making two-port network measurements is
relatively straightforward. A broad range of frequencies, dc to daylight, can be covered and repeated over a
fine grid of bias points over which to integrate.
The intrinsic part of the FET is embedded in a network
of access elements that includes package wiring, bond
wires, and on-chip metallization. These present significant impedances at high frequencies, vary with device
geometry, and introduce losses. Therefore, the first step
in the modeling process is to determine and characterize a model for the access network, as shown in Figure 1,
that can be subtracted from measured data to de-embed
the intrinsic FET. The process is simpler if unpackaged
bare chips are available to be probed directly. Otherwise,
the package also needs to be characterized.
One strategy for deriving the access elements is to
compare the port parameters when the active region is
biased off with the port parameters when it is biased
fully on. In practice, a Schottky-junction FET is either
turned off to look like a small capacitance or fully turned
on to look like a diode junction. Simplifying assumptions, including lateral symmetry, can be made when the
measurement is at zero drainsource potential (known
as the cold FET condition) [2][4].
Inevitably, there are more unknowns than measured
relationships, so terms such as an intrinsic channel
resistance must be set a priori [5], [6]. Incorrect assumptions produce inconsistent results across frequency and
bias, and oversimplification often leads to nonphysical
results. Optimization may help [7], or additional information from a known frequency dependence can be
exploited to pin down all the unknowns [8].
De-embedded port parameters can be completely
mapped to a two-port network of at least eight elements
corresponding to four real and four imaginary parameters. Two such mappings are shown in Figure2. In both
cases, two of the real terms, which correspond to the
intrinsic FETs transconductance and drain conductance,
are significant, while the other two, which arise from
leakage through the gate junction, are usually considered
to be negligibly small. The imaginary terms correspond
to capacitances and may include, as shown in Figure 2(a),
a combination of time delay and series resistance that can

April 2015

Figure 1. The intrinsic active region of an FET sits

behind a network of metal wiring, which is significant at
microwave frequencies. This needs to be subtracted from
the measured characteristics using a de-embedding process
to give intrinsic network parameters.

Re

ygg

ygd

ydg

ydd

ric2gs~2

ggd

gm

gds

ggd

+
vi
-

cgs
s
ygg

ygd

ydg

ydd

cgd

ri

Im

gmvie-j~x

= ~

cds

gds

cgs + cgd

-cgd

-cdg-gm(ricgs+x)

cdg+cds

(a)

Re

ygg

ygd

ydg

ydd

ggs

ggd

gm

gds

ggd
g

d
ggs

Cgs

Im

gm

Xgd
ygg

ygd

ydg

ydd

= ~

gds

Xdg

Cgs + Xgd

-Xgd

-Xdg

Xdg+Cds

Cds
s

(b)

Figure 2. The intrinsic two-port admittance parameters

give eight values that can be mapped to the conductance
and capacitance elements of an equivalent lumped-element
model. The correspondence depends on the topology and
vice versa. Shown are two possible mappings, which imply
a specific lumped-element topology. The imaginary terms
in (a) use a combination of time delay and series resistance
for the mapping, whereas the transdependent capacitances
in (b) provide a more direct mapping to each element.
be mapped to the port parameters [2]. The equivalent circuit in Figure2(b) uses a more direct mapping to transdependent capacitances.

77

For the most part, it comes down to

understanding the dynamic processes
behind the FETs eccentricities.
For a large-signal model, all of the intrinsic parameters
become functions of terminal potentials, so they need
to be viewed as surfaces above the gatedrain potential
plane, as shown in Figure 3. Line integrals over these
parameter surfaces give the charge and current functions
that are the basis for a large-signal FET model [9].

nce

cita

te

Ga

pa
Ca
Cgs

Xgd

Except in regions of significant heating and trapping,

which will be discussed later, it is possible to choose and
refine the access network model and de-embedding process to leave intrinsic active FET parameters that are the
same at all frequencies [8], [10]. This is the remarkable feature of the data in Figure 3, which includes surfaces over
a wide range of frequency measurements that sit on each
other. If this were not the case, then they would be considered to exhibit frequency dispersion, and additional
elements would be required, such as a resistance in series
with one of the capacitances or a time delay in the transconductance, as shown in Figure 2(a). These additional
elements do not affect a linear model, which only needs
to reproduce the small-signal port parameters. However,
as we will explore in the Charge It section, they do not
readily translate to a dispersion-free, conservative, and
large-signal description. An application of Ockhams
razor favors, particularly for large-signal charge modeling, a set of intrinsic FET parameters that are free of frequency dispersion.

Charge It
ce
our
S tial
e
t
Ga oten
P

Dr

ain
Po So
ten ur
tia ce
l

ig = Cgs

dvGS
dt

+ Xdg

dvGD
dt

Gate

Drain

Cgs

Xgd

Xdg

id = Xdg

dvDG

nce

cita

in

Dra

pa
Ca

dt

Cds
+ Cds

dvDS
dt

Cds

Xdg

Dr

ain
Po So
ten ur
tia ce
l

ce
our
S tial
e
t
Ga oten
P

Figure 3. The intrinsic admittance parameters (real and

imaginary pairs) correspond to four conductance elements
and four reactance elements. The latter are equivalent to
capacitances such as those shown here. The value of each
element forms a surface above the terminal potential plane
that can be integrated to give the charge at their common
terminal. Note that the graphs in this figure include, at each
point, data measured between 1 and 20 GHz, so, except for
high values, there is remarkably little frequency dispersion.

78

In Figure 3, the imaginary port parameters of the

intrinsic FET correspond to autodependent and transdependent capacitances. Autodependency implies that
the current depends on the temporal rate of change of
its own terminal potentials, whereas transdependency
gives a current proportional to the change of potentials at other terminals. Unless the off-diagonal port
parameters are equal, there will need to be at least one
transdependent capacitance.
The terminal current, say at the gate, is a function
of two-port parameters, and, hence, two capacitance
branches. Each carries a reactive current proportional
to the temporal rate of change of the relative potentials
of the other terminals: the gatedrain and gatesource
potential differences. The constant of proportionality,
the capacitance value, is a nonlinear function of the
gatedrain and gatesource bias potentials. There is
a significant, albeit subtle, difference between capacitance nonlinearity relative to bias, which comes from
small-signal measurements, and nonlinearity relative to
instantaneous potential, which is required for a largesignal model.
Turning constant values at specific biases into largesignal functions of instantaneous terminal potential
will introduce interaction between the parameters. For
example, the differential dependence of transconductance on the drain potential introduces an additional
drain conductance contribution that is proportional
to the product of both the gate and drain potentials.
Such interactions in the reactive currents also need to
remain faithful to the behavior of the real device.
Implementing a large-signal model with nonlinear capacitance functions will generate interactions
that can produce a nonphysical dc currentsee Lets
Be Conservative. This is not only erroneous but also

April 2015

introduces convergence problems for the simulator.

However, the problem does not occur if the capacitances form a conservative vector field.
A charge-based modeling approach gives conservation at a terminal by describing the charge at that
terminal with a well-behaved, continuous function of
the terminal potentials. Because the equivalent capacitances are the two partial differentials of such a function, they will form a conservative vector field [11], [12].
In a charge-based model, the current is the temporal
rate of change of the charge. Although the measured
data are capacitance, a handy property of conservative
vector fields is that its integral is path independent, so
it is easy to determine and fit the charge function by
integrating the capacitance data that form a conservative vector field. In general, gate terminal data are conservative within the accuracy of the measurement [9].
If the data do not form a conservative vector field, then
alternative approximations will need to be employed.

De-embedded port parameters can

be completely mapped to a two-port
network of at least eight elements
corresponding to four real and four
imaginary parameters.
The process needs to be repeated for the drain terminal to produce a drain charge. In principle, a source
charge could be also be extracted but is implied by
Kirchhoffs current law, which is a statement of conservation of total charge for the FET. While a chargebased model produces a conservative capacitance field
at a specific terminal, it is the combination of terminal
charges that should conserve the total charge.
If heating and trapping are not affecting the data,
the conductance parameters also form a conservative

Lets Be Conservative
Consider a reactive current, i, driven into one terminal
(e.g., the gate) of a three-terminal device (an FET).
The three-terminal model might be that shown in
Figure S1, with capacitance values C 1 and C 2, fitted
to small-signal measurements. The reactive current
into the common terminal will be

Energy from Nothing!

This turns out to be nonphysical because modulating
the capacitance can generate dc currents. To see how,
let v 1 = V1 sin ~t and v 2 = V2 sin ~t + z, then a little bit
of trig manipulation will show that the dc term in i is
1 c 2C 1 - 2C 2 m ~V V sin z.
1 2
2 2v 2
2v 1
Having this gives ever-increasing stored energy over time.
Reality Check
Clearly, if the mixed differentials are equal, then the
dc term will disappear and all will be well. In the
parlance of vector calculus, the capacitance data need
to form a conservative vector field with respect to the
potentials [11], [12]. For this to be the case, there must
by definition exist a function Q (v 1, v 2) let us call it
charge at the common terminalsuch that

April 2015

C2

V1

C1

i . ;C 1 + v 1 2C 1 + v 2 2C 1 E dv 1
2v 1
2v 2 dt
+ ;C 2 + v 1 2C 2 + v 2 2C 2 E dv 2 ,
2v 1
2v 2 dt
where the partial differentials account for the
capacitance variation with bias and signal potentialthat
is, the gradient of their surfaces above the (v 1, v 2) plane.

V2

Figure S1. A three-terminal model that includes

capacitance branches from a common terminal to
another two with values C 1 and C 2 .

C1 =

2Q
2Q
and C 2 =
.
2v 1
2v 2

If the data conform to this, then we can say it is

conservative at the common terminal.
Note that this is not a statement of charge
conservation, which must consider the whole device.
Rather, it is a requirement that the capacitance
vector field is conservative with terminal charge as
its scalar potential.
Lets Charge It
The best way to guarantee conservation at the common
terminal in a model is to use and fit a single terminal
charge function, Q (v 1, v 2) . That is, formulate the model
to be charge based.

79

Dispersion is just an interaction

with the frequency response of
state variables.
vector field. However, a frequency-dispersive element,
such as a time delay, will introduce a nonconservative
and, hence, nonphysical reactive component. Fortunately, it is possible to extract parameters for a smallsignal model with frequency-independent capacitance
and conductance terms, such as those in Figure 2(b),
Figure 3, [8], and [10]. One must, as we will explore
below, allow for the fact that there will be regions of
significant frequency dependence, which result from
heating and trapping effects, and then select data
from the other bias regions, as shown in Figure 3, from
which to extract and verify a dispersion-free smallsignal model.
What about energy? The terminal charges, which
are functions of terminal potentials, also form a
gradient vector field of an energy function [13], [14].
This should also be conservative but will not be if
the off-diagonal port parameters are not equal. The
implication is that energy-conserving intrinsic models must be reducible to no more than three reactive
elements. How to map measured data, which have
unequal off-diagonal terms, to such a model still
remains an open question.

Quick Step

Drain Current

Thus far, the topic of heating and trapping has conveniently been avoided. For that matter, so have the
drain-current characteristic and frequency dispersion

1s

30 V

10 ms 100 ns
10 ns
Time

ia
20 V
ent
Pot
e
rc
10 V
Sou
in
a
r
D

Figure 4. The steady-state drain-current characteristics,

at which admittance parameters are measured take time
to acquire, so various trapping and heating processes
will have changed the state. The characteristics measured
quickly (10 s in this diagram) after a change in terminal
potential are those for the initial state. The diagram shows
how certain points vary over time as the trapping and
heating states respond to the new terminal potentials to
give steady-state characteristics after 1 s. The scales are
typical for a wide-bandgap technology.

80

of reactive currents because they depend on trapping,

heating time, orin a phrasethe state of the FET.
The state is defined by state variables, which are simply values of temperature or trap potentials that must
be computed somewhere.
The small-signal parameters are measured at
steady-state bias conditions. The usual assumption is
that the currents have had time to settle to quiescent
conditions after the bias potentials are set. Another
way of interpreting this is that it is the state variables that need time to settle. The current and charge
responded instantaneously to these state variables and
terminal potentials. Thus, each point in a set of steadystate characteristics is that for the terminal potentials
and the corresponding settled values of the state variableseach point will be for a different state (e.g., a
different temperature). The implication is that the current and charge models are an instantaneous function of terminal potentials and state variables and that
dispersive and delayed responses arise from ancillary
state variable functions.
Slow-state variables do not respond to rapid changes,
so the FET will remain in a constant state while being
driven by a large signal at a microwave frequency.
Consequently, reliance on small-signal, steady-state
characteristics to predict the response at each point in
a large-signal excursion is problematic because there
will be a different state at each point. Instead, largesignal data for the constant state are required.
We need to perform a quick step to measure the
characteristics without disturbing the state of the FET.
This is the principle behind isodynamic pulse measurements, which give the drain-current characteristics for isothermal and constant trapping states [15].
The technique is widely adopted, and advanced systems also pulse radio sources to perform isodynamic
network parameter measurements, particularly of
high-power devices intended for pulsed-radar applications. Pulse techniques also facilitate nondestructive
investigation of transistor breakdown regions [16].
Commercial systems are available that are capable
of submicrosecond pulses. Examples are Accent Optos
Dynamic I(V) Analyzer [17], Auriga Measurement
Systems pulsed system, Focus Microwaves modular pulse system, and systems by Keysight Technologies, Keithly Instruments, and Amcad Engineering. A
degree of sophistication can be achieved with arbitrary
pulse patterns and arbitrary control of initial bias and
pulse timing [18], [19].
Isodynamic and steady-state characteristics are
shown in Figure 4. The characteristics in the short
10- ns time frame are those for a high-voltage bias state.
The data are built up by stepping to each point in the
curves and returning quickly to the bias state so as
not to disturb it. On the other hand, each point in the
steady-state characteristic at the 1-s time frame is that
at its own temperature and trap state.

April 2015

Caught in a Trap
Gate lag and drain lag are the classic manifestations
of charge trapping. In simple terms, electrons in a
conduction band contribute to current flow, whereas
electrons in a valence band do not. There are other
energy levels between these bands into which electrons can fall [20]. It takes time to capture and release
charge from these levels, so the charge is temporarily trapped. The problem is not that some charge is
trapped, as only a small fraction is, but rather that it
has a potential and FETs are sensitive to fields from
potential sources [21]. The FET is further turned off by
any negative trapped charge, and it is not until after
the lag time for the trap to release the charge that its
potential changes to allow the FET to fully turn on.
Although the effects of the trapping processes are
generally substantially slower than the operating
frequencies, their response rates may be comparable
with the modulation frequency. Thus, within the time
frame of the signal transitions, the traps state can act
like a memory of past conditions [22][24]. If we extend
the observation time frame to encompass the trapping
rate, then the memory effect is seen to be just a longterm transient response.
Large-signal FET models need to know what additional controlling potential is contributed by a trap, how
it varies with operating conditions, and how quickly it

April 2015

responds to change. A trap element can be elegantly

implemented in a circuit simulator by drawing a
lumped element analogy based on charge storage in a
capacitor (see A Better Mouse Trap) [25][27]. The trap
element is driven by a function of the FETs terminal
potentials, and its output is a trap potential that can be
summed with the gate potential. The FETs current and
charge functions then depend on the gate potential plus
the state remembered by the trap element.
To model three important physical characteristics
of trapping, the trap elements response:
has a single pole (so is of first order)
has a time constant that is set by the value of its
input and is independent of the traps state
becomes faster with increasing temperature.
These characteristics mirror, one for one, the three features of gate and drain lag in Figure 4 noted earlier.
Various combinations of terminal potential dependency and trap polarity are possible, which correspond
with the type and position of traps in the physical
structure of the FET. The rate at which the traps at
the surface of an FET will respond becomes faster at a
higher drain potential, whereas the rate at which traps
in the substrate respond can become slower at higher
drain potentials [28]. This is because the electric fields
at the surface increase with the drain potential, while
those in the substrate become less influenced by the
gate potential. The magnitude and polarity of the trap
potential and sign of the terminal potential dependency are the important considerations. The trap element is just one piece of the puzzle; there are others
that need to be considered before we can assemble the
FET model.

100
10 ms

10

ns

1n

ns

Drain Current

The transient responses from the isodynamic

to steady state are also shown in the diagram. The
delayed additional rise in the drain current soon after
the FET is turned on is known as gate lag if the gate
potential is stepped or drain lag if the drain potential is stepped (one can get lost in the semantics when,
as is the common scenario, both potentials are simultaneously stepped). These lags pop out very clearly
on the logarithmic timescale. Interesting features are
as follows.
The lag has a single-pole (first-order) response, so
it should be easy to model.
The response speeds up as the drain potential
increases.
It is faster at higher initial power conditions,
which suggests a temperature dependence.
The pulse and transient approach is a simple idea,
but there is a practical limit to how short the pulses
can be. A wide-bandgap technology produced the
elegant illustration shown in Figure 4. At drain potentials lower than those shown, the lag can be tens of
minutes. At higher drain potentials, the lag reduces to
nanoseconds, which is faster than practical pulse measurements. The scales reduce by more than an order of
magnitude for gallium arsenide devices, both in potential and time, such that the faster pulse measurements
are no longer isodynamic. This emphasizes the need to
draw upon radio-frequency (RF) techniques to probe
faster response characteristics.

0V

8V
DrainSource Potential

Figure 5. The pulse characteristics taken at various times

after turning on an FET show points along the journey to
a new state. In this example, there is evidence of one trap
that gives gate lag at a low drain potential as well as a kink
caused by a second trap. For a specific time after turn-on, the
low potential side of the kink is yet to see the state of that trap
change. The kink occurs at the potential where the rate of
change of that traps state matches the measurement time.

81

A Better Mouse Trap

Shockley, Read, and Halls analysis of trapping in terms
of capture and emission processes can be somewhat
overwhelming [25]; however, their ideas can be
portrayed in a readily understood circuit analogy that is
easy to implement in a circuit simulator [26], [27].

RC
Warmer

RC =

1 + eEI/kT
AT2e-EA/kT

Cooler

What Is the Trap Potential?

The traps potential, VT , in the analogy, is the
potential across a capacitor used to trap charge. It
follows the S-shaped sigmoid function of energy
ranging from zero at neutral charge to a maximum of
VO when the trap is fully ionized (see Figure S2).
How Does It Vary with Operating Condition?
The traps state depends on the position of the Fermi
level, E i, relative to its energy level in the bandgap.
This is influenced by the FETs terminal potentials. In
most cases, a simple linear combination of terminal
potentials provides an adequate model.
How Quickly Does It Respond to Change?
The rate of change of trap potential varies inversely
with the target steady-state potentialthat is,
exponentially with E I .
In an ionized state, the response rate is that of
emission, which, like many physical processes, is an
Arrhenius function of temperature T. The activation
energy E A is set by the position of the traps energy
level in the bandgap.

Kink from Impact

Related to trapping is the infamous kink effect shown in
Figure 5. It is a boost in current stemming from a positive
potential at a surface trap [22]. When this happens, and
how quickly, depends on the drainsource potential.
A positive charge comes from holes generated when
there is impact ionization in the channel [29]. It is easy
to measure the resulting hole current with a sensitive
current meter at the gate. This current also affects trap
sites near the source, and their increasing potential aids
the gate potential to further turn on the FET. The electric
field in the channel needs to be sufficiently high to cause
the ionization, so the effect comes on suddenly at a critical drainsource potential.
At high drain potentials, the trap responds quickly
(there are lots of holes arriving at the site) and by the
time the pulse measurement sample is made, the FET
is already further turned on. At lower drain potentials,
the trap is yet to respond by the time of the sample, so
the drain current is not boosted. The kink is formed in
the potential region between these conditions. Taking
measurement samples at a shorter time after the initial
turn-on will see the kink move to a higher potential

82

Emission

Capture

EI
R

VT

VT(t)

VT
Cooler
Warmer

Ionized

Neutral

EI

VT =

VO
1 + eEI/kT

Figure S2. A trap model can be implemented with a

capacitor and single dependent current sourcea couple
of lines of Verilog-A code. Need a hole trap instead?
Just change the sign of VO . Everything else is sorted
out. This model elegantly accounts for the variation
of the response rates from nanoseconds to minutes,
depending on the bias and temperature conditions.
The less ionized the trap is, the more quickly
it can capture the available charge. As it happens,
the mechanisms that increase E I also increase the
availability of charge to be captured.

where the response time of the trap is comparable to

the time of the sample.
It is important to remember that the trap potential is
a state variable that responds slowly, so the kink is only
an artifact of a change, or otherwise, of a state at the time
of the pulse measurement. A much faster signal will see
a constant state and so it will not be aware of the kink.
Notwithstanding this, it should also be noted that the
response time of the trap varies considerably with the
terminal potential and temperaturefrom seconds at a
low potential to nanoseconds or faster at several volts.
Thus, there will be operating conditions where the traps
will respond to the signal frequency [30].

Raise the Temperature

The temperature has such a significant impact on the
nature of all aspects of transistor operation that it should
really be considered on par with any terminal potential.
Increasing the temperature reduces the drain current,
slows the rate of impact ionization, and increases the
speed of the trapping response. These all interact during the transition from an isodynamic current at the
beginning of a transient to the final steady-state value.

April 2015

A consideration of temperature needs to go beyond

the traditional scaling of the drain current by a thermal coefficient or the heuristic accounting for power
dissipation. An accurate model needs to have a junction-temperature terminal at which the thermal state
of the FET is represented. A thermal network of heat
capacities and thermal resistance is an important companion to the temperature terminal. In a circuit simulator, an electric analogy can be drawn that parallels
temperature with potential, rate of heat flow with current, thermal resistance with electrical resistance, and
heat capacity with, not surprisingly, electrical capacitance. To determine the temperature state, the FET
model injects its instantaneous power dissipation (as a
current) into a node of the thermal network and reads
back the temperature (a potential) at that node [15].
This implements self-heating of the FET by its own
power dissipation, which is an inescapable aspect of
its operation.
The thermal network will have a frequency response
that is of fractional order [31]. Unlike a single-pole
(or first-order) response that changes over about one
decade of time or a second-order response that changes
over half a decade of time, the thermal response has
an order of less than one, so it changes over several
decades of time. This is the distinctive feature that
stands out in a transient response seen on a logarithmic
timescale. Any first-order transitions will be trap state
related rather than heating. Higher-order transitions
can also exist when there is an interaction between a
trap response and temperature.

Putting It Together
We have covered the basic building blocks required to
put together a reasonable large-signal compact model.
Terminal charge and drain current are functions of gatesource and drainsource potentials,
temperature, and trap potentials. The latter are
summed with the gatesource potential in the
expressions.
Trap elements that are functions of the terminal
potentials and temperature are required for gate
and drain lag effects.
A trap element that is a function of temperature
and impact-ionization current is required for
describing the kink effect.
A thermal impedance element is required to give
temperature versus power dissipation. This could
be a single impedance that connects to an ambient temperature node or a network that interconnects various FETs in the circuit.
The interaction of these is shown in Figure 6, which
also shows the relationship between small-signal measurements used to fit or design the charge and current
functions and other transient and temperature measurements used to fit or design the trapping and thermal impedance elements.

April 2015

It is possible to choose and refine

the access network model and
de-embedding process to leave
intrinsic active FET parameters that
are the same at all frequencies.
Implied in the model assembly, but not shown in
Figure 6, is an additional current source that is proportional to the impact-ionization current. This is
easy to implement as implicit functions of the drain
current and terminal potentials. Another piece of the
puzzle that should be considered is gate-junction conduction and breakdown, which not only sets power

Small-Signal Parameters

Xgd

Cgs
C

gm

gds

Xdg

Cds

Qd(vgs,vds)
Id(vgs,vds)
Qg(vgs,vds)
Large-Signal Relationships
g

Qg(vgs+vT, vds, T )

Id(vgs+vT, vds, T )

s
Qd(vgs+vT, vds, T)
State-Dependent Large-Signal Model
R(vgs, vds, T)
P(Id,vds)
vT(vgs, vds, T )
+
T(t)
vT(t)
C
Zth
-

Zth

State Variable Relationships

vT(vgs, vds)
R(vgs, vds)

Pulsed-IV, Temperature Variation,

Intermodulation Measurements
Dispersion and Memory Data

Figure 6. A state-dependent large-signal model requires

current and charge functions that can be determined by the
integration of small-signal parameters and state variable
relationships that can be determined from transient and
nonlinear measurements. Here, a single trapping state and
a temperature node are shown. The large-signal model is an
instantaneous function of these and the terminal potentials.

83

If we extend the observation time

frame to encompass the trapping rate,
then the memory effect is seen to be
just a long-term transient response.

with order P and a subthreshold exponential mode, a

smooth continuous transition over a region of a v V is
achieved by nesting logarithm, exponential, and polynomial expressions functions as

limits [32] but can also contribute to an additional

trapping state.
Not to be overlooked is the challenge of fitting the
model parameters. Small-signal data are measured over
a range of bias points that each have corresponding
temperature and trap states. Thus, it is necessary to
determine the state variables at each bias point to know
how to shift and scale the integrated data before fitting the charge and current models. The state variables
add extra degrees of freedom to the extraction process
such that several measurement vectors are required
[33]. Pulse techniques should be accompanied by intermodulation and RF measurements and should be interpreted with the hindsight of the trapping and heating
mechanisms.
Sound implementation of the model description
is important for accuracy and simulator convergence.
The equations used need to be continuously differentiable and implemented with appropriate smoothing functions rather than conditional statements [34].
High-order derivatives, which affect the simulation of
nonlinearities, also need to be correct and continuous.
For example, rather than using a case statement to conditionally switch between a power-law of potential v

which gives a far more realistic high-order differential

behavior [35].

16

GH

8
G
4

rds

2 GHz

Hz

2G
Cds

0V

4V
DrainSource Potential Xdg

Hz
4G z
H
8G
16
G
8 G Hz
H
4G z
Hz

2
H
G
z

Figure 7. Although intrinsic network parameters may be

independent of frequency, there is still dispersion whenever
there is interaction with traps and temperature. Here,
impact-ionization-related trapping adds a feedback effect
that alters the drain reactive and conductive currents,
which manifests a frequency dispersion of the related
network parameters. There is evidence of gate-lag trapping
at lower drain potentials as well.

84

6v ln ^1 + e v/v h@P, 

Wider Landscape
The fundamental starting point for the modeling process discussed here is a set of intrinsic FET parameters
that are free of frequency dispersion. For the most part,
it is possible to refine or optimize the de-embedding
process to achieve this [10]. That is, extract a smallsignal model with frequency-independent capacitance
and conductance terms, such as those in Figures 2(b)
and 3. As mentioned earlier, the approach accepts
that there will be bias points where there is frequency
dependence but attributes this dispersion to heating
and trapping. In the same way that a memory effect
is just a slowly responding trap, that negative output
resistance in current characteristics is just a slow heating effect, so dispersion is just an interaction with the
frequency response of state variables.
Dispersion is shown in Figure 7, where the drain
capacitances and drain conductance are varied by
impact-ionization trapping effects. The drain resistance decreases at the kink in the current characteristic,
but only at the bias point where the trap response rate
matches the signal frequency. The coincident modulation of the drain current and feedback through the trap
element to the gate combine to change the trans-dependent reactive current as well.
Note that the dispersion shown in Figure 7 is really
of the small-signal admittance parameters. The capacitance and resistance values shown here are derived
directly from these parameters using the relationships
in Figure 2(b) without accounting for state variables.
The results are easily reproduced with the large-signal
model shown in Figure 6, with which the capacitance
and resistance values are independent of frequency and
the dispersion of the admittance parameters is the result
of the frequency dependency of the state variables.
The intrinsic gain, the voltage gain into an open-circuit load computed as the product of transconductance
and drain resistance, exhibits frequency dispersion that
highlights the rate of response of the state variables [30],
[36]. The intrinsic gain covering a very wide spectral
range is shown in Figure 8. Although a network analyzer can cover most of the band, the low-frequency
data may require a low-frequency analyzer or a similar
test fixture [37], or could be derived from the pulse data.
A drop in gain at low frequencies is the most striking feature of the intrinsic gain surface. This is caused
by impact-ionization-related trapping, which has a

April 2015

Cliffhanger
The requirement to control linearity at microwave frequencies is probably the most compelling reason to
characterize and model the full dynamics of heating
and trapping processes in transistor models. At the
very least, an a priori understanding of these processes
is essential to the appreciation of their contribution to
distortion and intermodulation of a broadband circuit.
A dramatic display of a traps contribution to nonlinearity is shown in Figure 9. Here, a two-tone measurement of intermodulation at microwave frequencies
is plotted against the frequency difference separating
the tones. Sweeping the tone spacing causes the intermodulation to fall over a cliff at the locus of bias and
response rate of an impact-ionization-related trapping
process [23], [38], [39]. The difference frequency intermodulation technique can also be use to map the thermal and gate- and drain-lag responses [31].

Impact-Ionization-Related
Trapping
15

Isodynamic
Gain

Intrinsic 10
Gain
5

100 GHz
100 MHz
100 KHz
100 Hz
Frequency

Current
Lag from
Trapping

SelfHeating

4V
2V
tential
o
P
in
Dra

Figure 8. The intrinsic gain, the ratio of transconductance

to drainsource conductance, is also affected by trapping and
heating effects. This plot is useful for characterizing the time
constants of these effects. The rate of impact-ionization-related
trapping is most notable with a characteristic frequency
climbing from a few kilohertz to gigahertz as drain bias
increases. The low-frequency knee is affected by gate lag, and
heating is affecting the high-potential, low-frequency corner.

April 2015

Reproduction of the intricate

and subtle aspects of nonlinearity
and transient behavior requires
intricate and subtle interaction
with state variables.
Reproduction of the intricate and subtle aspects
of nonlinearity and transient behavior requires intricate and subtle interaction with state variables. This
challenges the notion that large-signal models can
be simply fitted to small-signal and dc measurements. Rather, the core charge and current relationships need to be fitted to conservative, dispersion-free
small-signal data to ensure that there is correct separation of, and hence interaction with, the state variable
characteristics.
In summary, the key to an accurate simulation of
nonlinear broadband circuits is a fully characterized
large-signal model of FET characteristics with appropriate thermal and trapping state variables. Placing a correct divide between the access network, the
frequency-independent current and charge relationships, and the state variable elements provides several
benefits. The large-signal model can be relied on for
small-signal analysis because it is derived through
direct integration and adds dispersion due to interaction with state variables. The conservative nature
of the relationships improves simulator convergence.
The architecture allows accurate scaling of the model
so that it successfully can describe unseen device layouts and operating conditions [40]. A model derived

Intermodulation Level (dB)

response rate that exponentially extends to gigahertz

frequencies as drain bias increases. At a high enough
frequency, the intrinsic gain settles to dispersion-free
values because the responses are isodynamic. The drop
in gain is also observed as the discrepancy between
gain calculated from the dc characteristics and the gain
the from low-frequency small-signal measurements.
There is peaking in the low-frequency, low-bias
region of the intrinsic gain surface that can be related
to gate lag. In wide-bandgap technologies, the time
constants can be so long that a significant reduction in
gain is sustained for entire operational periods.

1.5 V
2.5 V 3 V
10 kHz

1 MHz

3.5 V

100 MHz

Difference Frequency (D~)

Figure 9. The difference frequency of a two-tone

intermodulation interacts with trapping and heating
responses. Here, there is a resonance with impactionization-related trapping that gives dramatic biasdependent variation in intermodulation. Similar, although
less dramatic, the effects from heating and gate lag can also
be seen at the appropriate bias points.

85

this way also leads to the prospect of extrapolation to

higher, millimeter-wave, frequencies using finite-element and electromagnetic simulation tools to model
the access network that is correctly separated from the
dispersion-free, active region.

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