Solid-Start Ehcfmnics Vol. 24, pp.

IS--164
@ Pergamon Press Ltd.. 1981. Printed in Great Britain

A NEW DIELECTRIC ISOLATION METHOD

USING POROUS SILICON
KAZUO IMAI
Musashino Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation,
Musashinoshi 3-9-11, Tokyo 180, Japan
(Received 23 January 1980; in revised form I3 March 1980)
Abstract-A
new dielectric isolation technology is proposed. In the new structure, single crystalline Si islands are
separated from the silicon substrate by oxidized porous silicon. It is based on the following characteristics of the
porous silicon oxide formation: (1) p-type Si is more easily changed to porous silicon than n-type Si; (2) porous
silicon is formed along the anodic reaction current flow line: (3) the change in volume of porous silicon after
oxidation is relatively small; (4) thick porous silicon films (IO pm) can bcobtained easily. In this method, a p-type
isolated layer is obtained by proton implantation used for an n-type layer formation. Lateral p-n junctions fabricated in
such isolated silicon layers show lower leakage current than those reported in SOS technology.

1. INTRODUCTION

@I) is an excellent technique for

isolating active devices in an integrated circuit. In DI
structures, circuit components are isolated by dielectric
material, resulting in low parasitic capacitance and high
voltage isolation. One DI structure example is shown in
Fig. 1[I]. This DI structure has a number of advantages,
but the complicated production process, including
deposition of thick poly-crystalline silicon and grind back
polishing, prevents wide appearance of dielectric isolated
integrated circuits. Another kind of DI structure can be
realized by using Silicon on Sapphire (SOS)
technology(21. However, deterioration of device characteristics in SOS technology, caused by defects in the
epitaxially grown silicon layer and aluminum diffusion
during the heat treatment, have been reported by several
authors[3,4].
In this paper, a new DI structure and method using a
simple process technology is proposed. In the new
method, porous silicon is formed under a single crystalline silicon layer by anodic reaction along a reaction
current flow line, which surrounds the layer from bottom
to brim.
After an oxidation process, the single crystalline silicon layer is separated from the substrate by oxidized
porous silicon. Processing steps and experimental results
for the new DI method are discussed.
Dielectric

Isolation

Process steps for the new DI method are shown in Fig.

2. First, an n-type layer is formed selectively in p-type
Si. Then, porous silicon is formed in hydrofluoric acid
(HF) by anodic reaction. In the anodic process, the
Single Si

SiOa

;
Poly Si

Fig. 1. Conventional DI structure.

(a)

(b)

2. BABICPRIh'CIPLEOFTHENEWDIMETHOD
The new DI method is based on the following characteristics of the porous silicon formation reaction: (1)
Holes are necessary in the anodic reaction[5]. Therefore,
p-type Si is more easily changed to porous silicon than
n-type Si. (2) Porous silicon is formed along the anodic
reaction current flow line. (3) Porous silicon density is
about half that of single crystalline silicon[6]. Therefore,
the volume change when porous silicon is oxidized is
very small. (4) The oxidation rate of porous silicon is
large enough to easily form a 10 grn thick isolation layer.

(d)

(e)

P-Si

Fig. 2. Processing steps for new DI process.

I59

160

KAZUO

silicon surface in the p-type region is changed to porous

silicon because of characteristic (1) above. The current
flow is as shown in Fig. 2(b). After the front of
the porous silicon region reaches the bottom of the p-n
junction, part of the porous silicon proceeds around
behind the n-type silicon, as shown in Fig. 2(c), because
of characteristic (2). As the anodic reaction continues,
the n-type layer is separated from the p-type silicon by
porous silicon, as shown in Fig. 2(d).
Because of characteristics (3) and (4), the wafer surface is very flat and a single crystalline silicon layer still
remains after the porous silicon oxidation process as
shown in Fig. 2(e).
In the DI structure shown in Fig. 2, an n-type silicon
layer is formed. It is possible to obtain a p-type isolated
Si layer by using proton implantation for n-type Si layer,
formation. Proton implantation produces shallow donors
after 300-500C annealing. These donors disappear with
annealing at temperatures above 7OOC[7].An n-type
layer formed by proton implantation can be used for the
selective anodization process shown in Fig. 2. The
porous silicon oxidation temperature is 9O&lOOOC.
Therfore, the shallow donors in the isolated single silicon
layer disappear in the porous silicon oxidation process
and a p-type isolated silicon layer is obtained.
3. EXPERIMENTS

3.1 Donor profiles

The silicon wafers used were 50 R cm n-type (100) and
1.7R cm p-type (100) wafers 3 in. in dia. and 400 pm
thick. The n-type wafers were used for measurements of
the donor profiles produced by proton impiantation and
the p-type wafers for the DI structure formation.
Donor profiles were measured by pulsed C-V method
in MOS diodes prepared as follows. n-Type silicon
wafers were cleaned in aqueous solution of NH,OHHz02, HCI-HtO, and HF, and then rinsed in deionized
water. SiO, films 5OOA thick were formed by thermal
oxidation at 1oooC in dry 0, ambient. Protons were
implanted through the SOOASi02 with an implantation
energy of 60 or 100keV at a dose of 1x 1Olcm. The
implanted layers were annealed at 450 or 700C for
30 min in N2 ambient. Aluminum was evaporated to form
5OOpm square gate electrodes .for the MOS diodes.
Aluminum was also evaporated on the back of the
wafers to provide ohmic contacts to the wafers. The
donor profile calculations were made using the formulas
derived by Ziegler et al.[S]. In the formulas, the contribution of the majority carriers to space charge capacitance is totally taken into account.
3.2 DI structure formotion
p-Type silicon wafers were cleaned and 500 A SiO, films
were formed by thermal oxidation. An evaporated molybdenum film was used as a mask for selective proton
implantation. Protons were implanted through the 500 8,
Si02 film. The implantation dose was 1 x 105/cm2and the
energy 60 or 100keV.
Before the anodization process, the molybdenum film
was removed, the implanted layer annealed at 450C for
30 min in N2 ambient, and the 500 8, Si02 film removed.

IMAI

The porous silicon was formed in 40 wt% HF acid by

anodic reaction. The growth rate for porous silicon at
10 mA/cm current density was about 0.1 pm/l0 sec.
After the porous silicon formed, it was oxidized at
950C for 400min in wet O2 ambient. The donor state
produced by proton implantation disappeared under the
heat treatment during the oxidation process. The single
crystalline silicon was also oxidized and a 1.0 pm thick
SiO, film was formed. Then, the SiO, on the isolated Si
layer was etched selectively.
A lateral p-n junction formed in the isolated layer by
As ion implantation in which 1 x 106/cm2 As ion were
implanted at 110keV energy. The wafers were subsequently annealed at 1000Cfor 300 min in N2 ambient.
The surface was covered with a 4000 A thick SiOz film
grown by chemical vapor deposition at 450C. Contact
holes were formed and aluminum for electrodes
evaporated. A cross sectional view of the lateral p-n
junction is shown in Fig. 3.

4. RESULTS AND DISCUSSM)N

4.1 Donor profiles

Donor concentration profiles in MOS diodes after
450C annealing determined by the pulsed C-V method
are shown in Fig. 4. Each profile has a concentration
peak whose depth agrees well with implanted
proton or implanted proton induced damage peak values
of other measurements, such as Chu et af.[9] and Magee
et a/.[lO]. It is not clear how proton implantation
generated a donor state from the present results, but a
donor state sufficient to form an n-type layer in p-type
1.7 R cm substrate was produced under these implantation conditions.
Figure 5 shows the C-V curve for 450 and 700C
annealing when the proton energy is 60 keV.
The C-V curve for 450C annealing has a small
gradient at a capacitance where the surface depletion
region width corresponds to the donor concentration
peak depth. With 700C annealing, the small gradient
part disappears and the capacitance changes as expected
for constant bulk donor concentration (1 x 10?cm3).
Therefore, with 700C annealing, the donor state
produced by proton implantation disappears completely.
4.2 DI structure
A photographic cross sectional view of the DI structure before oxidation is shown in Fig. 6.
The proton implantation energy in this case was
60 keV, so the n-type layer is about 0.5pm thick.
AI

CVD Si02

Al

Si
I

Fig. 3 Cross sectional view of the fabricated

tion.

lateral p-n junc-

A new dielectric isolation method using porous silicon

Si

N-Si

Porous Si

P-Si

Fig. 6. Photographic cross sectional view of the DI structure

before oxidation process.

Si

Fii. 7. SEM photomicrograph of a cross section of the DI

structure after oxidation.

161

A new dielectric isolation method using porous silicon

4WCM

IOb

In this method, a completely isolated silicon island

width is decided by the porous silicon thickness. As
shown in Fig. 6, after the front of the porous silicon
reaches the bottom of the p-n junction, part of the
porous silicon proceeds around behind the n-type layer
and the lateral spread of the porous silicon is almost
equal to its thickness under the bottom of the p-n
junction. So, porous silicon thickness T is necessary to
isolate the n-type island, whose thickness t and width w
are shown by

30mm.omeol

* 4 0.5
s
Depth (pm 1

1.0
1

Fig. 4. Depth distribution of donor concentration

pulsed C-V method.

determined by

The main problem with the DI structure is the characteristics of the interface between isolated silicon layer
and porous silicon oxide. Figure 8 shows the reverse I-V
characteristics for a 5& wide lateral p-n junction formed in the isolated silicon layer. The reverse current is
proportional to the square root of the reverse voltage, so
the generation-recombination current in the depletion
region is the main component of the reverse current. The
leakage current is smaller than in SOS structures. [I I].

<..
:
. .

5.CONCLUSION

A new dielectric isolation structure and method have

been proposed. The new method uses oxidized porous
silicon formed under the single crystalline silicon layer.
The processing steps for the new method are simpler
than those for conventional DI method and are more
stable than those of the SOS technology.
In the DI method, the isolated Si layer is formed of a
part of the original bulk Si. Therefore, a layer of single

, .
450c
. . . . .._ . .

x.

163

X\.

,. 7OOC anneal

...x.
k.

-..._
.......

-5

Gate

Voltage

-10

-15

-20

(VI

Fig. 5. Puked C-V curves for 450 and 700C annealing after
proton implantation.

The porous silicon is about 2.5 pm thick. As the porous

silicon is not thick, the n-type layer is not perfectly
isolated. However, as shown in Fig. 6, part of the porous
silicon proceeds around behind the n-type Si layer.
An SEM photomicrograph of a cross section of the DI
structure after oxidation is shown in Fig. 7. In this case,
the proton implantation energy was 100keV and 0.8 @rn
thick n-type layer was formed. The porous silicon was
about 10 pm thick. The IO grn wide silicon layer was
completely isolated from the p-type silicon substrate by
the oxidized porous silicon. The isolated silicon thickness was reduced to about 0.4km, because the 0.8pm
thick n-type layer was oxidized in porous silicon oxidation process.

IO&-----J

1.0

IO

Reverse Voltoge (V)

Fig. 8. Reverse I-V characteristics of a lateral p-n junction

formed in the isolated silicon layer.

KAZIJO
IMAI

164

formed by the formation of a thin n-type Si layer. Also,

p-type isolated Si layers can be obtained by proton
implantation in n-type Si layer formation.
The characteristics of fabricated lateral p-n junction
in the isolated layer show lower leakage current than
those with SOS technology.
The new DI method is very useful for high speed and
high packing density integrated circuit fabrication.
p-type isolated Si layers can be obtained by proton
implantation in n-type Si layer formation.
Acknowledgemenls-The author wishes to thank Mr. M. Kondo
and Mr. Y. Yoriume for their encouragement and helpful discussions. He is also gratful to the staff of the Semiconductor
Memory Technology Section, Mask and Pattern Gerneration
Section at Musashino Electrical Communication Laboratory for
device fabrication.
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