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2.

3.

The ___________ is a microscopic flaw in a wafer.

a. silicon crystal ingot
b. die
c. defect
d. chip
e. semiconductor
The server can be best described as:
a. Computer used to run large problems and usually accessed by a network
b. Computer composed of hundreds to thousands of processors and terabytes of memory
c. Thousands of processors forming a large cluster
d. Currently the largest class of computer that runs one application or one set of related applications
e. Desktop computer without screen or keyboard usually accessed via a network
_____________ can be best described as a command that the processor can understand
a. Compiler
b. Instruction
c. Assembly language
d. Machine language
e. System software

Program
Program 1
Program 2

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Use the following tables and information for answering questions 4-8:

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1.

# instructions
load
store
branch
400
100
50
300
100
100

compute
1

load
10

store
10

total
1550
2000

branch
3

Instruction
# cycles

compute
1000
1500

Assume we want to run Program 1 and program 2 on the processor with 3 GHz.

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What is the CPI using Program 1?

a. 24
b. 6
c. 5.5
d. 3.97
e. 1.38
How long does the processor take to execute Program 2?
a. 16 s
b. 4 s
c. 2.05 s
d. 1.93 s
e. 1.1 s
Which of the following statements is correct?
a. The processor runs Program 1 (1.06) times faster than Program 2
b. The processor runs Program 1 (0.94) times slower than Program 2
c. The processor runs Program 2 (1.06) times faster than Program 1
d. The processor runs Program 2 (1.06) times slower than Program 1
e. The processor runs Program 1 (2.0) times faster than Program 2

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4.

5.

6.

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8.

What is the speedup achieved for executing Program 1 if the number of load instruction can be reduced by one half?
a. 1.49
b. 0.67
c. 2.0
d. 0.5
e. 1.35
What is the geometric mean of the different instruction classes?
a. 6
b. 4.9
c. 24
d. 17.3
e. 4.16

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7.

The following table shows the manufacturing data for a processor. Use it for answering questions 9-10:
Wafer diameter
25 cm

Defects per unit area

2
0.024 defects/cm

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9.

Cost per wafer

20

Find the yield.

a. 81.4 %
b. 88.2 %
c. 92.1 %
d. 96.4 %
e. 97.2 %
10. Find the cost per die.
a. 0.143
b. 0.176
c. 0.162
d. 0.155
e. 0.148

Dies per wafer

140

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The following table shows the SPECpower_ssj2008 running on a certain server. Use it for answering question 11.

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Target load %
100 %
90 %
80 %
70 %
60 %
50 %
40 %
30 %
20 %
10 %
0%

Performance (ops/s)
110,256
101,204
89,597
79,068
67,865
56,959
45,280
34,551
23,814
12,066
0

Average Power (Watts)

205
196
188
179
168
157
145
139
127
113
102

11. Find the overall ssj_ops per watt.

a. 516.3
b. 537.8
c. 404.0
d. 106.8
e. 361.1

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Consider the program in the following table running on a processor with clock rate = 3 GHz. Use it for answering questions
12-13:
Instr. Count
6
10

L/S instr.
50%

FP inst.
40%

Branch instr.
10%

CPI(L/S)
0.75

CPI(FP)
1.0

CPI(Branch)
1.5

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12. Find MIPS.

a. 3243
b. 1720
c. 5214
d. 4518
e. 10589
6
13. Define MFLOPS = No. FP operations/(Execution time 10 ). Find MFLOPS.
a. 1297
b. 1946
c. 4235
d. 688
e. 2086
14. Considering the following MIPS machine instruction
00af8020hex
which of the following statements is true?

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a. $rs = $10
b. $rt = $10
c. $rd = $16
d. shamt = 00001two
e. funct = 000000two
15. The following sequence of MIPS instructions
slt $at, $t5, $t3
beq $at, $zero, L
is equivalent to which pseudoinstruction?

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a. bge $t5, $t3, L

b. bge $t3, $t5, L
c. bgt $t3, $t5, L
d. bgt $t5, $t3, L
e. ble $t5, $t3, L
16. -2048ten converted into a 32-bit twos complement binary number is:
a. 1111 1111 1111 1111 1111 0111 1111 1111
b. 1111 1111 1111 1111 1111 1000 0000 0000
c. 1111 1111 1111 1111 1110 1111 1111 1111
d. 1111 1111 1111 1111 1111 0000 0000 0000
e. 1111 1111 1111 1111 1111 1100 0000 0000
17. Which of the following MIPS instructions is considered an unconditional branch instruction?
a. beq
b. bne
c. jal
d. slt
e. none of the above

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18. Originally, MIPS computer stands for

a. Million Instructions Per Second
b. Mega Instructions Per Second
c. MIPS is not an acronym
d. Microprocessor without Interlocked Pipeline Stages
e. None of the given choices
19. Consider the following MIPS statements
A: addi $t1, $zero, 4
addi $t2, $zero, -4
beq $t1, $t2, B
and $s3, $t1, $t2
or $s4, $t2, $t2
B: slt $s1, $t1, $t2
bne $s3, $s4, A
sub $s5, $s4, $zero
What is the instruction that is executed after the beq instruction?
a. and $s3, $t1, $t2
b. or $s4, $t2, $t2
c. slt $s1, $t1, $t2
d. bne $s3, $s4, A
e. sub $s5, $s4, $zero
20. The following bit stream represents a MIPS instruction. What register will be written?
10100010001100101010000110000101
a. $s4
b. $s1
c. $s2
d. $3
e. None
21. Consider the following MIPS instruction
beq $t0, $s1, L
Suppose L = 101011110011000010
Which of the following is correct
a. The instruction cannot be executed
b. L must be first loaded into a register using lui and ori instructions
c. An unconditional jump to the branch target can be inserted and the condition inverted
d. The instruction jal can help
e. The instruction can be executed without any modifications
22. Which of the following must be executed by the callee?
a. j
b. jal
c. beq
d. jr
e. bne
23. Which of the following instructions is an example of a PC relative addressing mode?
a. add $t5, $s2, $s3
b. multi $t5, $s2, 60
c. bne $s2, $s3, L1
d. lw $t5, -20($s2)
e. none of the given choices

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24. Suppose that $t7 initially holds the value 3. What is the value stored in $t7 after executing the following statement?
sll $t6, $t7, 4
a. 3
b. 6
c. 12
d. 24
e. 48
25. The following program tries to copy words from the address in register $a0 to the address in register $a1, counting
the number of words copied in register $v0. The program stops copying when it finds a word equal to 0. You do not
have to preserve the contents of registers $v1, $a0, and $a1. This terminating word should be copied but not
counted.
addi $v0, $zero, -1
loop: lw, $v1, 0($a0)
addi $v0, $v0, 1
sw $v1, 0($a1)
addi $a1, $a1, 4
bne $v1, $zero, loop
which of the following actions will turn the above code into a bug-free version?
a. addi $v0, $zero, -1 must be replaced by addi $v0, $zero, 0
b. addi $a0, $a0, 4 must be inserted between sw and addi instructions
c. addi $v0, $v0, 1 must be replaced by addi $v0, $v0, 4
d. bne $v1, $zero, loop must be replaced by beq $v1, $zero, loop
e. The above code is already bug-free

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