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VLSIDesignMethodology

FinalProjectReport
Programmable
ConvolutionalEncoder

VadimSmolyakov
SafeenHuda

Copyright2009UniversityofToronto


Introduction

In this document, a design overview of a programmable convolutional encoder is presented.


Convolutional encoding is a widely used coding technique that facilitates error correction at the
receiverend of a communication link. Programmable convolutional encoders are especially suited for
FPGA applications. Commercial FPGA vendors offer softIP in the form of RTL code to consumers to
alloweffortlessimplementationofhighperformanceerrorcorrectioncodes.Inthiswork,wepropose
the design of a programmable convolutional encoder a hardware block that can be programmed to
implementawidevarietyofconvolutionalencodingschemes.Thishardwareblockcouldpotentiallybe
implemented as part of a larger reconfigurable transmitter/transceiver system or as a new
programmablecustommlayoutIPimplementedinaheterogeneousFPGAarchitecture.

ChipOverview
SystemLevelOverview
Atoplevelsystemoverviewisshowninthefollowingdiagram:

Input Data
Stream
INPUT DATA REGISTER

CONFIGURATION MEMORY

SWITCH MATRIX (STEERING LOGIC)

MOD-2 ADDER ARRAY

INTERLEAVER BLOCK (PARALLEL


TO SERIAL CONVERTER)

Output
Data
Stream

Figure1:SystemLevelDiagram

Theproposedsystemusesashiftregisterwhicheffectivelystorespastsamplesoftheinputdatastream.
These past samples of data are then added together in a configurable order (through the use of the
switchmatrixandmod2adderarray);indeed,thereexistsavarietyofconvolutionalencodingschemes
andeachoffersatradeoffbetweenthetransmissionrateandtheamountoferrorcorrectionthatcan
berealized.Finally,aninterleaverblockpresentsaserialoutputofthedata.
Thenoveltyintheproposedsystemisinthewaypastsamplesaregroupedthroughaconfigurableas
opposedtoafixedarchitecture.Theswitchmatrix(whichactsassteeringlogic)andthemod2adder
arraycanbeprogrammed(bytheconfigurationmemory,implementedasashiftregister)suchthatthe
system as a whole can implement a wide variety of different encoding schemes; the end user of this
systemhastheflexibilitytotradeoffdatarateanderrorcorrectingcapability.Specifically,thedesigned
programmableconvolutionalencoder allowsfortheimplementationofasubsetofthemaximumfree
distancecodesasoutlinedintheIEEE802.16mstandard(thissubsetisprovidedintheAppendix).


BlockOverview

InputDataRegister

The input data register consists of a simple 8bit shift register, the outputs of individual flipflops are
usedbythedownstreamlogic(theswitchmatrixandthemod2adderarray),formingaconvolutionof
the input bitstream with a configurable impulse response of the encoder. The schematics and the
layoutforthisblockarepresentedintheappendix.

SwitchMatrix

ThedesignoftheswitchmatrixwasinspiredbyprogrammableroutingsuchasthatfoundinFPGAs.The
switchmatrixmakesuseofNMOSpasstransistorstoconnectinputsoftheadderarraytooutputsofthe
input data register. The number of transistors in the switch matrix and the pattern of connectivity
between the outputs of the data register and the inputs of the adder array were both decided on by
optimizingforminimumnumberoftransistors,whilesupportingthetargetedencodingconfigurations.
Alternatively,theswitchmatrixcanbeusedtosetaninputoftheadderarrayto0(thisiscrucialasit
helps facilitate the many different modes of the mod2 adder array). Schematics and layout for this
blockareprovidedintheappendix.

Mod2AdderArray

The Mod2 adder array is a tree like structure of two input adder arrays, in addition to multiplexing
circuitry,whichallowsforittobeconfiguredasasetofadderswithawidevarietyofaddersizes.The
array is comprised of four configurable adder blocks. A symbolic diagram for the configurable adder
blockisshownbelow:

INPUTS

4 to 1
MUX

4 to 1
MUX

OUTPUTS

Figure2:Reconfigurableaddercelldiagram

Notethatthemod2addersareimplementedusing2inputXORsandcanbeconfiguredtoimplementa
varietyofdifferentaddersbysettingsubsetsoftheinputsignalstozeroandbyconfiguringtheselect
signals of the two 4input muxes accordingly. In fact, the reconfigurable adder block can support the
followingaddersizes:
AdderSize
2
3
4
5
6
7
8

MaximumNumberofAdders
ImplementableperBlock
2
2
2
2
2(withsharedinputs)
2(withsharedinputs)
2(withsharedinputs)

Figure3:ReconfigurableAdderCellpossibleconfigurations

ItshouldalsobenotedthattheconfigurableadderblockcontainsasetofPMOSsleeptransistorsused
to shut of parts of the adder block that are not being used; this allows for savings in static power
dissipationforconvolutionalencodingschemeswhichdonotusealloftheresourcesmadeavailableby
theconfigurableadderblock(pleaserefertotheschematicsforthelocationofsleeptransistors).

The complete adder array (comprised of 4 reconfigurable adder blocks) along with the programmable
switch matrix gives the required flexibility to implement the set of targeted convolution encoding
schemes.

ConfigurationMemory

The configuration memory is implemented as a simple shift register with a singlebit wide input. A
particular encoding scheme is achieved by shifting a sequence of configuration bits serially with an
enablesignalusedtocontroltheshiftduration.

Interleaver/ParalleltoSerialConverter

Theinterleaver/paralleltoserialconverterusesan8inputmuxanda3bitcounter.Theeightinputsto
themultiplexerareformedbythe4configurableadderblockswith2outputseach.Theoutputofthe
counterisusedtocontroltheselectsignalsofthemultiplexer.Everyclockcycle,thecountereffectively
selects a different input of the mux to be output by the block. Thus, each of the 8 inputs of the mux
(whichcorrespondtothe8outputsoftheadderarray)arecycledthroughcontinuously,creatingaserial
data stream from a parallel input. The output of the interleaver is the output data sequence of the
programmableconvolutionencoder.

TopLevel

Thefollowingtableshowsapintableforourchip:
PinName
din
clk
rstn
en
cntl1
cntl2
cntl3
cntl4
cntl5
out
vdd!
gnd!

Input/Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Inout
Inout

Function
InputData
EncoderClock
ActiveLowReset
Confshiftregisterenable
ConfigurationData1
ConfigurationData2
ConfigurationData3
ConfigurationData4
Configurationpin(AdderArray)
EncoderOutput
Supply
Ground

Figure4:PinTable

Whileschematicsandlayoutsforindividualblocksareprovidedintheappendix,shownbeloware
schematicsandlayoutforthetoplevelcoreaswellasthetoplevelcorewithpadframe.

PADS

DataRegister
SwitchMatrix

AdderArray +
Interleaver
Configuration
Memoryfor
AdderArray

Figure5:TopLevelSchematic

Cntl1

Cntl2

din

Cntl3

Cntl4

Cntl5

CORE

clk

vdd!

rstn

gnd!

en

out

vdd!

gnd!

vdd!

gnd!

Figure6:TopLevelLayoutwithPadframe

DataRegister
ConfigurationMemory

SwitchMatrix

AdderArray

Interleaver

Configuration
Memory

Figure7:TopLevelCorelayout

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TeamMemberContribution

Cell
FlipFlopsandRegisters

Schematic

Layout

VadimSmolyakov

VadimSmolyakov

Interleaver

VadimSmolyakov/SafeenHuda

VadimSmolyakov/SafeenHuda

Switchmatrix

VadimSmolyakov/SafeenHuda

VadimSmolyakov

SafeenHuda

SafeenHuda

TopLevel

VadimSmolyakov/SafeenHuda

VadimSmolyakov/SafeenHuda

PadFrame

VadimSmolyakov

VadimSmolyakov

AdderArray

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Appendix
DataRegisterSchematic

FlipFlop

DataRegisterLayout

FlipFlop

12

SwitchMatrixSchematic
ConfigurationMemory
SwitchMatrix(withnmospasstransistors)

SwitchMatrixLayout

ConfigurationMemory

SwitchMatrix(withnmospasstransistors)

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ConfigurableAdderBlockSchematic

SLEEP_2

4 to 1
MUX

4 to 1
MUX

SleepTransistors

ConfigurableAdderBlockLayout
XOR

XOR

SleepTransistors

14

AdderArraywithInterleaverSchematic

Configurable
AdderBlock

Interleaver

AdderArraywithInterleaverLayout

Configurable
AdderBlock

Interleaver

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LVSREPORT
@(#)$CDS: LVS.exe_64 version 5.1.0-64b 04/27/2009 03:12 (cicamd10) $
Command line:
/autofs/CMC_2001/CMC/tools/cadence.2000a/IC.5141.ISR200905011535/tools.lnx86/
dfII/bin/64bit/LVS.exe -dir /autofs/gulak/b/b2/svadim/CMOSP35/LVS -l -s -t
/autofs/gulak/b/b2/svadim/CMOSP35/LVS/layout
/autofs/gulak/b/b2/svadim/CMOSP35/LVS/schematic
Like matching is enabled.
Net swapping is enabled.
Using terminal names as correspondence points.
Net-list summary for /autofs/gulak/b/b2/svadim/CMOSP35/LVS/layout/netlist
count
958
nets
12
terminals
1041
nfet
20
diode
1026
pfet
Net-list summary for
/autofs/gulak/b/b2/svadim/CMOSP35/LVS/schematic/netlist
count
958
nets
12
terminals
1041
nfet
20
diode
1014
pfet

Terminal correspondence points


N816
N44
clkp
N1092
N20
cntl1p
N84
N31
cntl2p
N258
N86
cntl3p
N651
N114
cntl4p
N1127
N80
cntl5p
N374
N67
dinp
N779
N98
enp
N423
N1
gnd!
N441
N51
outp
N996
N101
rstnp
N571
N0
vdd!
Devices in the netlist but not in the rules:
diode
Devices in the rules but not in the netlist:
capacitor resistor
The net-lists match.

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un-matched
rewired
size errors
pruned
active
total

un-matched
merged
pruned
active
total

un-matched
matched but
different type
total

layout schematic
instances
0
0
0
0
0
0
0
0
2087 2075
2087 2075
nets
0
0
0
0
0
0
958
958
958
958
terminals
0
0
0
12

0
12

Probe files from /autofs/gulak/b/b2/svadim/CMOSP35/LVS/schematic


devbad.out:
netbad.out:
mergenet.out:
termbad.out:
prunenet.out:
prunedev.out:
audit.out:

Probe files from /autofs/gulak/b/b2/svadim/CMOSP35/LVS/layout


devbad.out:
netbad.out:
mergenet.out:
termbad.out:
prunenet.out:
prunedev.out:
audit.out:

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DRCReport
\o
\o
\o
\o
\o
\o
\o
\o
\o
\o
\o
\o
\o
\o
\o
\o
\o
\o
\o

DRC started at Thu Dec 24 15:28:43 2009


Validating hierarchy instantiation for:
library: DiodeLib_dec23
cell:
top_with_pads_v2
view:
layout
Rules come from library cmosp35.
Rules path is divaDRC.rul.
Inclusion limit is set to 1000.
Running layout DRC analysis
Flat mode
Full checking.
executing: nwell = geomAndNot("nwell" "drcex")
executing: nwellres = geomAndNot(geomAnd("nwellres" "nwell") "drcex")
executing: saveDerived(badNet "via12 net not covered by drawing")
executing: via23Net = geomGetPurpose("via23" "net")
executing: temp = geomAndNot(via23 geomAnd(metal2 metal3))
executing: saveDerivedtemp("floating via23")
executing: drc(metal3 (width < rule) rule_text)

...
\o executing: temp = geomEnclose(via34 metal3)
\o executing: saveDerivedtemp(rule_text)
\o executing: temp = geomAndNot(via34 geomAnd(metal3 metal4))
\o executing: saveDerivedtemp("floating via34")
\o executing: saveDerivedtemp(rule_text)
\o executing: temp = geomSize(geomSize(geomAndNot(metal4 pad) -5.0) 5.0)
\o executing: drctemp((sep < 0.08) "sep of wide metal4 < .08")
\o executing: drc(pad (sep < 60) "Warning: If you bond through CMC, keep pad
pitch to 150 microns")
\o DRC started.......Thu Dec 24 15:28:43 2009
\o
completed ....Thu Dec 24 15:29:09 2009
\o
CPU TIME = 00:00:06 TOTAL TIME = 00:00:26
\o ********* Summary of rule violations for cell "top_with_pads_v2 layout"
*********
\o # errors Violated Rules
\o
12 Warning: If you bond through CMC, keep pad pitch to 150 microns
\o
164 Warning: substrate/well soft connected
\o
176 Total errors found

NOTE1:164substrate/wellsoftconnectionsareexpectedandareintroducedbythesleeptransistors
thatconnectvddislandsofadderarrayandswitchmatrixsubcells.Whenthesleeptransistorsare
removedandreplacedwithadirectconnectiontoVDD,thewarningsdisappear.
NOTE2:Apitchoflessthan150umwaschosenforthepadframeforcompactness.

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