UNIT-III

5. a) Explain in detail about Random Testing for combinational

circuits
b) Explain any one automated Test pattern generation

6
6

OR

6. a) Explain Functional Fault Models for Microprocessors

b) List out the trade offs in implementing Testability at chip level

6
6

UNIT-IV
7. a) Explain about clocked hazard free latches used in LSSD?
b) List out the advantages of LSSD over scan path technique

6
6

OR
8. a) Perform Syndrome Test on a simple combinational circuit
b) Obtain signatures for Fault Free O/P and Faulty O/P for given
circuit

6
6

UNIT-V
9. a) Write short notes on generic off line BIST architecture
b) Explain in detail about different operating modes of BILBO

6
6

OR
10. a) Explain in brief about RTS and CEBS architectures
b) Discuss the design rules for self test at board level

6
6
[12/II S/212]

[April-12]

[EPRVD 204A]

M.Tech. Degree Examination

VLSI Design
II SEMESTER
DIGITAL SYSTEMS TESTING & TESTABILITY
(Effective from the admitted batch 200910)
Time: 3 Hours
Max.Marks: 60
--------------------------------------------------------------------------------- ------------------Instructions: Each Unit carries 12 marks.
Answer all units choosing one question from each unit.
All parts of the unit must be answered in one place only.
Figures in the right hand margin indicate marks allotted.
--------------------------------------------------------------------------------------- -------------

UNIT-I
1. a) Explain the Modelling of Digital circuits at logic level
b) Derive a binary decision diagram for the functions

abc ac ab

6
6

OR

2. a) Define Static, Dynamic and Essential hazards with the help of

simple combinational circuit
b) Explain about Gate level event driven simulation

6
6

UNIT-II
3. a) What is the principle of path sensitizing and when a is said to
be sensitized? What is the disadvantage of path sensitization
technique
b) Explain in detail about stuck at and stuck open faults

6
6

OR

4. a) Discuss in brief about Bridging and Temporary Faults

b) Explain concurrent Fault Simulation

6
6

UNIT-III
5. a) Explain in detail about Random Testing for combinational
circuits
b) Explain any one automated Test pattern generation

6
6

OR

6. a) Explain Functional Fault Models for Microprocessors

b) List out the trade offs in implementing Testability at chip level

6
6

UNIT-IV
7. a) Explain about clocked hazard free latches used in LSSD?
b) List out the advantages of LSSD over scan path technique

6
6

OR
8. a) Perform Syndrome Test on a simple combinational circuit
b) Obtain signatures for Fault Free O/P and Faulty O/P for given
circuit

6
6

UNIT-V
9. a) Write short notes on generic off line BIST architecture
b) Explain in detail about different operating modes of BILBO

6
6

OR
10. a) Explain in brief about RTS and CEBS architectures
b) Discuss the design rules for self test at board level

6
6
[12/II S/212]

[April-12]

[EPRVD 204A]

M.Tech. Degree Examination

VLSI Design
II SEMESTER
DIGITAL SYSTEMS TESTING & TESTABILITY
(Effective from the admitted batch 200910)
Time: 3 Hours
Max.Marks: 60
--------------------------------------------------------------------------------- ------------------Instructions: Each Unit carries 12 marks.
Answer all units choosing one question from each unit.
All parts of the unit must be answered in one place only.
Figures in the right hand margin indicate marks allotted.
----------------------------------------------------------------------------------------------------

UNIT-I
1. a) Explain the Modelling of Digital circuits at logic level
b) Derive a binary decision diagram for the functions

abc ac ab

6
6

OR

2. a) Define Static, Dynamic and Essential hazards with the help of

simple combinational circuit
b) Explain about Gate level event driven simulation

6
6

UNIT-II
3. a) What is the principle of path sensitizing and when a is said to
be sensitized? What is the disadvantage of path sensitization
technique
b) Explain in detail about stuck at and stuck open faults

6
6

OR

4. a) Discuss in brief about Bridging and Temporary Faults

b) Explain concurrent Fault Simulation

6
6