HISTORY OF VLSI

The electronic industry has achieved a phenomenon growth over the last few decades.
Mainly due to rapid advances in Integration technology and large stage system design. Typically
the required computational and information processing power of these applications is the driving
force of the fast development of this field.
Evolution of logic complexity in integrated circuit:
Here are some ERAs or generations on integrated circuits.

In Electronics, the first device was none other than Vacuum tube. After that the first
transistor was developed in 1947 in Bells laboratory. Since then electronics field has never
looked back.
First integrated circuit is designed with 2 transistors on a single chip. Then multiple more
than 2 transistors after that connection problem occurred. Multiple connection taking too much
space on chip so multilayer PBCs are introduced. But all these connections and circuits or
design are of discrete type. And main disadvantage of discrete design was these designs were
unreliable i.e. lose connection, heating problems, humidity, corrosion etc .
To overcome these problems new trend was introduced monolithic integration. The
monolithic integration of a large number of functions on a single chip usually provides:

Less size/volume and therefore compactness

Less power consumption
Less testing requirement at system level
Higher reliability, mainly due to improved on-chip interconnects
Higher speed, due to significance reduced interconnection length
Significant cost saving

EVOLUTION OF MINIMUM FEATURE SIZE IN INTEGRATED CIRCUIT OVER

TIME:

As technology advances feature size of a transistor is reduces. Feature size is the length
between source and drain. In 1970-80s minimum feature size was 2m and it is expected
around 0.3 m around 2000. The actually development is a technology, however, has far
exceeded these expectations. A minimum feature size of 0.25 m was achieved by 1993.
The first 64Mb DRAM and the INTEL Pentium microprocessor chip contains more than
3 million transistors were already available by 1994. The first 4GB DRAM based on 0.15 m
manufacturing technology was announced in early 1997. Current market feature size is around
22nm. INTEL fab has he minimum feature size of 14nm.
MOORES LAW:
the number of transistors per chip has continued to increase at an exponential rate over
the last three decades, and conforming the Gordon Moores prediction on the growth rate of the
chip complexity, Which was made in early 1960s (Moores law).
Moore predicted that the number of transistors on chip doubles every 18 to 24 months.
He also predicted that semiconductor technology doubles its effectiveness every 18 months.

What is VHDL?
VHDL: VHSIC Hardware Descriptive language.
VHSIC: Very High Speed Integrated Circuits.
Note: Normally there are one or two definitions for VHSIC according to local authors, Very
High Scale Integrated Circuits and above one. But Very High Speed Integrated Circuits is the
correct one. Hardware description language can be used to model a digital system at many levels
of abstraction ranging from the algorithmic level to the gate level.

Conventional languages Vs VHDL

The conventional software languages like C, C++, java etc. are all about sequential
execution, i.e. In JAVA each statement executes first then the next statement executes.
This is nothing but the sequential programming. But VHDL supports both concurrent as
well as sequential programming. Concurrent means more than one statement can be
executed at single instance.
While programming in conventional languages we dont know what is happening at the
hardware level for the logic we are implementing in the program. EX. if I am
programming a simple addition function in C++, after compiling and execution all we get
is addition functions. I dont have any idea about how hardware going to implement this
addition function i.e.at gate level or at transistor level.
VHDL is strongly type language. This means that operations and assignments are legal in
the language only if the types of the operands and the result match according to a set of
rules; it does not allow objects and literals of different types to be mixed freely in
expressions. Examples of illegal operations are adding a real value to an integer value,
and assigning a Boolean value to an object of type BIT. It is, therefore, important to
understand what types are and how they can be correctly used in the language.
VHDL is not Case sensitive.
Time can modeled using VHDL

VHDL is an Integration of following languages:

sequential language
concurrent language
net-list language
timing specifications
waveform generation language

Features /advantages/pros of VHDL

Hierarchy: The language supports hierarchy, that is, a digital system can be modeled as a
set of interconnected components; each component, in turn, can be modeled as a set of
interconnected subcomponents.
Flexible Design: The language supports flexible design methodologies: top-down,
bottom-up, or mixed.

Abstraction: designed can ne described at various levels of abstraction ranging from

abstract behavioral descriptions to very precise gate-level descriptions.
Design reuse
Technology independent: The language is not technology-specific, but is capable of
supporting technology-specific features. It can also support various hardware
technologies, for example, you may define new logic types and new components, and you
may also specify technology-specific attributes. By being technology independent, the
same behavior model can be synthesized into different vendor libraries.
The language has elements and module that make large scale design modeling and testing
easier, for example, components, functions, procedures, packages and test benches. Test
benches can be written using the same language to test other VHDL models.
Portability of designs: As it is an IEEE and ANSI standards, VHDL design are portable
across synthesis and simulation tools.
Time: time (delays, hold timings, time constraints) can be described in this language.
Using VHDL makes a design device independent.
The language is publicly available, human readable, machine readable, and above all, it is
not proprietary.

Limitations/CONs of VHDL

It does not support modeling at or below the transistor level. It allows a design to be
captured at a mixed level using a single coherent language.
Designer has very little control at the gate level.
The logic generated by the synthesis tool is not optimized optimization for time any
affect area utilize and vice-versa.
The logic generated for the same description mat varies from tool to tool. This may be
due to the algorithm used by the tools, which might be proprietary.

Data Objects

A data object holds a value of a specified type. It is created by means of an object

declaration. An example is
variable COUNT: INTEGER;
These results in the creation of a data object called COUNT which can hold integer
values. The object COUNT is also declared to be of variable class.

Every data object belongs to one of the following three classes:

Signal: An object belonging to the signal class has a past history of values, a
current value, and a set of future values. Future values can be assigned to a signal
object using a signal assignment statement.
Variable: An object of variable class can also hold a single value of a given type.
However in this case, different values can be assigned to the object at different
times using a variable assignment statement.
Constant: An object of constant class can hold a single value of a given type. This
value is assigned to the object before simulation starts and the value cannot be
changed during the course of the simulation.

SIGNALS

Signal objects are used to connect entities together and communication changes within a
design. Signals can also be defined as interconnections between the different components
inside the module, only the internal interconnections not I/O connections.
Signals can be declared in entity declaration sections, architecture declarations (signal is
local to that architecture), and package declarations. Signals in package declarations are
also referred to as global signals because they can be shared among entities.
Signal assignment is concurrent outside the process statement and sequential within a
process.
Signals take the last value assigned to it in a process statement and assign the value only
after the compilation of the simulation cycle run. If we perform multiple count operation
on signals in process statement, only once the count operation will compiled.
A signal has three properties assign to it.
Type and attributes
Value
Time
Syntax:
SIGNAL signal_name : signal_type [:= initial value];

Signal assignment: it uses assignment symbol <=

E.g. C <= 1;

Following is an example of signal declarations:

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
PACKAGE sigdecl IS
TYPE bus_type IS ARRAY (0 to 7) OF std_logic;
SIGNAL vcc

: std_logic := 1;

-- Declaration in Package

SIGNAL ground : std_logic := 0;

-- Declaration in Package

FUNCTION magic_function ( a : IN bus_type) RETURN bus_type;

END sigdecl;

USE WORK.sigdecl.ALL;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY board_design is
PORT (data_in : IN bus_type;
data_out : OUT bus_type);
SIGNAL sys_clk : std_logic := 1;

-- Declaration in Entity

END board_design;

ARCHITECTURE data_flow OF board_design IS

SIGNAL int_bus: bus_type;

--Declaration in Architecture

CONSTANT disconnect_value : bus_type:= (X, X, X, X, X, X, X,

X);
BEGIN
int_bus <= data_in WHEN sys_clk = 1
ELSE int_bus;
data_out <= magic_function (int_bus) WHEN sys_clk = 0
ELSE disconnect_value;
sys_clk <= NOT (sys_clk) after 50 ns;
END data_flow;

Signal updates can have a delay specified in their assignment statements.

clk <= not clk after 10 ns;

Signal objects can be regarded as wires in a circuit while variable and constant objects
are analogous to their counterparts in a high-level programming language like C or
Pascal. Signal objects are typically used to model wires and flip-flops while variable and
constant objects are typically used to model the behavior of the circuit

VARIABLE

Variables can be declared and used inside a process statement. A variable is assigned a
value using the variable assignment statement that typically has the form,
Variable-object : = expression;
The expression is evaluated when the statement is executed and the computed
value is assigned to the variable object instantaneously, that is, at the current simulation
time.

Variables are created at the time of elaboration and retain their values throughout the
entire simulation run (like static variables in C high-level programming language). This is
because a process is never exited; it is either in an active state, that is, being executed, or
in a suspended state, that is, waiting for a certain event to occur. A process is first entered
at the start of simulation (actually, during the initialization phase of simulation) at which
time it is executed until it suspends because of a wait statement or a sensitivity list.
Syntax:
variable variable_name : [range] [:= initial value];
The keyword VARIABLE is followed by one or more variable names. Each name creates
a new variable. The construct variable_type defines the data type of the variable, and an
optional initial value can be specified.
Variables are preferred over signals for the following reasons:
Variables are inherently more efficient because assignments happen immediately,
while signals must be scheduled to occur.
Variables take less memory, while signals need more information to allow for
scheduling and signal attributes.
Using a signal would have required a wait statement to synchronize the signal
assignment to the same execution iteration as the usage.
Variables dont have past history unlike signals.
Example using two variables is shown here:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY and5 IS
PORT ( a, b, c, d, e : IN std_logic;
q : OUT std_logic);

END and5;

ARCHITECTURE and5 OF and5 IS

BEGIN
PROCESS(a, b, c, d, e)
VARIABLE state : std_logic;
VARIABLE delay : time;

--Declaration of a variable
--Declaration of a variable

BEGIN
state := a AND b AND c AND d AND e;
IF state = 1 THEN
delay := 4.5 ns;
ELSIF state = 0 THEN
delay := 3 ns;
ELSE
delay := 4 ns;
END IF;
q <= state AFTER delay;
END PROCESS;
END and5;

This example is the architecture for a five-input AND gate. There are two variable
declarations in the process declaration section: one for variable state and one for variable
delay. Variable state is used as a temporary storage area to hold the value of the AND
function of the inputs. Temporary storage value delay is used to hold the delay value that
will be used when scheduling the output value. Both of these values cannot be static data
because their values depend on the values of inputs a, b, c, d, and e.

CONSTANTS

Constant objects are names assigned to specific values of a type. Constants give the
designer the ability to have a better-documented model, and a model that is easy to
update. For instance, if a model requires a fixed value in a number of instances, a
constant should be used.

By using a constant, the designer can change the value of the constant and recompile, and
all of the instances of the constant value are updated to reflect the new value of the
constant.
A constant has the same scoping rules as signals. A constant declared in a package can be
global if the package is used by a number of entities. A constant in an entity declaration
section can be referenced by any architecture of that entity. A constant in architecture can
be used by any statement inside the architecture, including a process statement. A
constant declared in a process declaration can be used only in a process.
Syntax:
constant constant_name : constant_type[ := initial value];
Examples of constant declarations are
constant RISE_TIME: TIME := 10ns;
constant BUS_WIDTH: INTEGER := 8:
constant NO_OF_INPUTS: INTEGER;

The value of the constant has not been specified in last case. Such a constant is called a
deferred constant and it can appear only inside a package declaration. The complete
constant declaration with the associated value must appear in the corresponding package
body.

ALIASES

An alias declares an alternate name for all or part of an existing object. It provides a
convenient mechanism notation to write names for objects that have long names. It also
provides a mechanism of referring to the same object in different ways depending on the
context.
Only objects signals, variables, and constants can have aliases, not types. Alternate names
can be provided for types by using subtype declarations.
For example,

The syntax for an alias declaration is

Alias alias_name : subtype is name;

For example,

variable DATA_WORD: BIT_VECTOR(15 downto 0);

alias DATA_BUS: BIT_VECTOR(7 downto 0) is DATA_WORD(15 downto 8);
alias STATUS: BIT_VECTOR(0 to 5) is DATA_WORD(5 downto 0);
alias RESET: BIT is DATA_WORD(6);
alias RX_READY: BIT is DATA_WORD(7);

Given these declarations, DATA_BUS can be used wherever DATA_WORD(15 downto

8) is used, RESET can be used wherever DATA_WORD(6) is used, and so on.

It is important to note that assigning a value to an alias name is the same as assigning a
value to the aliased name. The alias does not declare a new object but merely provides an
alternate way of referring to the original object. The alias of an array object may change
the way in which the array is indexed, as shown in the alias declaration of STATUS.