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Anubhav Srivastava
Department Of Electrical Engineering
IIT Kanpur
Abstract
In this project different characteristics of
MOSFET are plotted by TCAD simulation. Plot is compared
with the measured values and optimized to match the data.
Thereafter threshold voltage based model is implemented
involving mobility degradation and channel length modulation.
Gummel Symmetry test is also performed.
Index TermsICCAP, TCAD, VERILOG-A, BSIM4.
I. INTRODUCTION
The project has two parts. They are described as follows.
In the first part TCAD simulation of long channel
MOSFET is performed. Current is plotted for different biases
and different drain voltages under various conditions. In
addition to current, its first derivative and log of current is also
plotted for all the conditions. These plots are compared with
the given experimental data. Then the plots are matched with
the data by varying different BSIM4 parameters. It is to be
noted that different parameters affect the plot in different
region viz. sub threshold, linear and saturation region. The
process is that first the plot is matched for sub threshold region
then for linear and at the last for saturation region. The process
is repeated till all the plots i.e. plots of currents and their first
derivative are completely matched. Final values of parameters
are noted.
In the second part threshold voltage based MOSFET model
is implemented for drain current. The affects that are included
are mobility degradation and channel length modulation.
Current is plotted for gate as well as drain voltage. First
derivative is also plotted. Gummel Symmetry test is performed
for Id- Vds curve. Model is checked to converge for extreme
biases. In this part MOSFET is implemented using Verilog-A
codes.
a)
b)
c)
d)
VALUES
775.5E-3
0.5
13.8E-10
-2.4E-9
500E-3
-60E-3
4.207
-34.8E-6
435.5E-3
0.97
727.8E-9
18E3
-267.3E-3
-241E-6
22080
4.009
700E-6
0.0665E-3
03595E-3
5.861E-3
560.5E-12
15
0
0
1.85
0 Bulk Mobility
t ox Oxide thickness
Vt Threshold Voltage
B. Channel Length Modulation
Channel length decreases on increasing Vds. This results in
a finite output resistance which is ideally infinite. This
brings a slope in the otherwise constant Id-Vds curve. This
is incorporated by the following equation.
CLM 1 VDS
C. CONTINUITY
2nT ln 1 exp GS T
(2nt )
VGSTEFF
2t
(V V VOFF )
1 n
exp GS T
2nT
q s N A
T Thermal Voltage
N A Substrate Doping
VOFF Fitting Parameter
I DS W
VDSEFF
COX VGSTEFF 1 m
VDSEFF CLM
2 V
GSTEFF 2 kT / q
With this equation we plot Ids v/s Vgs and Ids v/s Vds, It is
found that plots are continuous up to second derivative. The
plots are shown below.
Id v/s Vgs
Id v/s Vds
The current does not pass the Gummel symmetry test. Drain
current is not symmetric for negative drain voltages. As seen
from the figure. Drain current does not show same behaviour
for positive and negative drain voltages. In fact , the behaviour
of drain current in the negative region is highly unpredictable
as beyond Vds= -10V current has positive values.
3.
4.
.
Fig 18
1.
2.
VII. REFERENCES
Navid Paydavosi et al BSIM4v4.8.8 MOSFET
MODEL USERS MANUAL U.S. Berkeley, 2013
:Verilog-AMS Language Reference Manual,
Ver 2.3.1. June,2009