www.ietdl.

org
Published in IET Power Electronics
Received on 6th February 2014
Revised on 9th August 2014
Accepted on 15th August 2014
doi: 10.1049/iet-pel.2014.0099

ISSN 1755-4535

Voltage compensator based on a direct matrix

converter without energy storage
Jose M. Lozano-Garcia1, Juan M. Ramirez2
1

Electrical Engineering Department, Universidad de Guanajuato, Carr. SalamancaV. de Santiago,

Comunidad de Palo Blanco, Salamanca, 36885, Guanajuato, Mxico
2
Electrical Engineering Department, Centro de Investigacin y de Estudios Avanzados del Instituto Politcnico Nacional
CINVESTAV, Unidad Guadalajara, Av. del Bosque 1145, Col. El Bajo, Zapopan 45019, Jalisco, Mxico
E-mail: jramirez@gdl.cinvestav.mx

Abstract: The objective of this study is to present a voltage compensator based on a matrix converter without energy storage,
which can cope with common power quality problems presented in power distribution systems. The proposed scheme
acquires from the grid the necessary energy during the disturbance, which eliminates the drawbacks imposed by the use of a
dc-link and the need of energy storage components. A matrix converter study under unbalanced input voltage conditions is
exposed, as well as a detailed explanation of the proposed modied direct space vector modulation (MDSVM). It has been
veried that even when the supply voltage exhibits unbalanced conditions and harmonic distortion, the control strategy does
not exhibit difculties to synthesise the compensation voltages, provided the restrictions imposed by the formulation are
fullled. Numerical simulations and experimental results from a laboratory scale prototype are presented to validate the
performance of the compensator.

Introduction

The actual technological advance achieved in the power

electronics area has allowed the optimisation of components
within the energy conditioning eld. The series
compensation device known as Dynamic Voltage Restorer
(DVR) was introduced for voltage sag mitigation, and has
been utilised to unify power converter topologies able to
inject compensation voltages into distribution feeders, in
order to protect sensitive loads from voltage disturbances.
Converters based on the utilisation of a dc-link are
considered a solution for DVR implementation. For example,
variants of conventional DVRs that have appeared in the
open research which include the use of a high frequency
transformer to reduce the size of reactive components [1],
devices with reduced energy storage elements [2], multilevel
topologies using ying capacitors [3], just to mention some.
All the aforementioned topologies use the dc-link.
Since the acac converters may adapt the energy provided
by an electrical source to the requirements of magnitude,
frequency, and phase that the load demands, some
researches have focused their efforts in utilising this
technology in energy compensation applications [412].
According to the operating principle, it is possible to
distinguish two major types of acac converters: (1) direct
acac converters, which perform the energy conversion in a
single stage; (2) indirect acac converters, which utilises an
intermediate dc-link. In the latter case, since conversion is
accomplished by the cascade connection of a rectier/
inverter, its performance will be limited to high commutation
IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332
doi: 10.1049/iet-pel.2014.0099

frequencies. On the other hand, direct acac converters may

be divided in three main categories: (i) AC-link converters;
(ii) Naturally Commutated Cycloconverters (NCC); (iii)
Direct acac matrix converters (MC), which are based on the
force-commutation principle. Among these devices, the direct
matrix converter exhibits several remarkable operational
characteristics as input current with low harmonic content,
controllable input power factor, eliminates the requirement of
an intermediate energy storage link, etc., aspects that make
this kind of technology quite attractive. However, restrictions
as the limited voltage ratio and the absence of the dc-link,
which implies input/output coupling, increase the difculty
to dene adequate control strategies [13].
Over the years some pulse width modulation (PWM)
techniques have been developed in order to control a matrix
converter. Originally, they were mainly concerned with the
output voltage control, neglecting the quality of the input
currents waveform, sometimes exhibiting high harmonic
contents. The real development of matrix converter
modulation starts in the 1980s, when Alesina and Venturini
introduced a high frequency PWM approach [14] enabling
better quality for both output voltages and input currents,
with a maximum voltage transfer ratio of 86.6%. Since
then, other concepts have been applied to matrix converter
control such as space vector modulation (SVM) [15]. The
SVM strategy offers the advantage of allowing a better
selection of the required voltage and current vectors,
simplifying control algorithms and providing maximum
voltage transfer ratio without the need to add third
harmonic modulator components. The matrix converter
321

& The Institution of Engineering and Technology 2015

www.ietdl.org

Fig. 1 Generation of the output line-to-line and input current reference vectors using SVM strategy
a Required states for tracking U out(ref ) within sector I
b Fixed vectors for current vector I in(ref ) tracking

performance under unbalanced supply and abnormal

conditions has been discussed in several investigations
[8, 1620]. The modulation strategy used in this paper,
named modied direct space vector modulation (MDSVM),
is different from that presented in [1618], where the
conversion process has been divided into two stages:
rectication and inversion. The proposed algorithm
implements the power conversion directly from ac-to-ac,
and it is capable to operate in adverse conditions at the
converter input terminals. In case of unbalanced and/or
distorted supply voltages, the algorithm modies the duty
cycles by incorporating the characteristics of the supply
voltages, adjusting the calculated values according to the
disturbances presented in the system voltages. It is
noteworthy that, because of the MDSVM adaptive nature,
there is no need to perform extra mathematical
transformations, as symmetrical components or Fourier, to
identify the type of disturbance and determine the required
duty cycles.
Once the drawback of input/output coupling in matrix
converters has been overcome entirely by the novel
modulation strategies, topologies which eliminate the,
usually bulky, dclink but retain dclinklike functional
capability represent an interesting alternative and several of
these have published. A family of acac topologies based
on the traditional matrix converter has been proposed for
DVR applications, connecting to the distribution feeder
either in series [21] or in shuntseries [22, 23]. In [24],
authors present a DVR based on a traditional back-to-back
full-bridge conguration with a ctitious dc link. Several
topologies based on the traditional matrix converter [21,
2528] have also been proposed for DVR applications.
Moreover, the interesting article by Prasai and Divan [29]
utilises a matrix converter with minimum energy storage.
Among these matrix converter architectures, topologies
based on the vector-switching matrix converter, or simply
vector-switching converter (VeSC) [30], appear particularly
attractive given their modularity, simplicity, and ease of
operation. Recent research has shown the hardware viability
of VeSC-based DVRs [23, 31], but it addresses only
balanced voltage sag conditions.
Owing to the direct matrix converter operative
characteristics, when it is controlled by the MDSVM, it is
possible its use for voltage compensation purposes, in
322
& The Institution of Engineering and Technology 2015

applications that involve unbalanced and harmonic

distortion in the supply voltage. Thereby, the main aim of
this paper is to exhibit the ability of the matrix converter to
generate unbalanced and distorted voltages to counteract the
system abnormal conditions. Simulation and experimental
results validate the analysis, and demonstrate the feasibility
of the proposed DVR topology.

Matrix converter modulation algorithm

In the formal SVM, a three-phase time variant set of signals is

mapped into a complex vector in terms of the - coordinates.
This modulation technique relies on the Park transformation
and the tracking of a reference vector. Through the
combination of the two adjacent vectors dening a sector,
plus a zero component, it is possible to synthesise the
required vector. When the input voltages applied to the
matrix converter are sinusoidal and balanced, the analysis
performed to the resulting space vectors shows that the
complex plane is divided into six sectors forming a regular
hexagon. The major aim of the SVM strategy is to control
the output line-to-line voltage vector and the phase angle
between the input voltage and input current vectors within
any sector, Fig. 1.
However, since conventional modulation strategies are
derived under the assumption of balanced conditions and
considering that in applications concerning voltage
compensation to generate controllable output voltages
becomes a compelling requirement, the development of a
general modulation strategy that encompasses typical
abnormal conditions is required.
2.1 Modied direct space vector modulation under
unbalanced conditions
For unbalanced cases, let considers a three phase voltage
system dened as follows

Vin sin(vt )



va (t)
k V sin vt 2p + u

1
3
V p = vb (t) = 1 in
(1)




vc (t)

4p
+ u2
k2 Vin sin vt
3
IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332
doi: 10.1049/iet-pel.2014.0099

www.ietdl.org
where coefcients k1 and k2 specify the degree of unbalance
in two of the input voltage magnitudes. Likewise, by
adding the angles 1 and 2, it is possible to include angles
different from 2/3 among phases. Under such conditions,
the line-to-line input voltages become
x V sin
vt b 
1
in
1
vab (t)

V l = vbc (t) = x2 Vin sin vt + b2


vca (t)
x V sin vt + b

current vectors are dened by [32]

U outl (t) = (vAB (t) + vBC (t) e j(2p/3) + vCA (t) e j(4p/3) )


(12)
= U outl  ej/U outl
I in (t) = (ia (t) + ib (t) ej(2p/3) + ic (t) e j(4p/3) )
 
= I in  e j/I in

in

(2)

where, xj and j ( j = 1,2,3) are functions of k1, k2, 1 and 2,

Appendix 1. The input voltage Park vector is dened by [33]
U inl (t) = (vab (t) + vbc (t) ej(2p/3) + vca (t) e j(4p/3) )


= U inl  e j/U inl

 


U  = 3 v2 (t) + v2 (t) + v (t) v (t)
inl
ab
bc
ab
bc

/U inl = tan

2vbc (t) + vab (t)

3vab (t)

(3)
(4)


(5)

Equations (3)(5) represent the input line-to-line voltage Park

vector, modulus and argument, respectively. It is worth noting
that for line-to-line voltages, the homopolar or zero
component is equal to zero.
Substituting (2) within (3)(5), all actual unbalanced
conditions can be taken into account, where the balanced
condition is a particular case. Similarly, the corresponding
input phase voltage Park vector and its zero component is
dened by [32]
U inp (t) = (va (t) + vb (t) ej(2p/3) + vc (t) ej(4p/3) )




= U inp  ej/U inp

(6)

Uinp0 (t) = (va (t) + vb (t) + vc (t))

(7)

With the purpose of setting up quantitative indexes among

arguments and modulus on Park vectors (U inp and U inl ),
expressions dened as a function of the same variables for
both vectors are required. Thus, the following relationships
arise
 



U
 inp  = v2ab (t) + v2bc (t) + vab (t) vbc (t)
/U inp = tan1


3vbc (t)
2vab (t) + vbc (t)

/U inl = /U inp +

p
6

Voltage reference tracking

Assuming that reference vectors U outl(ref ) and I in(ref ) are

located within sector I, Fig. 1, the following relations can
be stated, in order to determine the reference output
line-to-line voltage vector [3336]

 


I
II
U outl(ref ) = U outl mI + U outl mII

(14)


 


III
IV
U outl(ref ) = U outl mIII + U outl mIV

(15)

where mi represents the commutation vectors duty cycle, that

is,
mi =

(10)
(11)

Ti
i = {I, II, III, IV }
Ts

(16)

Ts is the sample time and Ti is the time elapsed while the ith
state is on. From Fig. 1 and [3336] the following
expressions may be deducted

 


I
II
U outl(ref ) = U outl mI + U outl mII

These two expressions can be satised independently of the

unbalance degree. The output line-to-line voltage and input
IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332
doi: 10.1049/iet-pel.2014.0099

2.2

U outl(ref )

Then,


 
U  = 3 U 
inl
inp

Expressions obtained for vectors U outl and I in , can be utilised

for both, balanced and unbalanced conditions. The
modications imposed by unbalanced or distorted
conditions on the input voltages are manifested on the
output xed vectors characteristics. In this case, xed
vectors still split the complex space in six sectors; however,
the maximum magnitude of each vector may be varying.
Such variations have to be considered at the moment of
synthesising the reference vectors, since modulus and
argument of reference vectors will depend on xed vectors
and consequently on the active states.

(8)

(9)

(13)



2 
p j(p/6)

e
= U outl(ref )  cos /U outl(ref )
3
3
(17)

 

III
IV
= U outl mIII + U outl mIV


2 
p j(p/6)

e
= U outl(ref )  cos /U outl(ref ) +
3
3
(18)

Each xed vector has three alternatives, Fig. 1, which

modulus varies instantly depending on the line-to-line input
voltages. One way to attain the vector U outl(ref ) is selecting
the commutation states that produce the largest modulus. As
a consequence, the selected commutation states depend on
the position of vector U inp and consequently on the input
line-to-line voltages according to (9), which also allows to
establish a relationship between the input line-to-line
323

& The Institution of Engineering and Technology 2015

www.ietdl.org
voltages and the sector where U inp is located, despite
unbalanced conditions.
Rearranging (17) and (18) in terms of the input line-to-line
voltage vector



p


U outl(ref )  cos /U outl(ref )
3








4p




= U inl cos /U inl mI U inl cos /U inl
mII
3
(19)



p


U outl(ref )  cos /U outl(ref ) +
3








4p




mIV
= U inl cos /U inl mIII U inl cos /U inl
3
(20)
2.3

Similarly, the input reference current I in(ref ) can be determined

by [3336]

II
I in

mII

I in(ref ) = I in mI



IV
+ I in mIV

(21)



III
+ I in mIII

(22)

After mathematical simplications, and in order to avoid the

use of current parameters [3336],
p

p

mII sin /I in(ref ) mI sin + /I in(ref ) = 0 (23)
6
6
p

p

mIV sin /I in(ref ) mIII sin + /I in(ref ) = 0
6
6
(24)
2.4

Duty cycles computation

Solving the equations set (19), (20) and (23), (24) [32], the
duty cycles become




U


outl(ref
)
2

mI = 
U inl 
3
p


p
cos + /I in(ref )
cos /U outl(ref )
3
3

cos uin




2 U outl(ref ) 

mII = 
U inl 
3
p


p
cos /I in(ref )
cos /U outl(ref )
3
3

cos uin

Vout

mIV





U


outl(ref
)
2

= 
U inl 
3

p

p
cos /I in(ref )
cos /U outl(ref ) +
3
3

cos uin

(27)

(28)

The last expressions are valid within the intervals

p
p
p
p
, /U outl(ref ) , , , /I in(ref ) ,
6
6
6
6

(29)

It is necessary to verify that

Current tracking

I in(ref )

mIII





2 U outl(ref ) 

= 
U inl 
3

p

p
cos + /I in(ref )
cos /U outl(ref ) +
3
3

cos uin

1
Vin
3 2

(25)

(26)

mI + mII + mIII + mIV 1

If the sum of duty cycles is less than one, the use of zero states
is required. Substituting (25)(28) into (30) results [32],
 3 





U inl 
U outl(ref ) 
2
cos /U

cos uin




cos
/I
outl(ref )
in(ref )
(31)

Considering

 that for each sector  it holds that
= 1 and cos /U outl(ref )
= 1, from (8),
cos /I in(ref )
max

max

the inputoutput voltage relationship q = (Vout /Vin ) can
be established (see (32))
in Appendix 1. From
where variables , l and j are specied

(32) it may be observed that U in  is a time variant quantity
which depends on the unbalance degree. Besides, it can be
noted that the maximum voltage relationship is reached
when cosin = 1. Then, (see (33) at the bottom of the page).
Equation (33) implies that under unbalanced conditions on
input voltages, the reference output voltage vector is at the
most 0.866 times the minimum value of the input voltage
Park vector. For example, during balanced conditions the
maximum balanced output voltage vector that may be
generated, corresponds to 0.866 times the maximum circle
that can be inscribed inside the hexagon, Fig. 2a. On the
other hand, if a sag of 50% takes place on input phase b,
the input vector describes an ellipse, thus reducing the
available locus for the output voltage generation. In this
particular case, the maximum magnitude of the balanced
output voltage that can be generated is reduced by a factor
of 2/3, Fig. 2b. The latter also can be applied in the case of
harmonic distortion present on input voltages, where, as
long as the output voltage vector magnitude remains below
the 86.6% of the input voltage vector magnitude at any
time, compensation can be achieved.



 

lg
2
2
2
g + l + g + l + w 2gl sin 2vt +
cos uin
w

324
& The Institution of Engineering and Technology 2015

(30)

(32)

IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332

doi: 10.1049/iet-pel.2014.0099

www.ietdl.org

Fig. 2 Comparison of the maximum balanced output voltages obtained under balanced and unbalanced conditions on input voltages
a Voltage vectors for balanced input voltage condition
b Voltage vectors for unbalanced condition (50% sag on phase-b)

Finally, taking into account a unitary input power factor,

the duty cycles become [32]





U outl(ref ) 
p
(vbc (t) vab (t))
mI = 
2 cos /U outl(ref )
3
U 
inl
(34)





U outl(ref ) 
p
mII = 
(vca (t) vbc (t))
2 cos /U outl(ref )
U 
3
inl

mIII

(35)





U outl(ref ) 
p
(vbc (t) vab (t))
= 
2 cos /U outl(ref ) +
U 
3
inl

mIV

(36)





U outl(ref ) 
p
(vca (t) vbc (t))
= 
2 cos /U outl(ref ) +
U 
3
inl
(37)

From the above expressions, the incorporation of the supply

voltages characteristics into the computation of the duty
cycles makes the modulation process adaptive to
disturbances at the input voltages. The relevance of this
strategy resides on the fact that it can prevent the
undesirable features of the supply voltages from
propagating onto the output voltages.
The main advantages of the proposed MDSVM technique
is that it allows: (i) fast and accurate generation of balanced,
unbalanced and distorted reference output voltages, despite
the input voltages condition; (ii) output voltages and input
currents with acceptable harmonic content; (iii) magnitude

Vout

1
Vin
3 2

and frequency control in output voltages; (iv) controllable

input power factor; (v) implementation with only two
line-to-line voltage measurements and without extra
mathematical transformations.

Matrix converter as voltage compensator

The operational benets of the MDSVM technique allows the

incorporation of the matrix converter technology into the
conventional DVR conguration. The system shown in
Fig. 3, is utilised to test the developed algorithm. The
proposed DVR topology is intended for compensating
balanced and unbalanced conditions, as well as harmonic
distortion in the voltage supply, with the purpose of
reducing operational complexity since energy storage
devices are not required. In this conguration, the energy
comes from the incoming supply. During voltage sags, the
matrix converter input voltage drops proportionally; hence,
the maximum injected voltage would become,




(38)
V inj  3/2 |a|
where V inj is the injected voltage vector in pu, and a is a
voltage sag factor dened as the ratio between the voltage
during the sag and the load rated voltage. For example, if
the supply voltage falls to 0.5 pu at rated load, the
maximum possible voltage, injected by the matrix
converter, will be 0.432 pu, which would be unsatisfactory.
Hence, the ability to compensate for symmetric voltage sags
would be, theoretically, limited up to 0.45 pu voltage drops.
3.1

Voltage controller

The control strategy used to test the proposed compensator

topology, as it was structured for implementation in an
eZdsp board, is displayed in Fig. 4. The primary control



 

l

g
g + l + g2 + l2 + w2 2gl sin 2vt +
w

IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332

doi: 10.1049/iet-pel.2014.0099

(33)
max

325

& The Institution of Engineering and Technology 2015

www.ietdl.org

Fig. 3 Topology of the voltage compensator based on a matrix converter.

structure is based on the combination of an open-loop supply

voltage feed-forward control and a closed-loop PI-based load
voltage feedback control. The feed-forward component
provides the required transient response at the beginning of
the disturbance. The closed-loop voltage feedback is added
to minimise any steady state error in the fundamental
component. The voltage compensator is synchronised to the
grid by a phase-locked loop (PLL). A relatively slow PLL
is used to limit the inuence of harmonics and
non-symmetrical input voltages. At the instant the
disturbance occurs, the difference between the voltage
reference and the measured voltage at the supply terminals

is utilised for the feed forward loop to determine the base

of the voltage to be injected. The actual load voltage is
compared with the rated load voltage and the error is fed to
a conventional PI-based voltage controller. Finally, outputs
from both main control branches are combined to generate
the signal references to the compensator, which are then
transformed into coordinates in order to implement the
MDSVM and compute the duty cycles. The injected
voltages must satisfy the MDSVM restriction




U out(ref ) 

MAX



3/2U 

inl MIN

(39)

Fig. 4 Control diagram for the voltage compensator

326
& The Institution of Engineering and Technology 2015

IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332

doi: 10.1049/iet-pel.2014.0099

www.ietdl.org
3.2

Simulations

Table 1 Parameters for simulation

Fig. 3 depicts the schematic of the matrix converter-based

DVR. A second order RLC lter is used at the input
terminals of the converter to improve the input currents
waveform. A second order RLC lter is utilised at the
output terminals of the matrix converter in order to lter the
switching harmonic components in the generated voltages.
The combined effect of the non-ideal ac source and the
three phase line is represented by the inductance Ls.
Dynamic performance of the whole system is veried by
numerical simulation using PSCAD/EMTDC. Table 1
summarises the system key parameters used for the
simulation.
The cut-off frequency of the lters can be obtained by
fo =

1

2p Lf Cf

(40)

Therefore, the cut-off frequencies are 1.073 and 0.464 kHz

for input and output lters, respectively; which are adequate
to improve the quality of the input currents and output
voltages, since the commutation frequency in the converter
is 6 kHz.
The matrix converter-based compensator is utilised for
voltage sags and swells compensation, as well as harmonics
suppression.
The state-space equations for the matrix converter-based
DVR system becomes [32]
dx
= f (x, u)
dt

(41)

where x and u are the state variables and inputs, respectively;

f(x, u) is the non-linear function vector dened in appendix
2. The state variables included are the input current, the
input lter, the output lter, and the RL load, in the d-q
reference frame.
In the rst simulation case, unbalanced voltage sag of 40%
is applied to input phase b, within the interval 0.4 s0.5 s, in
order to evaluate the compensator near its operational limit.

Cif: input filter capacitor

Lif: input filter inductor
Rif: input filter resistor
Cof: output filter capacitor
Lof: output filter inductor
Rof: output filter resistor
Rload: load resistor
Lload: load inductor
Vload: maximum load voltage
Iload: maximum load current

10 F
2.2 mH
50
4.7 F
25 mH
100
120
213 mH
113.13 V
0.7835 A

The Park vectors U inl and U outl on the complex plane are
displayed in Fig. 5 and Fig. 6a displays the input voltages
in time domain. In this case, voltage imbalance is exhibited
on both sets of terminals in the matrix converter.
Nonetheless, as long as the vector U outl remains inside the
vector U inl loci, the control algorithm will be able to
synthesise the output-voltage. Figs. 6 and 7 depict voltage
and current waveforms during the voltage sag period. Note
that the RL load acts as a low-pass lter, reducing almost
all the current harmonic components. Likewise, the matrix
converter generates a set of unbalanced voltages to achieve
the compensation, which provokes a distortion in the
currents drawn by the converter and consequently the
system currents are distorted as well, Fig. 7. The total
harmonic distortion (THD) of output voltages and system
currents during the disturbance are exhibited in Fig. 8. The
control algorithm has accomplished to reduce the
imbalanced percent from 15.38% at the input voltages to
0.42%, value which fulls the NEMA criterion about
permitted imbalance percent of 1. Besides, each output
phase voltage presents an average THD lower than 3%
during the fault, which falls inside the guidelines
established in the IEEE-519 for general power systems of
medium voltage.
Once evidenced the capacity of the proposed topology to
operate in a satisfactory way under unbalanced conditions,
its behavior was veried under the presence of harmonic
components on the input voltage (results are omitted for the
sake of brevity) [32].

Fig. 5 Park vectors U inl and U outl on the complex plane

a Input and Output line-to-line voltage vectors in complex space
b Line-to-line voltage vectors magnitude.
IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332
doi: 10.1049/iet-pel.2014.0099

327

& The Institution of Engineering and Technology 2015

www.ietdl.org

Fig. 6 Simulation results: Compensator response under unbalanced voltage variation

From top to bottom
a Supply voltages
b Compensation voltages
c Load voltages

Fig. 7 Simulation results: Compensator response under unbalanced voltage variation

From top to bottom
a Load currents
b Phase a matrix converter input current
c Phase a supply system current
328
& The Institution of Engineering and Technology 2015

IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332

doi: 10.1049/iet-pel.2014.0099

www.ietdl.org

Fig. 8 Simulation results

a Load voltages THD
b System supply currents THD

3.3

Experimental results

A laboratory-scale prototype has been assembled using

IGBTs in the common collector conguration. The control

algorithm has been implemented using the xed-point DSP

TMS320F2812. Voltage sag correction and harmonic
suppression are veried by means of several experimental
tests.

Fig. 9 Experimental results: Supply and load voltages during unbalanced voltage sag test
a Pre-sag condition
b Sag condition (20 V/div, 5 ms/div)
c Pre-sag condition
d Sag condition (20 V/div, 10 ms/div)
IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332
doi: 10.1049/iet-pel.2014.0099

329

& The Institution of Engineering and Technology 2015

www.ietdl.org

Fig. 10 Experimental results: Supply voltages (top) and load currents (bottom) during the distorted voltage test
a Without compensation
b With compensation (20 V/div, 5 ms/div)
c Without compensation
d With compensation (0.5 A/div, 5 ms/div)

Load voltage and current presented in Fig. 9 exhibits the

compensator performance for an unbalanced case, where a
37.5% voltage sag is applied to phase-a. Similarly to the
simulated waveforms, the load voltages are fully
maintained, which demonstrate the effectiveness of the
matrix converter as compensator. The distortion on the load
voltages is partly because of the inductors saturation used in
both lters, input and output, Fig. 3, because low frequency
inductors were used. Besides, an important factor to
consider is the modulation index. Before the sag takes
place, a very low modulation index is being used; then, the
distortion is more notable during the pre-sag condition.
During the disturbance, currents on the supply system are
distorted as expected, but the load currents remain almost
invariant.
The following study involves harmonic distortion in the
supply voltages, because of a non-linear load, a diode
bridge rectier plus a resistive load. After the compensation
takes place, the fth and seventh harmonic components are
reduced by a factor of 20 and 15 dB, respectively; thus,
THD is reduced too. Fig. 10 displays voltages and currents
with and without compensation. Note, under compensation,
that the load voltages include some high order harmonic
components, which may be generated by the saturation of
the output lter inductors. Nevertheless, the effects of these
harmonics may be tolerable for the load.
330
& The Institution of Engineering and Technology 2015

Conclusions

This paper proposes a novel voltage compensator topology

using a direct matrix converter without energy storage, to
cope with power quality issues presented in distribution
systems. The main contributions of this paper are
summarised in the following:
The mathematical development of the MDSVM technique
to control the matrix converter operation. A detailed analysis
of the acac matrix converter under unbalanced conditions is
presented. The proposed technique allows the converter to
generate a totally controllable output voltage despite the
adverse existing conditions in the input voltages.
The design of a novel multi-functional DVR topology,
proposed to improve the power quality in distribution
systems.
Development of a detailed model of the DVR topology in
order to evaluate their dynamic behavior through
time-domain PSCAD/EMTDC simulations.
Development of mathematical models for the DVR
topology intended for future stability and power ow
control analysis.
Design and implementation of a laboratory-scale prototype
of the matrix converter-based DVR to validate the MDSVM
technique operation, which was implemented in a
IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332
doi: 10.1049/iet-pel.2014.0099

www.ietdl.org
DSP-based board eZdsp-TMS320F2812, along with a four
step commutation strategy.
The incorporation of matrix converter technology into
the conventional DVR conguration may result in a
cost-effective and multi-functional solution. Simulated and
experimental results presented show the feasibility of the
proposed topology. This analysis may be useful to study the
use of the matrix converter in future applications.

Acknowledgment

This work was supported by PROMEP under 103.5/13/7048

project.

References

1 Goharrizi, A., Hosseini, S., Sabahi, M., Gharehpetian, G.: Three phase
HFLDVR with independently controlled phases, IEEE Trans. Power
Electron., 2012, 27, (4), pp. 17061718
2 Al-Hadidi, H., Gole, A., Jacobson, D.: A novel conguration for a
cascade inverterbased dynamic voltage restorer with reduced energy
storage requirements, IEEE Trans. Power Deliv., 2008, 2, (23),
pp. 881888
3 Roncero-Sanchez, P., Acha, E.: Dynamic voltage restorer based on
ying capacitor multilevel converters operated by repetitive control,
IEEE Trans. Power Deliv., 2009, 24, (2), pp. 951960
4 Liu, S., Ge1, B., You, X., et al.: A novel quasi-Z-source indirect matrix
converter, Int. J. Circuit Theory Appl., 2013, Published online in Wiley
Online Library (wileyonlinelibrary.com). DOI: 10.1002/cta.1952
5 Karaca, H., Akkaya, R.: Modeling, simulation and analysis of matrix
converter using matlab and simulink, Int. J. Model. Optim., 2012, 2,
(3), pp. 328332
6 Szczesniak, P.: Three-phase AC-AC power converters based on matrix
converter topology (Springer, 2013), ISBN 978-1-4471-4896-8
7 Abdel-Rahima, O., Abu-Ruba, H., Kouzouc, A.: Nine-to-three phase
direct matrix converter with model predictive control for wind
generation system, Energy Procedia, 2013, 42, pp. 173182
8 Kumar, V., Chand Bansal, R., Raj Joshi, R.: Experimental realization of
matrix converter based induction motor drive under various abnormal
voltage conditions, Int. J. Control, Autom. Syst., 2008, 6, (5),
pp. 670676
9 Kwak, S.: Structures and modulation algorithms of direct ac/ac
converters with two legs and three legs for two-phase systems, Eur.
Trans. Electr. Power, 2010, 20, (4), pp. 422437
10 Zanchetta, P., Wheeler, P., Empringham, L., Clare, J.: Design control
and implementation of a three-phase utility power supply based on the
matrix converter, IET Power Electron., 2009, 2, (2), pp. 156162
11 Rosas-Caro, J.C., Mancilla-David, F., Ramirez-Arredondo, J.M., Bakir,
A.M.: Two-switch three-phase ac-link dynamic voltage restorer, IET
Power Electron., 2012, 5, (9), pp. 17541763
12 Rajendran, S., Govindarajan, U., Parvathi Sankar, D.S.: Active and
reactive power regulation in grid connected wind energy systems with
permanent magnet synchronous generator and matrix converter, IET
Power Electron., 2013, 6, (5), pp. 591603
13 Pinto, S., Silva, J.: Sliding mode direct control of matrix converters,
IET Electr. Power Appl., 2007, 1, (3), pp. 439448
14 Alesina, A., Venturini, M.: Solid-state power conversion: a Fourier
analysis approach to generalized transformer synthesis, IEEE Trans.
Circuits Syst., CAS, 1981, 28, (4), pp. 319330
15 Casadei, D., Serra, G., Tani, A., Zarri, L.: Matrix converter modulation
strategies: A new general approach based on space-vector representation
of the switch state, IEEE Trans. Ind. Electron., 2002, 49, pp. 370381
16 Saribulut, L., Tmay, M.: Robust space vector modulation technique
for unbalance voltage disturbances, Electr. Power Syst. Res., 2010,
80, pp. 13641374
17 Jahangiri, A., Radan, A., Haghshenas, M.: Synchronous control of
indirect matrix converter for three phase power conditioner, Electric
Power Syst. Res., 2010, 80, pp. 857868
18 Kumar, V., Joshi, R.R.: DSP-Based matrix converter operations under
various abnormal conditions with practicality. Proc. Int. Conf., New
Delhi, December 2006, pp. 14
19 Rivera, M., Rojas, C., Rodriguez, J., Espinoza, J.: Methods of source
current reference generation for predictive control in a direct matrix
converter, IET Power Electron., 2013, 6, (5), pp. 894901
IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332
doi: 10.1049/iet-pel.2014.0099

20 Blaabjerg, F., Casadei, D., Klumpner, C., Matteini, M.: Comparison of

two current modulation strategies for matrix converter under unbalanced
input voltage conditions, IEEE Trans. Ind. Electron., 2002, 49,
pp. 289296
21 Wang, B., Venkataramanan, G.: Dynamic voltage restorer utilizing a
matrix converter and ywheel energy storage, IEEE Trans. Ind.
Appl., 2009, 45, (1), pp. 222231
22 Lozano, J., Ramirez, J.M., Correa, R.: A novel dynamic voltage restorer
based on matrix converters. Proc. IEEE Mod. Electric Power System
MEPS, Wroclaw, Poland, September 2010, pp. 17
23 Ramirez, J.M., Garcia-Vite, P., Lozano, J.M., Mancilla-David, F.:
Dynamic voltage restorers based on ac-ac topologies. Proc. IEEE
Power and Energy Society General Meeting, July 2012, pp. 17
24 Babaei, E., Kangarlu, M.F.: Voltage quality improvement by a dynamic
voltage restorer based on a direct three-phase converter with ctitious dc
link, IET Gen., Transm., Distrib., 2011, 5, (8), pp. 814823
25 Subramanian, S., Mishra, M.: Interphase ACAC topology for voltage
sag supporter, IEEE Trans. Power Electron., 2010, 25, (2), pp. 514518
26 Babaei, E., Kangarlu, M.: A new topology for dynamic voltage
restorers without DC link. Proc. IEEE ISIEA, October 2009, (2),
pp. 10161021
27 Abardeh, M., Ghazi, R.: A new conguration for dynamic voltage
restorer based-on matrix converter. Proc. 45th Int. UPEC, August/
September 2010, pp. 16
28 Perez, J., Cardenas, V., Moran, L., Nunez, C.: Single-phase ACAC
converter operating as a dynamic voltage restorer (DVR). Proc. IEEE
IECON, November 2006, pp. 19381943
29 Prasai, A., Divan, D.: Zero-energy sag corrector with reduced device
count, IEEE Trans. Power Electron., 2009, 24, (6), pp. 16461653
30 Venkataramanan, G.: Three-phase vector switching converters for
power ow control, Proc. Inst. Elect. Eng.Elect. Power Appl.,
2004, 151, (3), pp. 321333
31 Garcia-Vite, P., Mancilla-David, F., Ramirez, J.M.: Per-sequence vector
switching matrix converter modules for voltage regulation, IEEE Trans.
Ind. Electron., 2013, 60, (12), pp. 54115421
32 Lozano, J.M.: DVRs Topologies matrix converter-based for improving
power quality in distribution systems. Ph. D. Dissertation,
CINVESTAV del IPN, 2011, available: https://www.dropbox.com/s/
xnisvbq9k7yup8e/Tesis%20Doctorado%20JMLG.pdf
33 Friedli, T., Kolar, J.W.: Milestones in Matrix converter research, IEEJ
J. Ind. Appl., 2012, 1, (1), pp. 214
34 Rodriguez, J., Rivera, M., Kolar, J.W., Wheeler, P.W.: A review of
control and modulation methods for matrix converters, IEEE Trans.
Ind. Electron., 2012, 59, (1), pp. 5870
35 Wheeler, P.W., Rodriguez, J., Clare, J.C., Empringham, L., Weinstein,
A.: Matrix converters: a technology review, IEEE Trans. Ind.
Electron., 2002, 49, (2), pp. 276288
36 Ghoni, R., Abdalla, A.N., Koh, S.P., Rashag, H.F., Razali, R.: Issues of
matrix converters: Technical review, Int. J. Phys. Sci., 2011, 6, (15),
pp. 35763588

Appendix 1


p
1 + k12 2k1 sin u1
6


p
x2 = k12 + k22 2k1 k2 sin u1 u2
6



5p
x3 = 1 + k22 2k2 sin u2
6
x1 =

 
k
cos
u
+
(5
p
/6)
1
2


b1 = tan1
1 k1 sin u1 (p/6)



1 k1 cos u2 + (5p/6) k2 cos u2 + (p/6)


b2 = tan
k1 sin u1 (p/6) k2 sin u2 (5p/6)


 
k2 cos u2 + (p/6)
1


b3 = tan
k2 sin u2 (5p/6) 1
331

& The Institution of Engineering and Technology 2015

www.ietdl.org




2p
g = x1 cos b1 + x2 k1 cos b2 cos u1
3




2p
+ x3 k2 cos b3 cos u2 +
3






2p
2p
+ x3 k2 sin b3 sin u2 +
l = x2 k1 sin b2 sin u1
3
3




2p
w = x1 sin b1 + x2 k1 sin b2 + u1
3


2p
+ x3 k2 sin b3 + u2 +
3

Appendix 2

f(x, u) = [ f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12]T



1
vds Rif ids idif idload vdi
Ls



1
= vids +
vqs Rif iqs iqif iqload vqi
Ls

R

= viqif + if ids idif idload

Lif

R 
= vidif + if iqs iqif iqload
Lif
1 
= vvqi +
i idload
Cif ds
 

vdinj
v
V
di2 vdo idof + in vdo
Ui Rof
Rof
Ui

f1 = viqs +
f2
f3
f4
f5

332
& The Institution of Engineering and Technology 2015

f6

f7
f8
f9
f10
f11

f12



vqinj
V
+vqo iqof + in vqo
Ui Rof
Rof

vqi
1
= vvdi +
iqs iqload 2
Cif
Ui
 

vqinj
Vin

v
vqo iqof +
Ui Rof qo Rof


vdinj
V
+vdo idof + in vdo
Ui Rof
Rof


vdinj
1 Vin
= viqof +
vdo
Lof
Lof Ui


vqinj
1 Vin

= vidof +
v
Lof
Lof Ui qo


vdinj
i
1
Vin
i
= viqinj + dof +
vdo
dload
Cof Rof Cof Ui
Rof Cof
Cof


iqof
vqinj
iqload
1
Vin
= v idinj +
+
vqo

Cof Rof Cof Ui

Rof Cof
Cof

R

= v iqload + if ids idif idload

Lload

1 
R + Rload
vdi + vdinj idload if
+
Lload
Lload


R
= vidload + if iqs iqif iqload
Lload


1
R + Rload
vqi + vqinj iqload if
+
Lload
Lload

IET Power Electron., 2015, Vol. 8, Iss. 3, pp. 321332

doi: 10.1049/iet-pel.2014.0099