Mobile Robot chapter 2: Fundamentals of a microprocessor based system (v.

4b)

Chapter 2:
Fundamentals of a
microprocessor based
system
Objectives
z
Learn about the basic structure of microprocessor systems
z
Learn about the memory read/write timing diagrams.
z
Learn about address decoding techniques

2.1

Introduction
In this chapter we will study the basic architecture of a computer system. In particular we
will discuss the relation of the memory devices and the microprocessor device.
We will first discuss the basic structure of a microprocessor system. Then we will discuss
different memory devices and their usage. Memory read/write cycles and the concept of
timing and address decoding methods will be introduced.

2.2

Basic structure of a microprocessor system

In general, a computer system contains the following parts:
z

Microprocessor (80x86 or 8051 etc)

Memory (Read only memory ROM , Random Access Memory RAM etc)

Input/output and peripheral devices

Glue logic to put the above components together

Clock
Oscillator

MicroProcessor

memory

Peripheral
devices:
serial,
parallel
Peripheral
devices:
serial,
parallel
interfaces;
etc.etc.
interfaces;real-time-clock
real-time-clock

Figure 1: A
computer
system with a
microprocessor

Mobile Robot chapter 2: Fundamentals of a microprocessor based system (v.4b)

2.3

Different kinds of Memory

Figure 2: an ancient memory device.

2.3.1 Random access memory (RAM): data will disappear after power
down.
There are two types of Random access memory (RAM)
z

Dynamic RAM (DRAM) low cost, slower: Each bit is a small capacitor; one or
zero is memorized by whether it is charge or discharged respectively. However, a
charged bit will become discharged because of leakage so it has to be recharged
regularly, say in every few ms (called refresh cycles). It is low cost so it is suitable for
making the main memory of a computer, but it requires a more complex circuit to
handle the refresh. And because of this reason we will not use it in our experiments.
There are also two major types of DRAM:

Synchronous Dynamic SDRAM [6], Double Data Rate Synchronous Dynamic

SDRAM (DDR SDRAM) [7].

EDO asynchronous DRAM (becoming obsolete).

Static RAM (SRAM)high cost, faster: each bit is a flip-flop, so it is more expensive
but easier to use than dynamic RAM because it is not required to be refreshed regularly.
Because of its high speed rate, it is usually used for building cache memory for
computer mother boards.
Since we only discuss static (SRAM) here, so the terms SRAM and RAM will be used
interchangeably.

2.3.2 Read only memory (ROM)

As the name indicates, it is a read-only device. But, what is the procedure to write
data/program to the device? One way is to ask the supplier to do it for you if you are
ordering a large batch. Otherwise there is a program-once type that you can program it by
using a PROM-programmer. But remember only once, you cannot change it afterwards.
It is suitable to be used in a product line for large-scale production.

Mobile Robot chapter 2: Fundamentals of a microprocessor based system (v.4b)

2.3.3 UV-EPROM
Also known as EPROM, it is Ultra-Violent (UV) light erasable and re-programmable
using a programmer. It is suitable for product development and experimentation, because
you can change the program many times (well over 10,000 times) by UV-light erasing
and re-programming. (Not that the natural sunlight will take 2 years to erase a chip).

Figure 3: Erase information in UV-EPROM by UV light

2.3.4 EEPROM
Electrical erasable memory, similar to a RAM but the write time is much longer so it is
not suitable to be used as the main memory of a computer. It also supports the byte-tobyte erase mode.

2.3.5 FLASH ROM

Similar to EEPROM but does not support the byte-to-byte erase mode. You must ease all
memory or a block at one time. It is used widely for storing BIOS system start-up
programs of computers, so that the computer is able to support online upgrading of
system software. It is also widely used for storing media (picture and sound) files for
portable audio/visual appliances.

A Sony memory stick card (flash memory)

from :http://www.world.sony.com/Electronics/MS/universe/index.html

2.4

Memory and memory interface and their timing diagrams

Diagram are taken from the data sheet of a 32K-byte Static RAM (SRAM) device
76C256 http://www.skt.co.kr/gm76c256clcll.pdf

2.4.1 Memory static ram (SRAM) pin assignments.

In the following example we will use the static RAM (or SRAM) 62256 or 76c256
for our illustration. This SRAM has 28 pins with 15 bits address (A0-A14), 8 data
bits (D7-D0) and three input signals for read/write control:

/CS = chip-select (or called /CE=Chip enable),

Mobile Robot chapter 2: Fundamentals of a microprocessor based system (v.4b)

/OE = output enable,

/WE = write enable.

Address and data: The address has 15 address bits, A0-A14, therefore this RAM
has 152 = 32K of address or locations. The address range is from 0000H to
7FFFH. And since each address has 8-bit of data, so the total memory size is
32K-byte.

Here is a way to interpret the concept of address and data. A memory device is
just like a high-rise building with many floors; each floor has a unique address
pointed by a 15-bit address. And each flat has 8 rooms, each room can contain a
bit 1 or 0. Now if you want to post a letter containing a code of 12H to the
flat of address 7ACDH, You need to write down the address (on the address bus)
and then give the letter containing the code 12H (through the data bus) to the
postman. Then after some processing (by the control signals /WR, /OE, /CE) the
code 12H will be stored in the building at flat 7ACDH. The following is diagram
showing the high building containing the data.
Address

Data
(8 bits)

7FFF H

35H

7FFE H

23H

7ACD H

12H

0001 H

32H

0000H

82H

The read/write convention. Remember that the central processor (CPU) is always
the subject of our discussion so memory read means data is read from RAM to the
CPU; similarly memory write means data is written from CPU to the RAM.
Memory read/write are done by a set of control signals synchronized with the address
and data bits, to understand this we must study the timing diagrams of the read/write
operation.

2.4.2 CPU and Static memory (SRAM) interface and timing

For a simplified case, the CPU has 16 address line outputs, 8-bit of bi-directional data,
two control output signals /WR and RD. It fits nicely with the SRAM that the
corresponding lines are connected together. The discussion below is based on the
example we used earlier that we want to read data from an address location of 7ACDH
and write a data of 12H into that location.

2.4.2.1 The memory read (read data from SRAM to the CPU) cycle
The operation, as depicted in figure 2, is as follows:
When the CPU executes an instruction that requires reading in a data from the RAM, it
first sends out the address to the RAM, in this case, say, 7ACDH. It is shown in the
timing diagram read cycle 2 of figure 2. At the beginning of the read cycle the address
lines become stable. You would see some lines are high some lines are low because it is
a bus and contains 15 lines, when they overlap they become a timing diagram like this.

Mobile Robot chapter 2: Fundamentals of a microprocessor based system (v.4b)

I.

A15 is connected to /CS (chip select) of the SRAM chip, so at the beginning of
the read cycle (T0), if the address is within 0000-7FFFH, A15 should be low, then
the SRAM is enabled.

II.

The output /RD of the CPU is connected to /OE (=output enable) of the SRAM. A
little while after T0, /RD will be pulled down by the CPU. When the memory
SRAM receives the following signals: (i) valid address, (ii) /CS is low, (iii) /OE
is low and /WE is high, data pointed by the address will be sent out to the data bus
at time T1.

III.

Data is valid at T1, then at T2 the CPU sets /CS, /OE to high, then data is latched
into the CPU. This completes the read operation. From T0 to T2 it is called a
memory read cycle.

IV.

You can see that the whole operation is a deliberate design required the
cooperation of the CPU and SRAM at precise timing. However, you dont have to
worry much, in most cases once you connect the correct wires together as in the
diagram below, the system will function as required. But you to make sure that the
access time of the memory (TACS) must be shorter than the required cycle time
(TCYC) of the CPU. Otherwise the CPU cannot read the correct data from the
memory.

A simplified connection diagram between CPU and the SRAM.

A0-A14

A0-A14

32K-byte
SRAM

CPU

/CS
/OE
/WE

A15
/RD
/WR
Bi-directional Data bus

T0

T1

Figure 4

T2

Memory write cycle (write data from CPU to SRAM)

The memory write cycle is quite similar to the read cycle.

I.

First memory address is first output from the CPU to the address
bus bus
at .
8-bit data

Figure 5
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Mobile Robot chapter 2: Fundamentals of a microprocessor based system (v.4b)

2.4.2.2 Memory write cycle (write data from CPU to SRAM)

The memory write cycle, as depicted in figure 3, is quite similar to the read cycle.
I.

First memory address is output from the CPU to the address bus at T0.

II.

A15 is low since the address (7ACDH) is within the memory range 0000-7FFFH.
So the signal /CS of the memory SRAM is now low.

III.

A while after T0 when the address bus is stable, /WE of the CPU is reset to low and
also data (12H) from the CPU becomes valid.

The /WR is set by the CPU to high, then the data is latched into the memory. The memory
write cycle is completed here.

T0 T1

T3

T4

Figure 6
Exercise2.1: Redesign the CPU/SRAM interfaces circuit in figure 1 so that
the address-range is 8000-FFFFH instead of 0000-7FFFH.
Exercise2.2: Redesign the CPU/SRAM interface circuit to add another
SRAM to enable the system to have the whole 0000-FFFFH address-range.

2.5

About Timing Diagrams

Timing diagrams are extremely important in hardware design. Here are the important points.
1.

When you are reading a bus:

A pair of horizontal lines (one high, one low) means you are in the valid region.
Why does it have two lines? Because you are now looking at a bus with all the
signals, which are merged or compressed. Therefore you see some high and low
signals packed together at the same time.
A14A0

Valid region

Mobile Robot chapter 2: Fundamentals of a microprocessor based system (v.4b)

Before entering a valid region, you find arrows there (at DOUT of figure 2). It is
because it is a place where transitions of the signals or the bus occur, try not to
use the signal at that time since the signal is not stable and not valid. Such an
invalid region also occurs when a signal changes from one valid region to

another valid region, for example, when the signals change from 55H to AAH,
etc.

In the above diagram, the shaded region at the left-hand side means a region
when high-to-low can be allowed or can happen at any time within this region.
The middle-region is a stable-low region. And the shaded region on the righthand side means low-to-high can occur or is allowed to occur anytime within
this region.

T0

T1

T2

In the above diagram, the horizontal line in the middle means the signal is at the
high-Z (float) region. Then at T0, the signal can become valid at any time within
this region. At T1 the signal must be valid. And after T2 the signal becomes
High-Z (float) again.

Exercise2.3 Explain the above timing diagrams.

2.6

Read only memory ROM devices

Since ROM is read only there is no need to have the /WE pin input. Otherwise the timing
operation are quite similar to that of the memory read cycle of an SRAM. The 27256
(32K-byte ROM) is also pin compatible to 62256 (32K-byrte SRAM), yet there is no pin
for /WR since there is no simple write operation allowed. A special machine called
PROM-programmer is used to write data into a ROM. It uses a very different timing
method. Interested students can read the data sheet of ROM for details.

2.7

Memory decode
In the above example the CPU has an address range of 64K, so two 32K-byte SRAM
devices fit nicely into the address map and it uses A15 to indicate which SRAM is in use.
But how about if we have a CPU which supports 128K-byte (has address pin A0-A16 =
17 pins, so 217=128K) of memory area.

Mobile Robot chapter 2: Fundamentals of a microprocessor based system (v.4b)

Exercise2.4: How many 32K-SRAMs do we need?

Answer: 128/32= 4 SRAM devices.
Exercise2.5: How to connect the SRAMS to the CPU? We need an address
decoder to enable each SRAM when it is in use.
Since the lower 15 address pins will be used for connecting the SRAM address inputs.
We will use the upper 17-15=2 pins (A16, A15) to connect to an address decoder.
The general rules are:

1.

Use the upper address lines for address decode (e.g. A16,A15 here);

2.

Connect the lower address lines (depending on the address pins in each
memory unit, e.g. A14-A0 here) in parallel for all memory devices.

For 128K bytes we need 5 hex numbers = 17 bits to represent it, x = dont care
A16,A15,..A0 (17 bits)

Address range( 5 hex.)

Range size

0 0xxx xxxx xxxx xxxx

0 0000 - 0 7FFF H

32K

0 1xxx xxxx xxxx xxxx

0 8000 - 0 FFFFH

32K

1 0xxx xxxx xxxx xxxx

1 0000 - 1 7FFFH

32K

1 1xxx xxxx xxxx xxxx

1 8000 - 1 FFFFH

32K

A decoder is a logic circuit, which has the following truth table

A16 ,A15

/CS0

/CS1

/CS2

/CS3

00

01

10

11

A set of simple Boolean functions is:

/CS0 = A16 or A15 (for address range: 0 0000 07FFFH)
/CS1 = /A16 or A15 (for address range: 0 8000 0 FFFFH)
/CS2 = A16 or /A15 (for address range: 1 0000 1 7FFFH)
/CS3 = /A16 or /A15 (for address range: 1 8000 1 FFFFH)

CPU A16
A15

Address
decoder

/CS0
/CS1
/CS2
/CS3

32K-byte RAM
/CE (or /CS)
(0000007FFFH)

32K-byteRAM
/CE (or /CS)
How to connect
Data bus (D7-D0), /WR, /OE
/CS2, /CS3 to the other two
SRAM chips?
8

(080000FFFFH

Mobile Robot chapter 2: Fundamentals of a microprocessor based system (v.4b)

Exercise2.6: Complete the above diagram and show (a) How to connect the
other two SRAM devices to /CS2, /CS3 and show their address ranges? (b)
How to connect the other address pins (A0-A14)?
Exercise2.7: Use the Internet to search for the data sheet of 74-138 or 54138(1-of-8 Decoder) and learn how to use it to make an address decoder for
circuit development.

2.8

Other interfacing methods

2.8.1 Serial memory devices reduction of hardware pins
Many flash memory devices are working in the serial interface mode, the main difference
is that each device uses a single IO bit for data exchange and usual coordinated by a clock
signal. The advantage is the pin count is low, (E.g. 6 pins for the whole device). Typical
examples are the SD, MMC flash memory devices used in MP3 players and digital
cameras [4], or the serial EEPROM [5].

2.8.2 Synchronous and asynchronous accessing methods

The above accessing read/write cycles are in asynchronous mode, for example, in a
memory read cycle the CPU can initiate a read request then the memory will supply the
data when it is ready. The two parties are loosely linked by an asynchronous relation. In
synchronous mode, the memory and the CPU are performing read/write operations
according to a master clock, hence the control is tighter hence the speed can be increased.
Synchronous memory can usually support burst mode. That is after the initial read/write
cycle requiring a few clock cycles, a block of memory (say, 8 locations) can be
transferred at an one-clock-cycle-per-location rate [1].

2.8.3 Double rate technology for synchronous access

Data transfer can occur at the rising as well as falling edge, so in each cycle of the clock,
data is transferred twice [7].

2.9

Questions
1.

List the types (in, out or inout) and functions of

address lines

data lines

/CS,/OE and /WE lines

of a static memory device.

2.

Referring to figure 1 and 2, what would happen if /RD of the CPU goes up before
the data valid region occurs?

3.

Referring to Figure 3, if tAS=0ns, twc=100ns,tCW=80ns, give comments on the limits

of tAW, tWP and tDW..

4.

For a CPU with 20-bit addressing space and 8-bit data lines,

What is the size of the addressing space?

How many 32-K byte SRAM do you need to fill up the address space.

Design an address decoder for this system.

Mobile Robot chapter 2: Fundamentals of a microprocessor based system (v.4b)

5.

6.

For a CPU with 32-bit addressing space, each location is referring to a byte, the
CPU has 32-bit data lines,

What is the size of the addressing space?

Discuss how do you access a byte, 2 bytes or 4 bytes using one memory
read/write cycle.

How many 32-Mbit DRAM do you need to fill up the address space of 64Mbyte?

Design an address decoder for this system.

Write essays on the following topics:

z

The main system memory technologies to be used in motherboards next year.

The main memory technologies to be used in digital cameras next year

Memory technologies come and go, why do we need to study all of them?

References
1.
2.
3.
4.
5.
6.

7.

System Memory: http://www.pcguide.com/ref/ram/tech.htm (Many technical terms on memory

are explained here)
Datasheet of a 320Kbyte Static Ram (SRAM) device 76C256
http://www.idt.com/docs/71V256SA_DS_18599.pdf
Data sheets for EPROMs., MCUs: http://batronix.com/electronic/datasheets/eeprom.shtml
Data manual for SD
http://www.sandisk.com/download/Product%20Manuals/Product%20ManualSDCardv1.7.pdf
Data sheet of serial EEPROM
http://www.hvwtech.com/downloads/datasheets/24lc16b_MCHIP.pdf
Synchronous Dynamic RAM -- SDRAM datasheet
http://www.samsung.com/Products/Semiconductor/common/product_list.aspx?family_cd=DRM
030104
Double Data Rate SDRAM (DDR SDRAM) datasheet
http://www.samsung.com/Products/Semiconductor/DRAM/DDRSDRAM/DDRSDRAMcompon
ent/256Mbit/K4H560838E/K4H560838E.htm
-- End of this chapter --

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