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INTERFACING
TECHNIQUES
AUSTIN LESEA
SYBEX
to
en
RODNAYZAKS
MCMXCVn
MICROPROCESSOR
INTERFACING
TECHNIQUES
AUSTIN -LESEA
RODNAY ZAKS
SYBEX
Published by:
SYBEX
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information.
However, Sybex assumes no responsibility for its use;
nor any infringements of patents or other rights of third parties which
would result. No license is granted by the equipment manufacturers
under any patent or patent rights. Manufacturers reserve the right to
change circuitry at any time without notice.
In particular,
Copyright
1977 SYBEX Inc. World Rights reserved. No part
of this publication may be stored in a retrieval system, copied,
transmitted, or reproduced in any way, including, but not limited to,
photocopy, photography, magnetic or other recording, without the prior
written permission of the publisher.
Q)
Number: 77-20627
ISBN Number: 0-89588-000-8
Library of Congress Card
CONTENTS
PREFACE
L
.5
INTRODUCTION
Concepts,
Details
II.
III.
6800,
BASIC INPUT-OUTPUT.
Parallel, Serial
IV.
The
17
45
85
191
The
VI
BUS STANDARDS
Parallel:
Serial:
215
TABLE OF CONTENTS
CASE-STUDY: A 32-CHANNEL MULTIPLEXER
VII
Introduction,
Specifications,
Architecture,
USART Module,
.259
Software,
DIGITAL TROUBLE-SHOOTING
Vni
CPU
281
IX
APPENDIX A
Plastic
317
Software
319
Manufacturers
APPENDIX B
SI 00 Manufacturers
INDEX
321
PREFACE
Computer interfacing has traditionally been an art, the art to design and
implement the required control electronics for connecting a variety of
peripherals to the main processor.
With the advent of microprocessors* and of LSI chips, since 1976, microprocessor interfacing is no longer an art. It is a set of techniques, and in
some cases just a set of components. This book presents the techniques and
components required to assemble a complete system, from a basic central
processing unit, to a system equipped with
all
keyboard to floppy-disk.
Chapters two and three are a recommended reading
for
every designer
has not had the experience of designing a basic system. Chapter two
presents the construction of a basic CPU, in the case of popular micro-
who
processors such as the Intel 8080. 8085, and the Motorola 6800. Chapter
with
three presents the set of input-output techniques used to communicate
facilitate
the external world, and a brief survey of the existing chips which
Chapter four
is
CRT
display, tape-cassette.
following chapters then focus on specific interfacing problems and
techniques, from industrial design (analog-to-digital conversion) (chapter
type, floppy-disk,
The
five) to
the design of a
32-channel multiplexer.
Finally,
CHAPTER 1
INTRODUCTION
OBJECTIVE
The
objective of this
book
is
hardware,
it
will
LSI
interface chips,
in
been the
art
of designing
managing the data transfers and the synchronization signals necessary for the processor to communicate with external devices. The processor itself has traditionally required one or more boards of
Each I/O
logic.
logic
on or more boards of
CPU
in
in the
a single chip.
implementation
chips.
The
architecture
It is
now
is
LSI
is
that the
chip.
number of LSI
still
imple-
menting your interfaces on one or more boards of logic, your design might
be obsolete!
Microprocessor interface-chips have not reached their maturity
yet.
They are still "dumb" chips. In other words, they can execute only a very
few commands. It can be predicted that in view of the very low cost of a
processing-element, most microprocessor interface chips will become fully
programmable in the near future. They will become "processor-equipped",
and be capable of sophisticated programmed sequencing. They will become
"intelligent" interfaces.
Although this next step has not been reached yet, all the techniques
presented within this book should retain their validity in the future. There is
always a trade-off between software and hardware implementation. The
balance will change with the introduction of new components, and with the
trade-offs involved in each specific system design.
As
all
the
common
interfac-
may
processor."
essor.
is
reason
to a "standard micro-
number
Motorola 6800,
limitation
on DIP's
simple:
is
by economic considerations.
components having more than 40 pins are
package
on a
itself
(abbreviated
MPU), and
perhaps the
clock, reside
single chip.
and RAM,
and I/O chips are external to the microprocessor, a selection mechanism
must be provided to address the components: a microprocessor must be
equipped with an address-bus. The standard width of the address-bus is 16
permitting the addressing of 64 K locations (where K = 1,024: 2 16 =
bits,
64K).
An
8-bit
microprocessor
must be equipped
At
least
tion to
an external crystal or
for power,
The
control-bus).
Because of
total
this
pin-number limitation, a
is
40.
No
16-bit
system (the
in the
pins are
left
unused.
microprocessor cannot
provide at the same time a 16-bit address-bus, and a 16-bit data-bus. One of
the buses must be multiplexed. This results in turn into a slower operation,
and
components
to multiplex
and de-multiplex
the buses.
It
will
soon introduce a
A mi(ROM
+ RAM) on
memory
on the
directly
is
chip, there
is
become
lines.
current limitation
Adding
is
external
expected that
it
memory
will
become
ROM,
involves
7T
V
PROGRAM-
ROM
MABLE
I/O
(PROGRAM)
.I/O BUS.
wZ^
v
^~
j/0 BUS K
czf~>
I/O
'
* CONTROL*'
DEy,CES
'
:>
CONTROL LINES
Fig.
1 .1
For the time being, the 8-bit microprocessor is indeed the standard de"powerful" and flexible applications, and will be referenced as
INTRODUCTION
The
such.
appears on Fig.
the
left
of the
was external
The microprocessor
1-1.
to the
itself,
labeled
MPU,
appears on
On most
illustration.
MPU.
It
Since 1976, the clock circuitry has been incorporated in the microprocessor
chip itself and all recent products do not require this external clock. How-
The
data-bus (implemented
8-bit bi-directional
It
appears here,
in tri-state logic to
allow
DMAC).
Finally, a 10 to 12-line control-bus which carries the various synchronization signals to and from the microprocessor. Control lines are not neces,
sarily tri-state.
All the usual system components are directly connected to these three
The three basic components appear on the illustration. They are
buses.
respectively the
only Memory.
Memory.
It is
ROM,
the
RAM,
ROM
is
the Read-
The RAM is the Random-Accessmemory which stores the data. The PIO is
It
MOS
a read-write
The
may
other chips.
Interfacing techniques are precisely those techniques required to connect this basic system to the various input-output devices. The basic interfacing techniques required to connect any microprocessor system to inputoutput devices are essentially identical. They will be described in detail in
and
five.
control-bus which
patible
At the
is
the control-bus.
make
It is
10
microproces-
appear on Fig.
1-2.
more
SC/MP,
inter-
interfacing charac-
appears on Fig.
1-3.
16-BIT DATA/
ADDRESS BUS
16-BIT
SC/MP
6800
PACE
8080
16-BIT
12- OR 16-BIT
8-BIT
8-BTT
8-BIT
ALL CHIPS ARE 1 TRUE; HOWEVER, IF INTEL SYSTEM BUS DRIVERS AND RECEIVERS
= TRUE.
ARE USED, 8080 SYSTEM DATA AND ADDRESS BITS ARE
ADDRESS STROBE
NONE
MRDC
DATA
2MHz
Fig.
1 .2
TO READ
TO SET
NADS =
MEMORY ADDRESS
LATCHES
VMA = 1
IDS 1 TO INPUT
DATA
R/W
DATA
2MHz
1MHz
NADS *
(CONCURRENT WITH)
1 TO READ
NRDS =
DATA
TO READ
1MHz
two basic
techniques:
1.
The fundamental
the microprocessor and the external world. This topic will be addressed
chapter
in
3.
MPU
data-bus
is
bus
is
implemented
is
8-bit-bi direc-
MPU. The
connect of the address-bus and the data-bus will be presented in the next
chapter.
The
third bus
is
It carries
the micro-
INTRODUCTION
11
CM
C\J
CM cy
!* IS
03 PS
CO
cy of cy cy cy
gg!i!gggg
3l
j
d
Ho
SB o
WS M
MS
Fig. 1.3
12
Signal Equivalences
CO
memory
2.
input-output synchronization
3.
4. utilities,
synchronization
Memory and
reset.
hand-shake procedure
is
or signal will indicate the availability of data. Data will then be transferred
"acknowledge"
is
case of
some input-output
devices, an
is
verified
through a
is
An
asynchronous design
will
8080 Control
INTRODUCTION
Signals
13
'
T,
Tj
T.
T
1
..
i
v_
ML
WA
n
L
/
i
1M
x.
UNKNOWN
0,0
SVNC
FLOATING
FLOATING
v_
,:;:
WRIT! MODE
E.OV
*AIT
Mm
on
DATA
TATUS
NFORMATIOM
/
DATA
MEMORY ADORE S3
SAMFLE REAOV
HOLD AND HALT
OPTIONAL
I/O
INSTRUCTION
DEVICE NUMBER
OR
STATUS INFORMATION
INTA
FETCH OATA
OR
Of*
ACCESS TIME
OUT
Basic
DBIN
IS
TRIGGERED BY B,
DBIN Timing
14
OPTIONAL
INSTRUCTION
EXECUTION
IF
REQUIRED
c;
>
DATA BUS
^>
DBE
D0-D7
TSC
HALT
NMl
6800
RESET
IRQ
BA
VMA
R/W
.01
CLOCK
A0-A15
5Z.
02
APPRESS BUS
DBE T
CONTROL BUS
6800 Bus
IT
'
1111*0
^>
N.
Signals
$1
CLOCK
$1
RESET
Trq
INTERRUPTS
NHI
HALT
3-STATE CONTROL
-*
Detail:
INTRODUCTION
15
16
CHAPTER 2
ASSEMBLING THE CENTRAL
PROCESSING UNIT
INTRODUCTION
The
is
CPU. A CPU includes the microprocessor, plus any additional components it may require. Memory devices, buffers, decoders, clock-drivers are
all included in the typical central processing unit. Many of these circuits are
now being integrated on the same chip as the processor. In fact, since 1976,
one-chip microcomputers are a reality. Yet, even with the advent of onechip microcomputers, there
cuit fabrication.
still
chip,
packaging
1,000,000?
1
NUMBER
OF
10,000
TRANSISTORS/
CHIP
1,000
I
1960
2-1
I
1970
1
1980
17
At
only single transistors were made on each chip. Later, differenand simple logic gates made their appearance. Present technology
allows for up to 30,000 devices to be integrated on a chip. A
graph of
tial
first,
pairs,
devices integrated versus time appears in Fig. 2-1. One factor has remained
constant throughout this process: process defects limit the maximum
size of
the individual die. Yields are higher for smaller die sizes.
(The yield
LSI
is
the
chip, the
of the
final
proved
yield.
2-2
package-pins
may
18
made from
crystal
is
The
integrated
silicon.
its
is
external.
LSI technology
partition our
system into multiple components, additional devices are often needed for
system expansion. Large microprocessor systems require a
significant
amount of "support-logic".
This chapter
will
Four
CPU: from
SYSTEM ARCHITECTURE
Fig. 2-3 presents the block-diagram of a typical microprocessor system.
All standard microprocessors, such as the 8080 or the 6800, have a similar
architecture.
and control-bus.
INTERRUPT
LOGIC
-mJ
VV
CPU
nrr
TMT
H
H
IT
H
2-3
The data-bus
mH
carries information to
output-devices.
To
specify
where the data are going, or where they are coming from, the
19
address-bus
used.
is
It
selects a location in
memory
or a register of an
input-output device.
The
control bus
is
processor," or "write to an output-device from the processor." Additionally, interrupt, direct memory access, and other control functions are
carried
by
lines
zation of events.
information in
nibble.
and fully-decoded
selection.
Linear Selection
In the microprocessor- world, memory is partitioned into read-onlymemory (ROM) for programs and fixed data tables, and random-accessmemory (RAM) for data storage and temporaries, because of the volatility
of MOS RAM's.
When more than one type of memory is used, the two types of memory
are generally in separate packages. Also, the size of each will be considera-
full
We
proper place
RAM
in
ROM
in
RAM
ROM
Two basic techniques are used to implement the chip selection: Linearselection connects individual address lines to individual chip-select inputs.
For example,
if
selected
20
whenever the
memory
is
tied to a chip-
most-significant-bit
locations.
Assume
is
a one. This
that our
ROM
is
by
selected
being "1".
The
is
To
RAM
by
this bit
we
A0
connect lines
will
this most-significant-bit
to
A7
of the address-bus.
new
address-line. This
is,
is
chip
simplicity:
selected
is
all
no special logic
by a dedicated
small microprocessor
systems.
address-selection, and
may be used
AI4
AI5
A15
AI3
AI2
A11
A10
A5
A6
A7
A8
A9
A3
A4
A2
A1
A0
ROM
CS
'
RAM
PIO
CS
CS
Linear Selection
2-4
the available
is used. If the
memory
in half every
time
fully
decoded addressing.
Fully-Decoded Addressing
The
is
to provide a
dressing capability.
In our example, the 256-location
tions
of
the
memory.
RAM
Expressed
binary,
in
Grouping
12.
FF00
bled
when
this is:
We
to
this
256 loca-
addresses
FFFF.
RAM chip
bits together
is
should be ena-
"AN Ding"
these
decoding for
our example.
21
A15
2-5
AND
Instead of using
gates for every device, there exist generalpurpose gating devices known as decoders. An example is the 8205 or
74LS138
three-to-eight decoder.
When
the three enable inputs are in their proper states, one of the outputs will be
active depending on the three select lines. Examples using the 8205 will be
S0= (A0-A1A2)
S1 = (AD
(E1-E2E3)
A1.A2)
(E1-EE2. E3)
2-6
22
8205 Decoder
space.
is
mem-
Most
sys-
partial decoding.
Storage Chips
The basic devices for storing information now used are the RAM and the
ROM. The ROM contains permanent information and cannot be changed
by the system. The RAM allows for temporary storage and retrieval of
information. The program information is usually kept in a non- volatile
ROM
since
stored in
it
does not change, and the data and intermediate results are
RAM.
"RAM"
is
bit
cell
may
consist of a flip-flop
in
cell.
in
18- PIN
Dynamic
RAMs
Address
is
multi-plexed
23
real-time applications as
ROM
will refer
memory
is in
will
progress.
may
ROM's
are available.
it
makes
data manipulations.
The use of
EAROM's
military applications.
Each input of a device presents a load on the output driving it. Most
components drive anywhere from one to twenty other components. Every
component must be checked for its input and output loading and driving
characteristics.
to
every
memory and
2-7
24
this, buffers
or drivers
listening to the
processor.
Fig. 2-7 illustrates the use of transmitters to buffer the address
control-buses.
The
lines
and
on the address and control buses are unidirecone direction.
must pass
in
will receive
TRANSCEIVER
2-8
sented so
far,
THE
8080
Intel's
RAM), and an
now be
8085 system.
SYSTEM
8080 has been the most widely used "standard "-architecture-
microprocessor.
The 8080
microcomputers.
for a typical 8080
is
We will assemble
many hobby
the: clock,
system
25
RAM,
controller,
covered
and
in detail in
ROM
Chapter
will
will
be
3.
2-9
The Clock
The 8080
requires a
Initially,
clock-drivers
must
connects the crystal to the 8224, the 8224 to the 8080, and
ing
is
One merely
clock interfac-
complete.
all
itself
in Fig. 2-9,
When designing the 8080, the lack of pins became a major limitation. In
order to gate out the required control signals, pins have to be multiplexed.
26
>
SYNC
->
01
->_
o E:
dh
RST
2-10
TTL
8224 Schematic
2-1
Control or address functions would have to share lines with the data-bus. In
chose to multiplex control information or status on
SYNC
signal.
The
may be
lack of pins
is
essentially
27
used for the 8080, which required three power levels, using four pins.
Early processor designs used latches and random-logic to capture these
status signals. In fact, this
known
is
why
The
still
retains
The
what
known
is
as
mation and the gates decode the status along with the other 8080 control
memory and
input-output devices.
should be
inte-
in Fig. 2-12.
This
shown
device latches the status and drives the control bus. In addition,
the data bus,
i.e.
it
buffers
DB0
DB1
DB2
DB3
BI-DIRECTIONAL
CPU
DATA
DB<4
BUS DRIVER
BUS
DB5
DB6
DB7
SYSTEM
DATA
BUS
-*- HEfIR
STATUS
LATCH
GATING
ARRAY
I/OW
BUSEl
IilTA
2-12
The
-*-
STSTB
DB|N
WR
HLDA
MEMW
-+- T70R
function.
Connecting the
ROM
in
two
essential varieties:
programmable and
28
are
programmed
at the time
of manufacture
ROM's
in
production systems.
The
CH
2708 Selection Using 8205
2- 1
^:
"V
I
"V
I
decoding
DATA FROM
2708
delay
^^
unstable
^^^^
stable
^^
PROM
ACCESS
TIME
2-14
PROM Timing
ROM
typical erasable
appears connected to our 8080 buses in Fig.
This device, a 2708 EPROM, contains 1024 bytes of memory. In order
to address 1024 bytes, 10 address lines are needed, (2 10 = 1024). In addition,
2-13.
the chip
must be selected
at its
proper place
in the
memory map.
We
will
29
choose to put
this
memory
at locations
up
to
memory
is
used
in addition to
some other
if
it
can
The
required.
The only control-line required is the memory jead line. The timing of a
memory read appears in Fig. 2-14.
The address and memory-read lines activate the 2708. After a period of
time called access-time, the data byte fetched appears on the data-bus. The
processor reads this byte and executes the instruction.
Connecting the
RAM
(IK =
1024).
manufacture of
inexpensive configuration
is
by
bit (least
Another popular
size is
256 by 4
bits.
ROM's
in different sizes.
number of
needed
This type of
is
K by
for
We
need
each
bit.
interfaced here.
256 by 4 implies that two devices are needed to complete the byte.
The
schematic for the 256 by 4 memories, interfaced to the 8080 bus, appears
Fig. 2-15.
Buffing
30
The most
pins).
one
RAM
is
in
DATA BUS
nlD d3
d4
A0_
A0
Al
A2"
~aT
"aT
s:
s:
d5d>
d7
Ai.
TS
cs
a8
>
a15
Connecting the 2 1
2- 1
1 1
RAM
the
memories
for reading
V
TRISTATE
X
data bus
TRISTATE
~
ACCESS
TIME
<
2-16
READ CYCLE
stable
> estate
,
>
WRITE CYCLE
RAM Timing
31
writing operation.
The
RAM's
2111
line.
The two
read" enables the output drivers of the chips to drive the data-bus. At all
is in a read-mode, but will not place information on the
bus.
RAM's. Timings
of these operations
When
the address
the chip
write"
is
becomes
and "memory-read"
stable
is
is
The
is
brought low,
accessed,
it
until fetched
write-cycle
is
"memory-
RAM's.
Integrating the processor and
we draw them
all
memory
into
an assembled module
re-
To make
life
more
interesting, the
PROM's
20FF hexadecimal.
0FFF
It will
hexadecimal.
this
XX01
1 1 1 1 1 1 1 1 1 1 1 1
0XX1XXXXXXXXXXXXX
(don't care condition). The PROM
binarywhere
form:
through
in Fig. 2-17.
binary.
is
We
addressed
for:
all
addresses of the
is
a one or a zero
XX00000000000000
memory
to
The
As an
THE
6800
SYSTEM
is
ments some design philosophy differences. The most obvious are the lack
of pin-multiplexing and the single power-supply requirement. Other differ-
ences
lie in
a 6800 system.
32
shows a schematic of
I?
CO
oo D-
LO
CM
or
X
3"
oo
oo
CD
oo
CD
Q_
II
MINIM
oo
CD
1^
oo
CD
Q_
^:
=r
it
oo
CD
oo
oo
OO oo
CD CD
r^.
i^.
PP
rii
CD"
oo
y
(=5
-lo
Lo
en i
<Ci
CD
2- 1
33
6800
DATA BUS
ROM
RAM
-ft"
PIA
ff
"ft-
"
|_
IN
R/W
2- 1
V =>
The Clock
The 6800
requires a
non-TTL compatible
clock-generator. Since no
other useful functions are needed for the two-phase clock generation, either
simple discrete clock circuits, or integrated drivers are used. Motorola
produces a hybrid device which contains the crystal and conveniently provides the necessary clock phases. Fig. 2-19 details the 6800 clock require-
ments.
eye
01
^~V
02
2-19
Signals
6800 Buses
34
essentially equal
troller includes
a data-bus driver).
applications.
NC 6880
DATA
J
BUS
HC 8T26
6800
XC 6885
ADDRESS
J
BUS
XC 8T95
non/inverting available
2-20
8ns
Suggested Devices
For memory
R/W,
interfacing, the
address control
<I>,
and
two of the
line.
TSC
DBE
R/W
MPU
VflA
IRQ
IS
IS
IN
PC
IS
PI A,
AC
NON-MASKABLE INTERRUPT.
NMI"
IS
HALT
BA
(HALT OR WAIT)
2-21
6800 Control
Signals
35
The
ROM
Motorola manufactures a
tate the interface
by
8-bit
mask
line
requirements
ROM
facili-
in small
ROM.
,,
1
1
CHIP1
CHIP 3
CHIP 2
CHIP 8
<
DATA BUS
^>
7%
D0-D7
IK BYTE
A0-A9
R0M
A10
VMA-02
CS0
+5V
ADDRESS BUS
CONTROL BUS
2-22
In the
example of
6800
36
way, the
ROM Connection
ROM
is
memory
<J>2
signal.
X
1C00
to
large area
it
takes up
is
is
undecoded address
due
A15, A14, and A13. The essential advantage of providing the three
Chip-Selects is to allow the possibility of connecting up to 8 devices to only
bits:
3 address lines:
The
no external decoder
is
2-24).
RAM
Motorola
RAM.
This
RAM
is
is
is
number of decoded
The
8-bit
The
interface of the
RAM
appears
in Fig. 2-23.
Note
RAM
bytes.
The other
address lines must be used in some combination to select the chip. In this
example,
is selected when Al 1 through A7 are all low. This would be
RAM
00FF hexadecimal.
memory is
it is
DATA BUS
D0-D7
A0-A6
128 BYTE
RAM
M
A8
CS1
VMA
CS3
CS2
A9
4-5V
CS0
11
-=r
3>
=>
ADDRESS BUS
CONTROL BUS
2-23
6800
R/W
COT
^css
RAM Connection
The 68 1
37
Q_
y>
itOOlf
S
ce
is
Ice
a.
lesi
C_>
|C_>
<_>
OO
J k
<c
is i-h
OO OO
<
a
cc
3
^v
Dd
LU
j
'
>
'
=r
t
.1
OO
PQ
oo
oo
LU
=>
\
oo
CL
f=>
(=>
oo loo l^l'O
1
<C
a:
en
oo
Ii
<=
oo
oo
i k
oo
oo
i I
3c
<
CS1
RES
TSC
SJ
\,7
3
MPU
<C 1
01 0?is:
,>
Jn
a:
(
oo
LU
DC
CD
2-24
38
<C
RAM
with our
ROM, we
FFFF
The
must
ROM
is
and
memory
cycle,
and
output device
THE
is
is
that an input3.
Z-80
Up
its
it
has
some
Intel 8080,
The Z-80
original device.
which improve
is
software-compatible
Note
presented.
in Fig.
2-25.
POWER
CLOCK
Aq-Aq
+5 V
GND
ADDRESS
MREQ
^5v
ROM
RD
MA t
z-80
<*
DATA
OUT
c
I0RQ
1M
Ao
PIO
Ml
Al
T\
2-25
Z-80 System
\>
OUTPUT
DATA
INPUT
DATA
39
Dynamic
RAM
Interface
With
static
RAM's
RAM's
memory
is
applied.
RAM's.
Dynamic
A dynamic RAM stores informaSuch a device can only retain its charge for a few
milliseconds. The cell must be accessed every few milliseconds,
in order to
renew, or "refresh" the cell. The Z-80 provides the refresh address
using a
need to be refreshed periodically.
tion in a
FET
capacitor.
design trick.
After an instruction
circuit,
RFSH
MREQ
A
12
r>^>\
A0-AU
PAGE
MREQ
2-26
RAM, 20K
40
bytes of
UOZS-BiO-1
<OOliUt
sa-a
2.S.
Ad*
77_~ w wo/i
MM
00.
3TV
L
2
<
BU
as
*
.
i
Q
2-A/V
11
7s :*
OJ
ui
IA
2-27
Ul
TTTT
SldnMM3J.NI
8085 System
41
consists of eight
4K by
8-bit
processor.
The 8085
Intel naturally also had to improve the 8080
design. The 8085 reduces the
parts count of an 8080 system while increasing
the speed. Essentially, it
integrates the 8080, the 8224, and the 8228 into a
single-chip.
This time, to provide expanded control functions, 16 address
lines and 8
data lines, the decision was made to multiplex the low
eight address bits. At
ALE
address
("address-latch enable")
Fig. 2-27
no latch
special
is
bits.
is
bitsl Intel
it
has created a
new
line
of
low-address latch.
lines.
The
may be
built.
An
8277
PROM
I/O chip
is
presented
CLK
READY
DATA
PCWER
2-28
42
8277
PROM + I/O
in
LSI chips
Fig. 2-28.
The clock
crystal to
two pins
been
The connection of a
CPU.
X1
_d'
X2
X2
WITH A CRYSTAL
SUMMARY
The standard microprocessor
the
architecture, with
its
devices,
RAM
full
were presented
address-decoding.
The
CPU
CPU
The
now be
43
CONVERSION TABLE
BINARY
DECIMAL
HEXADECIMAL
0001
0010
0011
it
It
It
0101
0110
OOOO
0100
0111
1000
10
1001
11
1010
10
12
1011
11
13
1100
12
lit
1101
13
15
1110
lit
16
1111
15
17
APPENDIX CHAPTER 2
44
CHAPTER 3
BASIC INPUT-OUTPUT
INTRODUCTION
Now
our microcomputer
is
complete, the
mation must be displayed, and sent to control the various devices. This
chapter will present the input-output techniques, and illustrate them with
design examples. This will be done in two steps.
first
will first
scheduling techniques required for sequencing the input-output devices will then be presented: polling, interrupts, and direct-memory-access.
The
first
be
clarified.
MEMORY VS.
I/O
distinguishes
I/O and
Memory-Mapped I/O
many more memory instructions than I/O instructions. For exammemory-mapped I/O, arithmetic may be performed directly on an
input or output latch, without having to transfer the contents in and out of
temporary
What
registers.
way makes
one
are
needed as
BASIC INPUT-OUTPUT
45
this is virtually
in a microprocessor system. Second, instrucon the memory normally require three bytes to address
the location of the port (there can be 65,536 locations, which require 16 bits
of address), whereas special I/O instructions may need only eight bits to
I/O
memory
instructions.
Mapped Input-Output
In
is
not
signals indicat-
for
memory.
Two
may be used
to select
memory
locations.
The disadvantages
One
are two:
loses
the processing
control
this
technique
Fig. 3-1
trol signal,
is
depends on the
through
memory
A0
shows a memory-mapped input-output system, where the conwhich determines whether the address is for memory or I/O,
state of
A15.
If
A15
is
high, then
A15
is
low,
all
addresses on bits
A14 through A0
location.
MEMR
MEMW
I/OR
TO
MEMORY
TO
I/O
I/OW
3-1
46
Memory-Mapped Input-Output
A14
specify a
Fig. 3-2
lines for
in
device and a register or location within the device. This is illustrated
is
This
performed.
Fig. 3-3. The control-bus will specify the operation to be
MEMR
TO MEMORY
IOR
TO I/O
IOW
Input/Output Mapping
3-2
LINEAR SELECTION
10
15
ADDRESS
WASTES MEMORY:
7
BITS:
1
IK
LINEAR
SELECT
ADDRESS
UNUSED
(WASTE)
BIT 15
ON
BIT 14
ON
8K
BIT 13
ON
4K'
BIT 12
2K
BIT 11
ON
ON
32K
UNUSED
16K
UNUSED
BASIC INPUT-OUTPUT
47
:>
^
REGISTER
SELECT
MEMORY
3-3
I/O
CHIP
DATA BUS
^TO
DEVICE
FROM DEVICE
ADDRESS BUS
3-4
PARALLEL INPUT-OUTPUT
minimum
On
is equipped with
an input-buffer, which latches input signals from a device, and holds them
stable, until the microprocessor requires that information, and with an
48
DATA BUS
=>
7>
ADDRESS BUS
i>
\7
I/O
I/O
<=^>
DATA
ADDRESS
I/O DEVICE
I/O INTERFACE
> CUNIKULK
STATUS
\7
CONTROL BUS
3-5
(I)
AUDBESSJUSL
<=^
CftTfltp
ADDRESS DECODER
OUTPUT
WRITE
EN
LI
CLK
^>
OUTPUT
3-STATE
LATCH
BUFFER
READ
LATCH
INPUT STROBE
CONTROL BUS
3-6
BASIC INPUT-OUTPUT
CLK
3-STATE
BUFFER
BUFFER FULL
DATA RECEIVED
<^r
(II)
49
them
essentially obsolete.
Programmable
described.
The address-decoder
These
written.
will select
registers
one of the
may be
select, will
'
'programmable'
PIO
is
'
is
it is
possible,
bit-by-bit basis, to define a port as having the first three bits configured
The
tion.
Each
ponding
bit
PIO
ports
programmable
is
A PIO
put.
in direc-
of the "data-direction register" specifies whether the corresof the PIO port will be an input or an output. Typically, a "0" is
bit
is
programmable
in
"1"
PIO
specifies
an out-
typical
PIO
The maximum
is 3,
including control
appears on Fig.
3-7.
two ports
Example
The
two
1:
internal
PIA
One
set
is
3-8. It
for port
for
port B.
same
is
input. Bits 5, 4,
and
SO
CA1
it
Its
input.
format
It is
monitors the
shown on
CA2
interrupt-flag.
The
CA2
is
used as an
PORT 2
PORT 1
14*4
*
DATA BUFFER
DATA BUFFER 2
J
FUNCTION REG
FUNCTION REG
POWER
STATUS
CONTROL
LOGIC
i
CHIP
SELECT
MICROPROCESSOR
DATA BUS
CONTROL
SIGNALS
Typical PIO
3-7
DDRA
CA1
PDRA
-+-CA2
DATA BUS
> -D
(A -i X
H > m
CRB
REGISTER
RS0
SELECT
RSI
DDRB
<^=>
PDRB
<=>
IRQA
-*-
--CB2
TRQB
-*-
3-8
BASIC INPUT-OUTPUT
CB1
6820 PIA
51
CRA
IRQA1
IRQA2
READ-ONLY
3-9
clarification
register-select
DDR
CAl
CONTROL
DORA
ACCESS
READ/WRITE BY 6800
two
CA2 CONTROL
same address.
Bits
and
is
the
in each port share the same address! They are differentiated by
the value of bit 2 of the control register, a programming nuisance.
Fig. 3-10 indicates
RSO
pins,
and the
how
RSI and
SELECTING PIA REGISTERS USES 2 LINES (RS0, RS]). PLUS BIT 2 OF CR:
RSI
RS0
RSI =
RSI = 1
RS0 = 1
RS0 =
CRA(2)
CRB(2)
REGISTER
BUFFER REGISTER
CONTROL REGISTER
1
]
3-10
Fig. 3-11
52
CONTROL REGISTER
direction registers.
BUFFER REGISTER
1
1
shown
and
and data
DATA BUS
u=>
cai
D0-D7
k-
CA2
PA0-7
RS0
RSI
CS0
PB07
E5Z
CS1
E
R/W
Reset
CB2
CB1
+ 5V
inn
<:
3-1
ADDRESS BUS
CONTROL BUS
tai
Interface
"
TAO
DATA
<^
_.
INrUI
KLAUY
mm it
Ari/
DATA
00000000
00100111
DATA
>
nMTDIIT
11111111
00100111
mo
_-.
LOl
3-12
BASIC INPUT-OUTPUT
nn-rniiT
nrnu
uuirui KtUUt5l
6820 Application
53
As
chip as
it
DATA
DATA LINE
^
3-13
Example
2: Intel
(BIDIRECTIONAL
CONNECTION)
8255 PPI
The 8255
bits each.
contains four ports, two with eight bits each, and two with four
Each port can be programmed via the mode control register to be
either
inputs,
all
all
Fig. 3-14.
Table 3-15 indicates how the ports are addressed. There are several
operation, where each half of port C are used for interrupt flag
inputs or handshaking signals. The Intel device is not programmable by bit,
modes of
but offers 4 more lines for control. Overall, the functions performed are
54
o
O
o
I/O
GROUP A
PA0-PA,
PORT A
(8)
GROUP A
<^
CONTROL
<=>
DATA
BUS
BUFFER
GROUP A
PORT C
tt
*c
WR
<
Al
C>
READ/
C=3
WRITE
CONTROL
GROUP B
RESET
"^3
"TZ
RD
pc /) -pc
UPPER (4)
CONTROL
LOGIC
GROUP b
PORT C
LOWER (1)
GROUP B
PORT B
<^
(8)
CS-
8255 Addressing
3-14
c s
A 1
R D
OPERATION
W R
MP'J
READ
PORT
TO DATA BUS
(A.
3.0
MP'J
j
C
\
3-15
ILLEGAL
WRITE
(DISABLE)
8255 Addressing
SERIAL INPUT-OUTPUT:
Several devices require serial communication: teletype (TTY), tape,
disk.
BASIC INPUT-OUTPUT
55
Instead of latching eight bits of parallel data, we could pass each bit in
the byte to a single line one at a time. Known as bit-serial interfacing, there
are serial standards that cover this kind of transmission. Such standards are
discussed in Chapter
shown
6.
serial
input-output to a teletype
is
in Fig. 3-16.
MARK
ST0P1
START
LSB
MSB
SPACE
STOP 2
- TIME
3-16
Serial Character
Format
bit
UART
to
perform
this conversion:
by software, or with a
software,
deserialization.
On
program can simply accomplish the serializationprogram will wait until it senses a start bit,
input, the
gram
On
bits.
An
with a pro-
line,
in the
flowchart of
Fig. 3-17
It will
is
to
one
bit at
The
simplest
way
is
is
to output the
connected only to
line 0. The accumulator is then shifted right, by one bit position, a delay is
implemented, and the next bit is output. After 8 (or more) outputs, the
initial parallel
Conversely, assembling
as simple. Bit
is
assembled.
56
serial
The accumulator is
shifts,
is
just
shifted
left.
ENTER
ENTER
SEND START
SET BIT
COUNTER TO
ELEVEN
BIT
OUTPUT
A BIT
SEND DATA
BITS
DELAY
9.1 MSEC
SEND STOP
BIT
NO
DONE
EXIT
YES
RET
3-17
Flowchart for
Serial
Conversion
TYOUT
MORE:
MVI
MOV
ORA
RAL
OUT
CALL
RAR
STC
DCR
JNZ
RET
B.ll
A,C
A
2
DELAY
B
MORE
,
,
DELAY
DLO:
DL1:
MVI
MVI
DCR
JNZ
DCR
JNZ
D,6
E.2000
E
DL1
D
DLO
3-18
,
,
1.5 MSEC
INNER LOOP
8080
Serial
Conversion Program
is
simplicity
and the
quired.
BASIC INPUT-OUTPUT
57
UART
and USART:
One
serial-to-parallel
and
parallel-to-serial converter.
UART. A UART
The
is
parity,
parallel data.
The
UART
UART appears
on
Fig. 3-19.
Each
Almost
all
of the standard
"improved" version
UART.
SERIAL INPUTCLOCKenable/reset-
PARALLEL
OUTPUT
RECEIVER
PARALLEL
TRANSMITTER
SERIAL
I/O
OUTPUT
CLOCK
STATUS
SIGNALS
CONTROL
CONTROL
FUNCTIONS
POWER
3-19
The
Motorola MC6850 ACIA (asynchronous communications interface adapand the Intel 8251 USART (universal synchronous and asynchronous
tor),
receiver-transmitter).
Example
The
1:
internal block
ACIA
diagram of the
ACIA
the input and output serial/parallel registers, the control circuitry imple-
for details
58
EIA RS232C
ACIA
TDR
TRANSMIT
Jp
<
DATA
BUS^
=>
MUX
<
SERIAL
DATA
DATA OUT
RDR
RECEIVE
SERIAL
DATA
DATA IN
SR
STATUS
"
CR
CONTROL
3-20
3-21
BASIC INPUT-OUTPUT
6850 ACIA
59
down
modem
serial devices.
The clocks
RS232C modem
The
explanation
controls the
link.
system.
full
The modem-control
truth table
The bus
may be
different for
internal registers,
REGISTER
R/W
R S
CONTROL
STATUS
RECEIVE DATA
TRANSMIT DATA
6850
3-22
Example
2:
The
Intel
8251
USART
control signals for the 8251
USART
are
shown
it
in addition to
asynchronous transmis-
USRT,
the
"SSDA"
for
synchronous
communication)
The
The
mode,
The
is
Some
of the
4>2 clock
USART
status,
60
is
TxRDY
SERIAL OUT
TxD
TRANSMITTER
TRANSM. EMPTY
TxE
TxC
CHARACTER READY
RxRDY
RxD
TRANSMITTER CLOCK
(baud rate or multiple)
SERIAL IN
RxC
RECEIV. CLOCK
SYNDET
RECEIVER
DATA BUS
<^=$
BUFFER
RESET
CLK
c/d
RD
MODEM
CONTROL
WR
DSR
DTR
CONTROL
CTS
RTs
CS
3-23
8251
USART
CQMTRQL MIS
aBWBSU8
11=3 wr
I
8251
15
e
CRT
CRT
TERMINAL
CONTROLLER
:=a
3-24
Serial Interface
BAUD RATE
GENERATOR
Summary:
Most
KEYBOARD
be made even
in
UART's.
new
troduced to perform
Still
more sophisticated
BASIC INPUT-OUTPUT
standards described in
61
c/tT
RD
WR
cs
OPERATION
8251 TO DATA BUS (READ)
3-25
We
have introduced
required for
scheduling-strategy
strategies.
These three methods are illustrated on Fig. 3-26. They are called: polling, interrupt-controlled, and DMA. (Combinations may also be used).
Programmed I/O or
In
programmed
Polling:
input-output,
all
transfers to
formed by the program. The processor sends and requests data; all input
and output operations are under the control of the program being executed.
The
transfers
method
for determining
flag is
a bit which,
when
a condition
has occurred that needs attention. For example, a flag indicates "device-
ready" = buffer
full for
device.
The
flag is continually
approach
overhead.
62
is
checked:
to use a minimal
it is
The
characteristic of this
at the
expense of software
"polling."
amount of hardware
MEMORY
DATA BUS
>
MPU
^
i
^__
>
1
I/O
I/O
POLLING
MEMORY
1
INTERRUPT
MPU
I
I/O
I/O
INT
t INT
t INT
1
HOLD
DMA
MEMORY
DMA
MPU
III
>
I/O
L- i/o
1
L_
3-26
SERVICE ROUTINE
FOR DEVICE A
SERVICE ROUTINE
FOR DEVICE B
SERVICE ROUTINE
FOR DEVICE C
3-27
BASIC INPUT-OUTPUT
Polling
Loop Flowchart
63
The program
if
When
is
is
its
completion.
Two
basic
use of a
The
flags
simplest technique
nient
is
of eight devices
When
the port
is
first
read
in,
bit,
!_
INDIVIDUAL
INTERFACE
DEVICE
D2
FLAGS
D3
k:
W
k
k
k
CPU
D4
D5
J2L
D7
DECODED
ADDRESS
3-28
is
ROM or a priority-encoder chip. This way, the status port holds the actual
address of the highest-priority device requesting service. Figs. 3-29 and 3-30
show
64
No
1
3-29
Device
on port
Device 2 on port 2
service requested
Device 7 on port 7
Byte Format
A-
Priority
Encoder
N<*-
bit
binary code
of input with
highest priority
3-30
Polling Priority
Encoder Hardware
By changing the upper five bits to any other code, other port addresses
may be generated. This will save looking up or generating the port address
from the device-ready status-port since that port holds the address of the
ready device.
is the most common and simplest method of I/O control. It
no special hardware and all input-output transfers are controlled by
the program. Transfers are said to be synchronous with program execution.
Polling
requires
BASIC INPUT-OUTPUT
65
Interrupts
The
It is
peripherals
all
2.
limitations:
it
the time.
all
It is intrinsically
two
slow since
it
all
when
illustrated
is
on
Fig. 3-31.
nected to an interrupt
line.
This line
will gate
its
controller,
is
con-
mi
I/O
I/O
INTERFACE 1
INTERFACE n
INT
INT 1
INT n
'
Interrupt Sequence
3-31
microprocessor
tion. If
an interrupt
present,
it
is
will
present,
it
program
in
at the
critical
is
no
interrupt
is
processes,
it
must be guaranteed
If the
system
is
Power
failure
failure
is
detected.
power-failure routine
is
66
is
considered a
INTERRUPT LOGIC
EXECUTE
INSTRUCTION
MASK
ON
_E
NEXT INSTRUCTION
3-32
This
is
on, interrupts
whenever
it is
"enable."
An
not masked.
PRESERVE REGISTERS
llfnwtmn
IDENTIFY DEVICE
(Iff
EXECUTE ROUTING
RESTORE REGISTERS
INTERRUPT HANDLER
3.33
BASIC INPUT-OUTPUT
Interrupt Control
67
Once the interrupt request has been received, and accepted, by the
microprocessor, the device must be serviced. In order to service the device,
Two
prob-
lems occur:
MICROPROCESSOR
MEMORY
SPT
** mwa-w-w-51
^^
NEXT INSTRUCTION
GENERAL
REGISTER
r
K^W^W-KJi
sp
pp
PP IS PRESERVED
IN THE
STACK
INTA
SP
* INTERRUPT
ROUTINE
pp Eaasaaasasasfl
ADDRESS OF INTERRUPT
ROUTINE IS LOADED
INTO PC
^T
INTERRUPT VECTOR
program
in
all
preserved
PC,
registers
in the stack, in
the con-
order to
install
new branching
address in
can be done
in
been preserved
Once
the
problem
away
registers will be
in the stack.
must be pushed
the
These
is
PC
may be
(plus pos-
microproces-
arises:
may be done
in
hardware, in software,
The
The technique
is
The
68
will
be
interrupt identification
It will
check
their
The presence of
in a
given bit
device did request the interrupt. Having identhe device which has triggered the interrupt, it will then branch to the
The order
is
conducted
will
serviced
is
in
which the
first.
poll-
This imple-
ments a. software -priority scheme, in the case where multiple devices might
have triggered an interrupt at the same time.
.
INTERRUPT
N0_ OUT
(RTI)
OUT
(RTI)
3-34
hardware,
is
on
This acknowledge
rupt,
it
is
gated to device
If device
number on
it
it
2.
Device 2
will
it
be
will
same
is
mechanism can be
The
fastest
method
is
the vectored-interrupt
It
becomes the
responsibil-
of the I/O device controller to supply both an interrupt and the identity
of the device causing the interrupt, or better yet the branching-address for
ity
it
is
is
BASIC INPUT-OUTPUT
is
achieved
16-bit
when
The
branching address.
It
69
(1 TO N LINE22
DATA BUS
3-35
in the
memory, and
made
this
One more problem arises: several interrupts may be triggered simultaneThe microprocessor must then decide in which order they should be
serviced. A priority is attached to each device. The microprocessor will
ously.
is,
will
Restart), level
be for a
will
priority
(PFR or
may be left
be for a power-failure
computer world,
CRT. Level 2
CRT. Level 3 could be
is
next, and so
Power-Failure-
software.
The
routine looking at the devices will simply look at the device with the
70
DATA BUS
DATA BUS
PIC Logic
3-36
interrupt register.
interrupt levels
The
masked. However
program.
rupts.
mask-register
selectively.
it is
is
also possible to
mask
The
be converted to a
parator in the
and
will
PIC determines
then generate a
will
The
will
will
The
RAM
of 8 x
acceptable,
the PIC.
is
The microprocessor
more sophisticated PIC
is
its
address bus.
by the programmer.
BASIC INPUT-OUTPUT
71
INTO
INT
INT 2
INT 3
INT 4
LEVE
VECTOR
3R
INT 5
INT 6
INT
INT
COMPARATOR
LOGIC
INT
DETECT
1NSTN
PROGRAM A
INSTN INSTN
INSTK
RETURN
jBRAHCIL
CONTROL UNIT
INTERRUPT HANDLER
OVER-
SERVICE ROUTINE
~
^
IHnta
|IRQ
HEAD
RQ
3-37
Interrupt Sequence
from
left
to right
on the
illustration,
program
Trq. This
account
at
at the
microprocessor
Once
this
branch
is
in
Going
execution until an
overhead-time
is
The
interrupt-handler
may have
to
line
of
spend some
in preserving the registers, which might not have been preserved automatically by the control unit of the microprocessor. The service
72
be restored (time
Tf
to Tr).
return instruction
is
registers
must
control unit restores the previous contents of the program counter (fetched
from the
Program
resumes
to
may resume.
time Tp.
at
Ts
program
is
the interrupt-response-time,
i.e.
time at which
has elapsed between the interrupt request, and the effective
manufacturers
Some
work.
useful
the service routine has started doing its
length of time
consider that the response-time is only Trq to Th. The total
the interrupt
in
involved
overhead
lost to the program is Tb to Tp. The total
is
really
Tb
to
Ts + Tf
to
significantly
from one
microprocessor to another.
Tc
TII.E
PROGRAM P
INTERRUPT
I,
INTEkkt.PT
I-
1HTERU.PT
3-38
Multiple interrupts
and
the stack.
Fig. 3-38 illustrates the role of the stack during multiple interrupts.
Time TO program P is
registers
in execution.
At time Tl
interrupt II
is
accepted.
At
The
used by program P are then pushed in the stack (see the bottom of
left). Interrupt II executes until time T2. At time T2,
Interrupt II
is
and
it
is
suspended just
like
P is
be popped back
in the
microproces-
left in the stack, (see Fig. 3-38: the stack contains only
II
at time
T4,
it is
P at
interrupted
again by another interrupt, 13, of higher priority. Again two levels are in the
BASIC INPUT-OUTPUT
73
stack: II
tion, at
and P
at
time
T4
ously, the
if
a large
programmer should
illustrates the
allocate a large
enough stack
simultane-
to contain the
successive levels.
DEVICE A SERVICE
CLEAR DEVICE A
INTERRUPT FLAG
RETURN FROM
INTERRUPT
INTA
CASB
*-
MSI
-*-
CAS2
-1
INITIALIZATION
RD-*k
fin
INT
(8228)
C0WNO
R/W
fr r
LOGIC
Afr
IRS)
B-SERVICE
MORS
fc
REGISTER
<^
PRIORITY
INTBNPT
RGOCST
CS-*-o|
RGGISTBt
7T
D0-7
<=>
2Z
IR7i
Direct
Memory
Access
device.
may
However
still
CRT
is
memory
is
transfers
to replace software
DM
DM
DM AC will require
DMAC
differ in the
way
may suspend
philosophies
a processor, or
it
may
stop
or
it,
it
may
DMAC
memory cycles
Some sophisticated
steal
DMA
A complete discussion
beyond the scope of this book. The simplest approach, and the one usually implemented for most microprocessors, is to
of
philosophies
is
suspend the operation of the processor. This is the reason for the tri-state
buses used for the data and the address-bus. The organization of a
system is illustrated on Fig. 3-39. Each device will send its interrupt to the
DMA
,16
1.
2.
3.
MEMORY
MPU
<F
MEMORY
MPU
DMA
HOLD
PERIPHERAL
MPU
MEMORY
DATA
PERIPHERAL
4,
MEMW
DMA
I/O DEVICE TO
DRIVER
TRANSMIT
3-39
BASIC INPUT-OUTPUT
DMAC,
interrupt
from a device,
the
it
When
DMAC receives an
the
HOLD signal. The HOLD signal will suspend the microprocessor, and
place
It is said to
"float"
its
buses.
It
receipt of the
released.
HOLD-acknowledge,
then automatically
place an address on the address bus, which specifies the memory address at
which the data transfer is to take place.
connected to 8 I/O
devices will contain 8 16-bit address-registers for this purpose. Naturally,
It will
A DMAC
DMAC
This
is
DMAC
DMAC
word-transfer,
the
counter
declamented.
is
to 0, or
The
whenever the
data-transfer
stops
DMA
The advantage of a
is to guarantee the highest possible transferspeed for the device. Its disadvantage, naturally, is to slow down
the operation of the processor. The
is a very complex device whose complexity is analogous to the one of a microprocessor.
It is also expensive, since
DMA's do not sell in the same quantities as microprocessors. In many
DMA
DMAC
DMAC
DMA
Motorola 6800
appears on Fig. 3-41. The
controller shown
on Fig. 3-41 is a cycle-stealing
controller. The address-bus and the
R/W float up to 500 ms. However the maximum duration of the suspension
may not exceed 5 microseconds, as the dynamic registers of the 6800 would
DMA
DMAC
RQ
DMA
76
S\
4\
*n
^DB-7
-MSTB
HF&
:>.
-HEN
cs
*:
CONTROL
ADDRESS
DATA
BUS
BUS
BUS
BASIC INPUT-OUTPUT
g_40
Intel
DMAC
77
DATA BUS
S
MEMORY
PIO
DMJI
ADDRESS BUS
TR/W
TxAK
TxRQ
READY
mm
REFGRT
3-41
CS/TxAKB
R/W
2
DMA
RESET
"1
TxRQ 2
78
Motorola
DMAC
S>
>
DMA
TRI
STATE
ADBRESS BUS
DRIVER
RAM
ROM
COUNTER
Hi
DMA
WORD
COUNT
REGISTER
6800
ADDRESS
TRI
DMA
STATE
DATA
DRIVER
SOURCE
R/W
DBE
<
DMA
TSC 1
CONTROL
CLOCK 02
16-bit counter.
is
The maximum
illustrated in Figs.
transfer rate
The
is 1
Intel
on
Figs. 3-40
and
is
shown on
It
It is illus-
Am 9517
of
3-44.
DATA BUS
3-42
BASIC INPUT-OUTPUT
343
4 Channels of 8257
SUMMARY
The
in this chapter. In
The
80
done
in
Chapter
4.
the
11
14
DWA.S
MAS
-3*
AM
<0
20
/0
9J.SJ.
fc
=}EISW
i k*
azsJL xBLlsia?
IF
*.
oo
>
<l7Qff
Z2l
WW
<<.
-V>
town*
^>
/woi
ADSTfl<r%
*W|J!
<
WW3W
ADEN
u u
mm
S3
-Ida*
iV-^U,
*P*<*
vol
ML1MK
Mor
AKEW
ootte
12
V W V W
U^>o-^|g
*
<^
}
3 -44
BASIC INPUT-OUTPUT
=0
Appendix:
TIMING ELEMENTS
'V,
OUTPUT
INPUT
OUTPUf
"
346
One Shot
Stretches Pulses
MUl.Tiri.EXED
<E>
347
82
Multiplexer Operation
348
RESET
+5
A15
*-
^>
3-49
r>
new A15
BASIC INPUT-OUTPUT
83
1T02A
PROM
L >-
input
output
jW
Code Converter:
Load Prom withBaudot to ASCII
ASCII to Baudot
EBCDIC to ASCII
ASCII to EBCDIC
or other converson
tables
3-50
address
check
i\
A8-al5
ROM
PROM
Interrupt on
Sof+ Tnil H^-h^n-h
)
25L,
low
>
-RD
data
Compart
^
^
A*\
B
i
'
>.
3-51
84
CHAPTER 4
PERIPHERAL INTERFACING
INTRODUCTION
Now
ing,
that the
how do we
What about
the
paper-tape punch, keyboard and telephone line? These are all peripherals
that allow the user, or another computer, to communicate with the system.
In this chapter, a number of common peripherals will be interfaced:
in
a matrix fashion.
new key
stroke.
Bounce
One
bounce
of the most
close, they
when
common
problems with a single switch is bounce. Keywhen the contacts of a mechanical switch
bounce
is
is
also true
switch contact.
85
KEY
DEPRESSED
LEADING
EDGE
BOUNCE
TRAILING
EDGE
BOUNCE
HARDWARE SOLUTION:
R-C FILTER
SOFTWARE SOLUTION:
4-1
The
solution
is
Key Bounce
may be done by hardware -filtering or by a softwareThe hardware circuit appears in Fig. 4-2 and requires the
20 milliseconds. This
delay routine.
same
circuitry for
switches
in
circuit
is
often used.
+5V
4-2
86
few front-panel
Debounce
Circuit
is
A Hex Keyboard
Non-Encoded Keyboard
Usually, the keyboard
n by
is
m key organization. We can scan one set of lines with a "walking one"
pattern and sense the other lines for a coincidence. (See Fig. 4-3). This
key-identification technique is known as "row-scanning." Once a coinciis found, it is checked for 20 milliseconds or
and then the corresponding data are generated.
dence
i "}
""
>
a
i
/
/ /
A'
/ / *\'
/ /
'
'
'
'
a
a
a
l<
'
'
IT]
T
<
>
a
i
4-3
11
I
<
'
stable
[71
'Y
J
l<
it is
OUTPUT
OUTPUT
|i
so, to see if
shows how
a four to sixteen line decoder allows for a 64-key matrix with four bits of
output and four bits of input from the microprocessor I/O ports. Fig. 4-5
87
16
>
bits
bits
|S
>
4:16
DECODER
ROW
SELECT^
16 x 4
KEYBOARD
i*
^
(
4-4
I0LUMN SENSING
to 16 Line
/A
F 8
3^-
>*-
*2-
CQL0
>*-
>*
4-5
Rollover
Rollover
the
88
same
is
time.
when more
is
held
down
at
from being generated. The three main techniques used to resolve this problem are the two-key rollover, the n-key rollover, and the n-key lock-out.
rollover provides protection for the case
Two-key
Two
closure
detected.
is
The
last
key
to
The
is
simplest two-key
until
philosophy
is
first
key
is
pressed. Clearly
N-key rollover
down, or
every key
keys
in
order to
is
that
significantly
and
significant cost
is
Any
additional
keys which might have been pressed and released do not generate any
By convention
codes.
it
may be
left
the
down
first
will
generate the
pushed.
it
must be
fully released
pressed down.
Line-reversal Technique
The
on
keyboard
is
method can now be used. This is the line-reversal technique. This method
will use a complete port on a PIO, but will be more efficient soft-warewise (faster). This method is illustrated below. In the example, a 16-key
keyboard is used. One port of the PIO is dedicated to the keyboard
interface. The identification of the key is performed in essentially four
instructions only. In practice, some more instructions may be needed,
because of the specific structure of the PIO used.
Step one: Output
Initially, the
8 lines of the
PIO
are configured as
lines in,
and 4
lines
89
KEYBOARD
INT
out.
the
row inputs
illustration,
to the keyboard.
may be used
As an
90
OUTPUT
ii
'
'__'
_J
'
1
1
INPUT
1
1
l_.
. _j
PIO
At
is
perform
sion technique, to obtain the code corresponding to the key. In addition, if more than one "zero" is present either in the first "nibble"
91
key is pressed.
The advantage of this technique is to require a very simple software
program, and to eliminate the circuitry needed to scan rows. The disadvantage is to dedicate one port of a PIO to keyboard management.
However in view of the very low cost of PIOs, this can be indeed a very
until only a single
inexpensive alternative.
Encoded Keyboard
Not everyone enjoys writing the software required for keyboard encodVarious types of LSI interface-circuits are used to encode keyboards.
ing.
Usually, the circuit will scan the matrix, discover a coincidence, provide for
Some
rollover,
an internal
With
this
in the
or
EBCDIC.
display interface
Keyboard Encoders
The basic role of the keyboard encoder is to identify the key which has
been pressed and to supply the 8 bit key code corresponding to it. In
addition, a
described above.
static encoders,
scanning
In
linear
keyboard
is,
is
keyboard which
then easy.
The
However
this
is
pulse
then
means 64
by 8 keyboard, only
the key
The
price paid
is
8.
ASCII keyboards
92
In an 8
in
(full keyboards)
view of the cost of every
No
key.
scanner
is
However most
Scanning-Chip
As
long as no key
is
scanned
is
when
in turn
using a
by using a
is
is
generated,
and scanning stops. The counter can be read: it identifies the row and
column on which the key has been pressed. Such a straightforward scanning
first
When two
in close
was pressed.
is
encountered.
identified might
better scanning
mechanism
scan the entire keyboard for key closure and will generate a valid code
will
only
will
is
if
pressed.
is
advantage of providing
intrinsic
is
is
pressed,
it
6 -BIT
COUNTER
'
'
J
DECODER
ROW-
CLOCK
OSCILLATOR
'
OF
" Mr : j ''
f
'
''
'
<
'
!'
SCANNING
/\
^
i
OF
_
8X8
KEYBOARD
DE-
CO-
Scanning
The above
If all
Keyboard
umns.
DER
it is
at the
same
time,
it
would be impossible
93
closure.
The
counter
used.
The top
is
to 8
decoder and are used to activate sequentially each one of the 8 columns
turn.
bits
in
to 8
decoder which
is
is
the 8 rows are scanned in turn. Then the next column is activated.
Whenever a key-closure occurs, the detection will occur whenever the row
is selected, and this will stop the six-bit counter. The contents of the
counter can then be read. They identify the column and the row which
Good keyboard-encoders
memory which
They should
are pressed.
7(PARIT>
6
5
ROM
4
)
CODE
SHIFT
~~
CTRL
STROBE-
LATCH PROVIDES
the
NECUPD
illustration 4-6.
It
trol oscillator,
94
shift,
+ debounce, frequency
control,
and
con-
WiYAViYn
z,
-.-.:... -..,
NEC
4-6
It is
90 keys
bit
ROM,
It
provides a
0-bit
It
is
ring
output for
in 4
10 matrix.
Keyboard Encoder
its
memory
mask programmed
or
to provide
ROM
can be
such as ASCII
EBCDIC
This device
may
be used
in a
during the bus. The data ready line can be used to flag the processor
keystroke
is
when a
ready lo be read.
4-7
ASCII
Keyboard
95
Intel 8279:
KEYBOARD
MATRIX
8 COLUMNS
8 ROWS
'RFTURN
LINES
5V
w
a-BiT
MICROPROCESSOR
SYSTEM
DATA
BUS
2L
SHIFT
CONTROL
R8-7
V DD
TJT1
RESET
of 8
DECODER
"1
SS
IOR
IOW
ADDRESSi
BUS j
3F
S 0-3
8279
CS
C/D
C/D ?
CLK'
A0-
BLANK
DISPLAY
$
$
1L
h/
of 16
DECODER
TOdkES!
Aiironyy
(DECODED)
DISPLAY
CHARACTERS
DATA
DISPLAY
4-8
matrix with
shift
this
generated. For example, pressing control and shift and the letter
be one of
the.
"p" would
codes.
In addition to encoding the keyboard, the device will also scan a display
and
data stored
in
RAM
bank
in the
8279
ASCII Keyboard
Keyboards may be purchased with the standard teletype or typewriter
ASCII code. These keyboards contain
the keys, plus the LSI keyboard-controller chip. The output is usually
layouts that generate the seven bit
seven parallel
bits
UART and
input, a
clock
may be
To
added.
The complete
design appears in
Fig. 4-11.
The
or
96
UART takes the seven bits of data and transmits them in a serial
11 bit
format
when
The keyboard
is
10
locked-out
CASH ORAW
KEY SWITCH
TOTALS
AUDIO INDICATOR
8748/8048
PROM/ROM
RAM
I/O
TO OPTIONAL
TIMER
z: COMMUNICATIONS
INTERFACE
TV"
READER
STORE AND FORWARD
-N
\s
-\
DATA 1 STROBE
STEFFER MOTOR
CONTROL
FAFER ADVANCE
8279
KEYBOARD DISPLAY
STATUS
a2_
Az.
MATRIX FRINTER*
WITH FAFER
ADVANCE
(SPLAT
I8IB18I
TAX
"fc-
ETC.
4-9
BIT NUMBERS
1
'
'
b7
>6
*>5
*>4
b3
*>2
hex
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
rv
NUL
DLE
SP
SOH
DC1
STX
DC2
ETX
DC3
EOT
DC4
it
ENQ
NAK
ACK
SYN
BEL
ETB
BS
CAN
HT
EM
10
LP
SUB
11
VT
ESC
12
PP
PS
13
CR
GS
11
SO
RS
15
SI
US
4-10
<
>
DEL
ASCII Table
97
while transmitting.
The
is
serial
bit rate.
it is
For 110
tuned to 4800
hertz.
EIA driver
S1883
data lines
from keybd
timerbaud-rate
oscillator
strobe
B1J_ B2
Baud-rate selection
ASCII Keyboard
4-1
Serial Interface
LED DISPLAYS
Light-emitting-diodes (LED's) are
Three of these
are: single
LED
LED,
displays
seven-segment
LED, and
dot-matrix
LED
displays.
The single
ing
LED
on the type.
or infrared
is
It is
light.
are red
.2 to
shows an
LED
bit.
is
off
98
LED.
its
intensity.
volt supply.
al-
orange,
to flow,
sS
NPN
Transistor
TTLIN
5-(Vd + Vcesat )
I
4- 1
Seven-Segment
LED Interface
LED
seven-segment
LED's
Single
LED
**-*
4-13
Seven Segment
LED
With these segments, we can display the numerals through 9 and some
of the alphabet. In this way, we have a readout of the seven drive
letters
signals.
It will
99
LED
USES
SEGMENTS:
r
/
r~7 _/
r O n n
/
o u u
n /_ r
r r
u u r
/
7 Segment Characters
LED's
the
An
BCD
output port
may
An example
is
the 7447
4-14
before a
serve a
new
may be
digit is selected
number of
displays.
multiplexed.
Each
LED
digit
digit is
Two
are
presented here:
Fig. 4-15
how
100
shows the
first
is
because,
digit
when
multiplexing, each
o
z
CM CO
t- -
n t--00000'i-000t-'*-'-0
"
o^-t-oo^oo
T-T-^T-^0 ^^-^
"O
0^0^^0^
t~ t
"^'
t" t
T~'r
"
09
"
~^
T" ,
A 0Ot-^0t-t-t--^t-t-
m
0-0t-0'-000'-
"O
"
t" t" t~ t
a
K
>
S
oo-*-ot-t-oo--o--
oooo- ^--oo--'--
s
z
>
i-XXXXXXXXXXXXXXXXOX
-1
Ill
-1
CD
<
Z
H
T-CMCO^inWt-COOOr-CMCO^WjggtDECIMAL
OR
FUNCTION
D
DC
1-
101
display must be
circuits
cannot provide
it
it is
Most
times as large.
on 1/N
integrated
must be
used.
BCD
T0
7
/-SEGMENT
DECODER
DATA
<r
<p
<r
,,
SEGMENT
DRIVERS
p<pjp
vv
'p
ip
v w
'P
if
ip
ip
ip
IT
DI
I
TZ
DIGIT
SELECT
ip
DIGIT
DRIVERS
4-15
Multiplexing LED's
The second scheme, in Fig. 4-16, uses a counter to advance the digit
The count is input to the processor and used to address the proper
data for the digit. The data are placed on an output port which drives the
count.
is
needed
to increase the
brightness.
4-16
102
Matrix
LED
on
Fig. 4-17.
ROWS
AO
D
D D D
D D D
R6
D D Q
D D D
A8 A9
a n
A1J
r-r-rr-
CHARACTER
TO BE DISPLAYED
DATA
C4
crr
DECODER
-TL
4-17
7 x 5 Dot Matrix
COUNTER
LED
CLOCK
OUTPUT
PORT
zr
OUTPUT
!=>
4-18
PORT
Counter Multiplexed
7x5
Matrix
LED
103
The
first
output port selects the column data and the second output port
grammed
The counter
will start at
and count to
They
through row
be generated
1.
Column
this
R6 to RO:
The row data
are from
counter to column
Column
4.
The
1001 lll a
are
character-
ROM
is
being
now
1001001 2
way.
typical
character-ROM
is
shown
the
This continues
may
in Fig. 4-19.
Summary
of Displays
There are many other displays. However, LED type displays are reliand illustrate the techniques used in most all other
display interfacing techniques. CRT-interfacing will be covered also in this
chapter, and the dot-matrix methods will be presented in that section.
able, easy to interface,
OUTPUT ENABLE
BLOCK DIAGRAM
4-19
104
Dot Matrix
ROM
S25261
CHARACTER FONT
ASCII SET, VERTICAL
SCAN
7X9 WITH
CODE CONVERSION
ROM
Dot Matrix
TELETYPE
A teletype is a serial mechanical input-output device which usually operbaud depending on the model and manufacturer.
will be presented here: one for a UART, using
interfacing
of
Three methods
for
a Motorola ACIA, using a model 33 Teleone
Teletype,
33
model
a
ates at 110, 150 or 300
type with opto-isolation, and one RS232EIA interface. A model 33 Teletype operates at 10 characters per second. Each character is encoded by
eleven
rate
is,
bits:
one
start bit, 8
data
bits,
The
and 2 stop
bits.
The
resulting transfer
problem
is
to
105
may
SET TO:
-20 MA LOOP
1-FULL DUPLEX
-H>o
4-20
UART
sequence.
interface
shows how
STOP1 STTJP2
MARK
"""I hl ? lllMl7hl
SPACE
9.09 ms -
'
MSB
LSR
'
4-21
Serial
Data Format
DATA READY
RECEIVE FROM TTY
READER RUN
TRANSMIT
LOAD
TRANSMIT TO TTY
Rl
4-22
106
Timing of UART
the
TTL
by the
TTY.
In Fig. 4-23
from the microcomputer system. This requires that the + and - 12 volts
levels also be isolated from the microcomputer. The ACIA performs the
conversion and interfaces directly with the 6800 bus.
5V
|4-]2V|
2K
Rx DATA
<
'
6850
.+5V
ACIA
+12V
Tx DATA
{>>^\A
1-
1N33
4-23
In
Opto-Isolated
TTY
Interface
with
EIA-RS232C
integrated circuits.
package so a number of
lines
4-24
in
a serial configuration.
may be
illustrates a
common
set
in
each
interfaced.
107
NEXT 1
LDA A STACON
LOAD STATUS
ASR A
BCS FRAM
ASR A
FRAM
OVRN
PAR
DATA
ASR A
BCC NEXT 1
BR ERROR 2
ASR A
ASR A
BCC OVRN
CHECK FE BIT
BR ERROR 3
FRAMING ERROR
ASR A
BCC PAR
BR ERROR H
ASR A
BCC R DATA
CHECK PE BIT
BR ERROR 5
LDA B TXRX
RTS
NEXT
LDA A STACON
(1)
LOAD STATUS
ASR A
ASR A
BCC TX DATA
ASR A
ASR A
TX DATA
BCC NEXT
CHECK CTS
BR ERROR 1
CARRIER LOSS
STA B TXRX
RTS
To
When
108
comes
in,
two
all
will occur,
They each
trip
The next
eight bits
come
in,
paper.
The
comes
punch was on, the selection of the
enough time
along.
print-bars
on the
The
distributor.
distributor
is
an au-
The motor
is
engaged to turn the commutator once around, which opens and closes the
loop generating the
key.
TTV DISTRIBUTOR
4-25
Distributor in Teletype
Note that the synchronous motor is the timing source for the machine,
and an accurate line frequency is necessary, or else the machine will lose
sync due to old age, no oil, or other mechanical problems.
109
ENTER
ENTER
"
SET BIT
COUNTER TO
ELEVEN
SEND START
BIT
<r
SEND DATA
BITS
OUTPUT
A BIT
v
DELAY
MSEC
SEND STOP
BIT
1
9.1
DONE
EXIT
YES
4-26
ACIA
RET
Transmit Software
TJB.liJB.Tii'E
OUTPUT 3UBR0UT1 NE
BIT
0)
DELAY:
DLO:
DL1:
110
MVI
MVI
DCR
JNZ
DCR
JNZ
RET
I10
WAIT STATES)
D,6
E,2000
e
DL1
D
DLO
1.5 MSEC
INNER LOOP
8080
a counter.
The contents of
set to 11.
It is initially
shifted out,
i.e.
will
be decre2. It is
bit
be ignored. This
bits will
register
transmitted to port
is
Initially the
accumulator contains
the 8 bits to be transmitted. In addition, both the start-bit and the stop-bit
must be transmitted. This will be accomplished by using a feature of the
The
of the accumulator, in
carry
bit,
is
which
is in
shift
0.
This
will
0.
be the
then be
start bit.
The
accumulator were simply shifted left, the left-most bit would be lost. In this
gets written in bit
is preserved in the carry, while a
position 0.
It will
in the
be noted,
has been done, successive rotations will rotate into the left of the accumulator successive ones created in the carry bit. This will guarantee that
the stop bits get transmitted at the end.
The sequence of
the program
is
straight forward:
TTY TX DATA
430/W
PORT 2
Hardware
4-27
The counter
register
is
TTY Connection
performed:
cumulator.
RAR.
is
set to 0.
This
will
occurs:
delay.
The
delay-routine
start bit.
A right rotate
bit position
ms
be the
is
of the ac-
implemented as subroutine,
111
and appears
at the
RAR
bit.
The
carry
is
is
transmitted.
The
bit-counter (register B)
is
executed to
set in anticipation
of
be correctly
TRANSMIT
ROUTINE
YES
READ STATUS
^>
CTS =
LOSS OF
CARRIER ERROR
ROUTINE
4-28
ACIA
Flowchart
goes directly to
we
the
1
ACIA
so
it
into accumulator
must be
A.
shifted twice to
ACIA.
If the
was
ACIA
to send, the
clear-to-send, a carrier-loss
112
NEXT
LOAD STATUS
LDA A STACON
ASR A
ASR A
BCC TX DATA
ASR A
TX DATA
ASR A
BCC NEXT
CHECK CTS
BR ERROR 1
CARRIER LOSS
STA B TXRX
STORE CHARACTER IN AC I
RTS
ACIA
BRANCH TO ERROR R
Software
PAPER-TAPE-READER
The
4-29.
JV."^
I+BV
}-(
IR
ONE OFF
MOTOR DRIVER
TOR
^^
MOTOR TO DRIVE
4-29
PINCH ROLLERS TO
113
Our microcomputer must turn-on the motor, sense a feedhole (which are
smaller than the data, indicating the center of a bit frame), sense the
framepattern and store the data before the next feed-hole passes by. When
an
end-of-tape character
8
is
ooooo
oo
oooooooooooooooooooooo
o
o
o
o
o
o
ooo
4-30
FEEDHOLES
8 Level Bit
Frame
A bit-frame for our 8 level tape appears in Fig. 4-30. A typical problem is
caused by the ragged edges of the holes, or by dirt on the tape. The hole
data appears on Fig. 4-31. Due to this, the feedhole sensing might
need
some
extra delay so that the middle of the feedhole will be the time at which
ji
4-31
Hole Data
LINE PRINTER
Usually, a teleprinter
is
files.
In this case, a
line-printer
To
on
Fig. 4-33.
READ
TAPE
TURN ON MOTOR
(NO TAPE
IN
REACTOR)
READ
IN
IN
TABLE
DATA, STORE
IN
MEMORY
Reader Flowchart
4-32
mm
FLATTEN
STEPPER
MOTOR
PRINT HEAD
xsssssssxsssssssx
HEAD
POSITION
STEPPER
MOTOR
1
I
I
I
4-33
It]
heaq pos|T|ON
SCREW SHAFT
115
To move the head and platen, stepping motors will be used. These
motors can move by a small amount, each time they are pulsed. Some are
accurate to over 1000 steps per rotation. The ones used here will have
32
steps for the head-motor, and 32 steps for the platen-motor.
Each character printed will be on a 7 x 9 dot-matrix. The head will step
once to put it at the next character position. The print wires will print the
Then
The process will
The head
wires
finished.
When
is
next
character.
solenoids
PRINT HEAD
wmw
Print
Head
SCREW SHAFT
Detail
But wait the platen is no longer at the top of the character. To prevent
unnecessary stepping, the whole row of the tops of characters will be
printed before advancing. The same will be true for each row of dots.
Because of this, we will need to buffer a complete line before starting to
print.
pseudo-graphics
the
full
range of platen steps. Fig. 4-34 illustrates the flowchart for the
printer interface.
The program will advance to the new line starting position after checking
enough data is present to print. The program will then print dot row by dot
row each character on the line.
if
One
were to
116
damaged
is
PRINT A LINE
1 STEP
STEP HEAD TO
LEFT MARGIN
FIND BEGINNING
OF NEW LINE
STEP PLATTEN 10
STEPS UP
(1
CHARACTER/
LINE)
CHARACTER
SET
PRINTER TO
FIRST
CHARACTER
INITIATIVE
POINTERS
SET
ROW COUNT
TO
FIRST
ROW
4-34A
6
may be damaged. To
prevent
this, special
This
illustrated for
is
charge
dump
one solenoid on
Fig. 4-35.
When
When
fire.
117
PRINT DATA
CHARACTER
POINTED TO
INCREMENT
CHARACTER
COUNT
^^^LASl
<
^V^
CHARA
NO
INCREMENT ROW
COUNT AND SET
CHARACTER COUNT
BACK TO THE FIRST
4-34B
DONE WITH
+ 24
LINE
VOLTS
CHAB.GING RESISTOR
1
IT
4-35
Change
Dump
Solenoid Driver
118
CAPACITOR
4-36
Stripe
Reader
119
The diode
when
it is
field in
shut-off.
is
most
common
in the
new
point-of-sale terminals.
inexpensive, has few moving parts and the interface can be done mostly
with software routines.
It is
MAGNETIC-STRIPE-CREDIT-CARD CARD-READER
One
encoded
interface.
The program will control the decoding of the information on the stripe
and the movement of the card in the reader. In normal operation, the card
will
be sensed
We
assume
is
If valid, the
may appear
that
the card
down.
^i_ru^r^_^-LJTj
4-37
Recorded Data
and then
and
be written three times in a scrambled form, with
various parity checks and heading, and trailing blocks of ones or zeroes.
security, data should
OUTPUT
OF
COMPARATOR
CONDTTIONER
-TLTiSU
4-38
120
Final Data,
L_J
LTU
Filtered
If
it is
The
it
it
and
in
read, end-of-card sense (reverse motor to return); and two outputs: motoron (automatically will reverse, unless turned-off), and serial-data-to-bewritten. Thus, one half of a 6820 PI A or 8255 PPI will be sufficient input-
out hardware!
long-term storage
necessary.
is
recorder can be used without modification to store and load digital information.
The
interface required
scribed here
in
is
the
KIM-I
is
interface to a cassette-recorder.
The format for transmission will need to convert the binary information
memory into a serial stream of bits that can be recorded on the tape. The
The
signals for a
"1" or a "0"
are illustrated
on
Fig.
4-39.
9 PULSES
9 PULSES
6 PULSES
JlMJUUUulRMJuTJUUmnnJTRjrL^
9 PULSES
6 PULSES
LOGIC
6 PULSES
juuuijuuuuuuijijir^^
LOGIC
I
4-39
Bit
BIT
Format
for
KIM-I Cassette
MOS
INTERFACING THE PERIPHERALS
Recording
121
The program
will
face and
ROM-chip on
one output
bit
inter-
When
a tone
may be decoded.
Fig. 4-40
is
PB7
*!
l
e-JW\r-rJWV-pM^--]
CONT
4-40
122
Note
that different
densities.
Because
different timing
all
means of modulation
is
done
in
software,
scribed here
U-100
"
fJ
R
L8
(16H)|2A H ,| C
|
|
1
|H8|
1
441
The
i{
H
'
Av -.
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1
|
1
'
>
RECORD
and
come
any
the start-of-
record character, and record-number bytes. After that, the starting address
hexadecimal
is
written, as well as
SC/MP
latter).
Cassette Interface
Peripheral decoding
cuit
Figs. 4.41.5.
123
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124
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128
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IDENTIFICATION
ADDRESS
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LENGTH
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WORO
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PROGRAM
X'AS
PROGRAM
(X'820C)
(X'820A)
(X'8203)
(X-8204)
(XB20D)
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BYTES OF
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BY BLOCK TRANSFER
ROUTINE
V
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137
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139
NEC
The
UPD371D provides in a single chip most of the functions
required for interfacing a digital cassette-transport. It uses the
ISO format
and performs:
Parallel-to-serial
and
serial-to-parallel
normally accomplished by a
data-conversion
(functions
UART)
It
on one
in
to
unit, or
on 4-41.7.
i__i
MO-D87
R(
F==l
INPUT/OUTPUT StiT.
REAP DA TA iwceiTiwri
Fig. 4-41 .6
140
SAMfLIHG
UTf
rt
Interface
o-
-o
-0-
rtiffl
-o-
&
-0-t>-
-0-0
-t=
v}"
-O<--t>
;_n."'
rr- b
_.zT
TIT
Fig. 4-41 .7
141
critical
in the
is
the
home
television-set.
Higher
We
will
television-type display.
Fig.
The
4-42
The
signal
fed from the antennae into the tuner, which outputs a video i-f frequency,
at 4.5 MHz. The signal is fed into a filter-amplifier which is
transformeris
It is
fed to a
filter, in
is
directed to the
sound
142
i-f
amplifier (4.5
MHz)
The
signal
CRT through
The
FM
is
is
the video-signal
then
split
three
sound-carrier
is
fed to a
as
(horizontal) sync,
and
(vertical) sync.
on the screen.
two
points:
it
of the
RF
modulation method
The output
is
that
it
FCC regulations,
the
RF
modulation
the limit
The
number of characters
total
itself.
naturally that
is
few
sets are
is
we
requires a
it
equipped with an
will
on color
US.
display characters
on a screen.
30 Hz
OR
262.5
OR
60 Hz
512 LINES
PER FRAME.
or
Fig. 4-43
15,750 Hz
(B&W)
15,735 Hz
(COLOR)
TV Timing
143
other
side
of the
screen,
while going
down one
line.
This
called
the
"horizontal-fly-back" phase. It is illustrated on Fig. 4-43.
Two types of
scan are used, called respectively the direct-scan and
the interlaced-scan.
In the interlaced scheme, the screen is scanned twice.
The second scanning,
or field, is made on lines between the previous ones.
262.5 lines are available in each field. An interlaced scheme therefore
provides 525 lines per
frame. In the case of a
display connected to a microprocessor, the usual
is
TV
used to
provide
TV
line.
first
The
dot reaches the end of the display-time, it goes black. The time
from the end
of the display-time to the line-sync is called the blank-time.
(See Fig. 4-44.)
SCREEN SIZE
I2\
LINE SYNC
/
flyback
*^""
VERTICAL
FLYBACK
>
^-3-
BLAflK
DISPLAY TIME
BLANK
J
l
L!
SCREEN
OVERSCAN
144
Fig. 4-44
TV Blank Time
SCREEN
OVERSCAN
Generating Characters
called a
Characters are represented on the screen by a pattern of dots
characters. The
dot-matrix. Two standard formats are used to represent
used is the 5 x 7 dot-matrix. A lesser-used system is the 7
most frequently
x 9 dot-matrix. The advantage of a 7 x 9 dot-matrix is a better definition of
Howcharacters, and a more pleasing representation of lower-case letters.
this
for
and,
ever, a 7 x 9 dot-matrix requires the use of a high bandwidth,
character
each
reason, is much less used. A 5 x 7 dot-matrix represents
by a
with 35 dots. It uses 7 rows of 5 dots, and each character is represented
The
dots).
"black"
sequence of dots and un-dots (blank dots or rather
TV
of
a
scan
Each
4-45.
representation of characters is illustrated on Fig.
line will
the line.
of
present on the screen the five dots belonging to all the characters
and
characters,
these
for
Then, it will present the next row of dots
on the
so on. At a minimum, a 5 x 7 dot-matrix will require eight lines
pracIn
characters.
the
between
screen, since one blank line must be used
tice, for
good
CHARACTER
ASCII
CODE
ROW
ADDRESS
a
A0
CHARACTER
Al
GENERATOR
A2
?
ROW CODE
~~ZZZ
._
*ZJZ zzz
zZi *zzzz
zz^._
(5x7
Fig. 4-45
dot matrix)
145
ROM
output.
CHARACTER
ADDRESS
TO 8 BITS
CODE
CHARACTER
>
i>
GENERATOR
VIDEO
OUTPUT
IF
CURSOR
EDITOR LOGIC
Raster Generation
frequency,
of a refresh-memory.
fast, that
DMA
turers,
MOS Technology,
146
that can
is
is
limited
x 7 dot-matrix
will usually
be selected,
The
up to 16
line will be perhaps 43 microseconds. Displaying 32 characters in 43 microseconds will leave us approximately 1 .3 microseconds per character. This
80 characters per
required for the
line,
memory.
If
we were
using
memory.
LATCH
I
CHAR
GEN
III It
n
i>
tl
""
ii
SERIAL
OUT
LINE SELECT
Fig. 4-46
The
line.
The
7-bit
ASCII
is
presented on the
left
of the
character-generator on the illustration, and the three line-select lines, appearing at the bottom of the character-generator, specify which one of the 7
rows of the dot-matrix is being output on the right. The five dots corresponding to the row contents are then gated into the shift-register, and are
147
into a
composite video
signal:
2.
3.
the cursor
4.
finally the
and
Sync
signals.
is
illustrated
on
Fig. 4-47.
JL
Si
^lr
ANALOG
IS
IS
Fig.
SWITCH
and
The sync
signal
is
tip.
is
Its
illustrated
duration
is
on
Fig. 4-48.
4.7 us. It
is
followed by the black and white dot signals encoded as a voltage swing
between .5 and 2 volts. The timing appears on Fig. 4-49. On a standard
television, white is 100% level, black is 25 to 30%, and sync is
0%. Typical
voltage swing
is
is
45 us.
or
through an
illustrated
148
RF
on
Fig. 4-50.
is
TRANSISTOR
TV
INTERFACE
LEVEL
LEVEL
1.562
GRAY
(OPTIONAL)
Fig. 4-48
DISPLAY ON SCREEN
(FLYBACK)
2! to 30%
25
j
I
V7us
18.34s
45.7us
RIANKTIME
LINE TIME
I""
Fig. 4-49
'
TV Timing
VIDEO
OUTPUT
CHARACTER
GENERATOR
TV VIDEO ENTRY
RF
MODULATOR
Fig. 4-50
Video vs
RF
TV ANT ENTRY
(RF)
Entry
149
MEMORY TIMING
DOT
COUNTER
32 or 64
COUNTER
*- 10 or 11
Character
Refresh
Memory
DMA
DMA
DMA
DMA
itself, line
will start
is
buffer
emptying
itself
through the
DMA
DMA
DMA
DMA
exclusively for
croprocessor
150
memory
itself.
refresh,
USING A
u P
MEMORY REQUIRES
LINE BUFFERS
ft
^^-\ LINEBUF2
Fig. 4-5
One-Chip
CRT
1MPU Requires
p'
Line Buffers
Controllers
RAM
page-buffer. This
RAM
page-buffer
may have
a size of
2K words
or more
of 80 characters.
The
CRTC
CRT's
in
ROM
downstream logic which has been described, including essentially the shiftregister and video output. The use of such a typical CRTC is illustrated on
Fig. 4-52.
feATA 6US
31
NPU
TO
CRTC
31
IE
PRESS BVS
3E
!^> zC>
x
REFRESH
TIMING
RAM
=T7^>
:>
BUFFER
iz
LP
*.
--
V|
Fig.
4-52
CRT Controller
CHARACTER
GENERATOR
REGISTER
OUTPUT
Block Diagram
151
The
CRTC
character-generator, the
refresh address for the
and
RAM
It
Programmable features
register,
light-pen
register,
and
are:
R/W
RS
CS
i
E
"n
R0-4
RESETLPSTP
"
CURSOR-*-
D0-7
A0-13
SS
HSYNC
BLANK
^S DATA
BUS
REFRESH ADDRESS
CC
Fig. 4-53
152
row count to
character
----(ROM)
VSYNC
Vgen
6ENERAT0R
DCLK-
Q5
'_
> to
m>
to
can
a:
uj
3=*="
->-
75 UJ I ;
S
["
t
*
<=>
Li-
7S
n
CD
X
X
O
LU
5
S\ /%
CO
CM
i
C9
=>i
r->
fc
OO
*-*
o
I
CD
oxx
easr
zr
cc
3:
szszir
ou
dquioujov)o:<
I
Fig.
4-54 Using
153
The
Intel
CRTC
8275
CRTC
a 5 x 7 or 7 x 9
will interface to
all
The
basic
As
usual, the
CRTC
(CM0/CM2 inputs on
(COMP SYNC, VRT SYNC).
pulse generation
It is
Fig. 4-54)
It
and sync
programmable:
scroll input)
(this is
line
rate
Other output
DLC0-3
signals are:
is
it
character.
LDV
"loaded video".
is
It is
register.
Blank
Blink
is
is
As an example,
on
C MO-CM 1-CM2
Fig. 4-55.
FLOPPY DISK
simply a disk coded with a magnetic material, and divided into sectors
is
recorded.
It
large capacity.
Two
types of floppy
lowing
sume
facilities: (It
SHUGART
SA800 provides
154
the fol-
We
as-
PO WER
FORMAT
SELECT
5x7/7x9
scroll/page
MTX
A2
A3
A5
A6
A7
A8
A9
A10
RR
CURSOR
MOTION
CM2
CMS
CLOCK
CP
RESET
MR
AUTO
LINE FEED
miTE ENABLE
WR
CURSOR
10TION STORAGE
)ATA ENABLE
WE
FS0
FSl
FS2
SCROLL
60hz/50hz
WRITF RFQUF^T
DE
fc
DLC0
DLCl
DLC2
DLC3
LDV
CRSR
FLG
AL
Fig. 4-55
BLINK
BLINK
BLANK
BLANK
COMP SYNC
COMPOSITE SYNC
VERT SYNC
VERTICAL SYNC
CRTCPinout
CM2
CM1
CM0
UP
RETURN
LEFT
HOME
DOWN
NEW LINE
RIGHT
FUNCTION
DE OUTPUT IS LOW)
Fig. 4-56
Cursor Functions
155
Fig.
156
INDEX.
PREAMBLE 46 BYTES
26 SECTIONS
Fig. 4-58
In
IBM
Floppy-Disk Format
kilobits.
kilobits/sec.
is
The access
times are:
track to track: 8 ms
Average access time: 250 ms
Settling time: 8 ms
The head load time 35 ms.
The rotational speed of the disk
is:
(inside track)
is
is
3200 bpi for single density, and 6400 bpi for double
density.
is
48
tpi
is
77.
characteristics are:
capacity:
Unformatted: 109.4 kilobytes per disk and 3125 bytes per
Formatted: Two cases must be distinguished: soft-format
track.
and
hard-format.
157
Fig.
158
4-59
3.25
in
(82.6mm)
Size of Mini-Floppy
Fig.4-60
In a hard-format
ning of the
new
punched on the
disk, to
punched to indicate the beginning of every track, but the length of sectors on the track is
left up to the designer, or the programmer.
The
The
sector. In a soft-format
Hard
72.03 Kbytes
2058 Kbytes
128 bytes
Sectors/track: 18
16
is
access-time
is:
Track-to-track: 40
Average: 463
Settling time: 10
Density
is
total
ms
ms
ms
loading time
Rotational speed
The
is
Soft
transfer-rate
The head
is:
is:
75
ms
300 rpm
number of
Track density
is:
tracks
is:
35
48 bpi
159
Capstan
Base Casting
Mounting
Plate
Fig. 4-61
Head Positioning
Double-sided Floppy
Detail of
Mechanism
for
drive.
The
disk
Life
8000
is
POM.
Errors
10
Hard:
Seek: 10
rating are:
"
Soft:
10'
Consumption
is:
15 watts
is
160
is
12
in
standby
is
illustrated
on
Fig.
4-62.
Permanent Label
Temporary
ID Label
Index
8.00
Holes
Drive
in.
Spindle
Hole
(200mm)
Write
Protect
Notch
fl
6.25
(159mm)
in.
8.00
in.
<
(200mm)-
SA 104/105/124
Write
Protect
Notch
5.25
in.
(133mm)
3.93
in.
(100mm)
-5.25
Fig.
in.
(133mm)-
The
1.
2.
The
drive
3.
The
4.
The read
(2
PC
boards)
mechanism
mechanism
write head
161
The
above, include:
circuits
circuits
Accessing a Track
It is
moved
along a radius of the disk by a stepping motor. In order to access a track, the
following sequence will occur:
1.
2.
movement of the
head.
its
The head
will
move
periphery.
movement, no
writing should
occur.
4.
Reading
is
Writing
is
accomplished by:
162
is
data-line.
DRIVE
SELECT
SA 400
MOTOR ON
DIRECTION SELECT
STEP
WRITE GATE
TRACK 00
INDEX/SECTOR
WRITE PROTECT
READ DATA
(CLOCK + DATA)
WRITE DATA
SA 400
Fig. 4-63
+12V
+5V
Floppy-Disk Drive
The
SA
communi-
MOTOR ON
The
motor on, or
off.
When
after activation.
commands
life
of the drive.
DIRECTION SELECT
This input selects the direction
will
in
will
be
line.
STEP
This moves the head by
it.
away from
WRITE GATE
Write
is
is
enabled
when
Read
is
specified
when
the line
inactive.
163
TRACK
The
i.e., its
00
commands
additional step
are issued.
INDEX/SECTOR
signal is issued
holes
may be
whenever a hole
is
sensed
in the disk.
Two
types of
first
is
When
soft-sector
is
is
When
sector.
11
per revolution.
_ __
I
._
_-|
RECORDED
Fig. 4-64
Recording
_^
|OXIDE RECORDING
BIT
A Bit On A Disk
_M_R_R_R_R
'
BIT
BIT CELL
CELL
I
Fig. 4-65
164
'
Tl_
CELL
BIT
2
Disk Formatting
Both clock and data information are encoded into the same signal. Clock
bit. A "0" data is indicated by no further pulse
is
in the
illustrated
on
middle of the
Fig. 4-65.
"1"
is
indicated
UNIQUE
UNIQUE
RECORD
10
10
Fig. 4-66
Record
OTHER RECORD(S)
Identifier
Soft-sectoring refers to the fact that the division of the disk or track into
sectors
is
is
is
is
started
by a physical index-pulse,
preceded by a unique
separated by gaps.
identifier.
Gaps
speed variations
in
all
or
DATA:
(HEX:B)
Hexadecimal F
Fig. 4-67
Identifier
Format
165
DATA
CLOCK
FC
DT
ID ADDRESS MARK
FE
C7
FB
C7
DELETED DATA AM
F8
CT
ADDRESS MARKS
INDEX HOLE
GAP
IQ
GAP
GAP 3
PRE
(18)
17
18
USER DATA
128
BYTES
ID
track! SECT
ADDR
MAj AUDR | ADDR
CRC
CRC
16
Fig. 4-68
CRC
SYNC
GAP
166
(BYTES)
21
17
20
For
this reason,
between any two zones which might be updated separately. Most often, the
IBM disk-track format is used, sometimes with minor variations. This format is illustrated on Fig. 4-68. Four kinds of gaps are used:
Gap
at the
Gap
It
is
and
"FF"
It is
It
appears
first
is
used
at the
followed by 4 bytes containing "00". These four bytes of 0's are the
classical
way
length of gap
may never
vary in length.
The index-gap
is
The
followed by the
ID
1 is
first
record.
It
sum
field.
The
CRC
ID
check-
sector-address provide a verification that the right track and sector have
WRITE SIGNAL
READ BACK
Fig.
4-69 Timing
167
Gap
field
is
from
called the
its
data
field.
uses 10 bytes.
It
It is
The
The
first
identification
length of gap 2
may
file
updating.
The first record, or data-field follows. It uses 131 bytes (see Fig. 4-47).
The first bytes contains data or deleted address-mark. It is followed by the
actual 128 bytes of user data.
sum
It is
CRC check-
bytes.
Finally,
Gap
uses 18 bytes.
3 terminates the
The
first
record.
It is
"FF", and
first
and
the four
last bytes contain "00", for the sync. Every successive record
on the disk,
or sector, will start with ID, gap 2, and so on.
Hard-sectoring
When
is
punched
hole
is
then
started by a physical sector pulse. In the case of the mini-floppy disk, two
configurations are used: 16 sectors of 128 bytes or 10 sectors of 256 bytes
per track. The track is started by the index pulse. This is illustrated on Fig.
4-70.
X,
V6ECTO
SECTOR
ECTOR
INDEX
N -
16
N =
10
12.5ms
- 20ms
Fig. 4-70
168
SECTOR
,2
SECTOR PULSE
This corresponds to the case where the data being written on the disk is
not written correctly. The way to verify whether data has been correctly
written
is
is
read again
during the next revolution of the disk. Normally, the user will simply write
again data which has not been correctly written on the disk, and attempt to
Read
Errror
Two
is
transient
and
is
step in
its
Hard: Whenever usual correction procedures fail to read data from the
it must be deemed unrecoverable. This is a fatal error. Data is lost.
disk,
SEEK ERROR
This corresponds to the case where the head does not reach the correct
can be verified by reading the ID field at the beginning of the
track. This
Whenever an
error
is
is
detected, the
The head
is
moved
issued.
DETECTING ERRORS
Universally, the error-detection for any data written on a disk
complished by
(CRC)
bytes.
is
CRC.
used for
The data
G(X) =
using
this
a check-sum
is
ac-
Cyclic-redundancy-check
purpose. Each
X 16 + X 12 + X 3 +
It is
method.
written in the
1.
two bytes
division
is
When
is
called the
reading back
CRC bytes.
1 69
Fig. 4-7
170
If the
is
not
0,
an error
and
CRC's
disk-controllers
(FDC)
CRC
Motorola 8501,
One-chip floppy-
-1
L_ D
>FF
r->FF
-i
*>FF
Fig.
Cyclic
is
the favorite
is
method
memory
areas
CRC
Detail
tion,
Redundancy Check
CRC
CRC
4-72
it is
in the
often used
technique
is
is
word
are treated as
is
called here a
dummy
is
interpreted as B?
X +
1
X +
7
X6
Bo X.
variable.
= X7 + X2 +
Be
1.
171
<
>*~1
<L
>"
4_
1
'
>*
ac
u-
<
4_
T*
I
X-H'
a.
4_
'6
f
fi
Fig. 4-73
172
CRC
used.
divided by
this
generator G(X).
the quotient
is
to
append to a
bit string
an
extra byte (or bytes), equal to R(X), so that the total string will be exactly
divisible by the generator polynomial. The above equation can be rewritten:
B(X) - R(X) = Q(X) G(X). The string formed by B and the remainder R
string B are
is exactly divisble by G(X). The extra bits appended to the
CRC bits (or bytes). When receiving for the first time a string B,
CRC generator will compute the remainder R which will be appended to
called the
the
the string.
When
CRC
bits will
exactly divisible by the generator polynomial G(X). If they are not, an error
has been detected. If they are divisible, no error has occurred, or else a
As
usual, the
in software.
grammed CRC,
The program
Summary
of Disk Operation
The complete principles of floppy-disk operation have now been presented. The signals necessary to drive the disk, its operation, the formatting
of data, as well as the error-checking mechanisms that must be implemented. We will now describe the implementation of a disk-drive controller to
Example: The
SHUGART SA
This controller-board
controller chip. It
will
is
designed to control
be
mini-floppy controller.
the
is
new
FDC
Then
show the
capabilities of a full
chips.
This controller
is
IBM
shorter). It provides a
173
DEFINITION OF SYMBOLS
EQU
EQU
EQU
EQU
EQU
EQU
EQU
PROCESSOR REGISTERS
H'08'
H 01
'
'
PSL:
1=WITH,0=WITHOUT CARRY
CARRY/BORROW
BRANCH CONDITION UNCONDITIONAL
EQUAL
TABLE OF POLYNOMIALS
CRCF0
CRCF1
CRCR0
CRCRI
CCIF0
CCIF1
CCIR0
CCIR1
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
H'10
H'02
H'20
H'01
H'08
H'10
H'01j
CRC16 FORWARD
CRC16 REVERSE
CCITT FORWARD
CCITT REVERSE
H'08
BEGINNING OF SUBROUTINE
CRCGEN PPSL
L0DI.R2
L0DA.R1
EORA.R0
TEST
CK0
CK1
SHIFT
CPSL
TMT.R0
BCFR.EQ
PPSL
EORI.R0
E0RI.R1
WC
8
CRC+l
CRC
C
H'80'
SHIFT
C
CRCF0
CRCF1
RRL.R1
RRL.R0
BDRR.R2 TEST
STRA.R0 CRC
STRA.R1 CRC+l
RETC.UN
INITIALIZATION
OPERATIONS WITH CARRY
INITIALIZE BIT COUNTER
GET OLD REMAINDER LSB
EX- OR OLD REMAINDER MSB WITH DATA
CLEAR CARRY
TEST MS-BIT OF R0
BRANCH IF NOT A '1'
PRESET CARRY
APPLY 'FEEDBACK'
RAM AREA
CRC
ORG
RES
END
H'500'
2
Fig. 4-74
174
CRCGEN
READ:
READ
disk
track
WRITE:
AM
SA 4400
Controller
1
"^
Status
Busy
MPU
Xfer
SYSTEM
FDCOn
o
DISK DRIVE
Command
Acknowledge
Halt
Reset
Fig. 4-75
The previous
three
commands
Interface Signals
will
processor and the disk-buffer, or between the buffer and the disk.
in
status for
The
signals used
1.
Seek
2.
Find sector.
3.
Shift
4.
Check
track.
CRC.
Few commands
commands
most
only.
175
I&&
i.
Ph
a.
In la
ttUlllltUlti
IX
5 S
Uttttft
IS
IS
g 3
Fig. 4-76.
176
FDC
FDC
is
naturally
formatter
IBM
will interface to
3740 compatible.
It
most
provides:
on
all
FDC's.
an
be standard on
FDC.
or multiple records
automatic sector search
entire
in
an
FDC.
programmable controls:
track to track stepping time
head-settling time
head engage time
three-phase or step-plus-direction motor-control
DMA or program transfers
alert reader will notice that all of the
The
standard for
all
FDC's. The
essentially
number
The
will
be described
six registers,
interface.
in detail
will
It
and a floppy-disk
now be examined.
The
interfaces: a processor-interface
and two
Each
now.
FD1771B
Circuits
the CRC
which generates the check-character.
the ALU (Arithmetic-Logical-Unit), which was used for the obvious
logic
compare characters
for incre-
will
be described below.
1 77
O
O
q go:*:
o o. q. >
u. _)
$?
a
(=5
(
te
fe
LU
1-
rf+
\\
O
W U_Q
-.UJ
UJw</>
l-t
CM Q_
Q.
If
Fig. 4-77
'
'
'
la
'
<
Q
'
Z
o
(23
a:
TV*
178
oo f
a-
Ci
Q_
LU
II
3=
q oe > uj
FD 1 77 1
From
1.
left
floppy-disk data-line.
2.
the data-register
is
write operations.
buffer,
and may
re-
is used to hold the 8 bit command being exeloaded by the programmer and specifies the mode
The command-register
cuted. This register
is
4.
The
5.
disk),
6.
It
Processor Interface
The
request
data-request-output
(INTRT)
is
(DRO)
is
DMA.
The
interrupt-
RATE
(COMMAND WORD)
BIT 1
BIT
!
1
Fig.
4-78
PERIOD (MS)
(STEPS/S)
166
166
125
10
100
Command Word
Bits
179
A 1
1
1
RE
WE
STATUS REG.
COMMAND REG.
TRACK REG.
TRACK REG.
SECTOR REG.
SECTOR REG.
DATA REG.
DATA REG.
Fig. 4-79
Register Addressing
The signals appear on the right of illustration 4-77. They provide headpositioning controls, write controls, and data-transfers.
The clock is a
head-settling time
is
Disk Operation
A read-operation
on the disk
is
performed
in five steps:
1.
Load
2.
3.
Wait for
4.
5.
Check
the track-register
verification
Conversely, awrite-operation
1.
Load
2.
3.
Wait for
4.
5.
Load the
6.
7.
Check
180
is
number of transfers.
performed
in
seven steps:
the track-register
verification
first
BUSY
and CRC-error
flag
is
received.
PROCESSOR INTERFACE
UPD372
-WRITE DATA
HLO
-HEAD LOAD
SELECT
LCT
LOW CURRENT
WFR
REGISTER SELECT 2
WE
REGISTER SELECT
SOS
SELECT -
SID
STEP
UBI
REGISTER WRITE/READ
REGISTER
SELECT
COMMANDS
REGISTER
INTERRUPT REQUEST
DATA BUS
DBS
OBI
DATA BUS 2
DB2
DATA
BUS S
DBS
DATA
BUS
OAT* BUS
DATA BUS<
IN
OR DIRECTION
UBS
UA1
DISK
UAB
COMMANOS
ORIVE Al SELECT
READ CLOCK
-REAO DATA
DB4
0B3
IDX
OATA BUS 6-
DB6
WFT
OATA BUS 7
087
Tea
-TRACK ZERO
WRITE CLOCK
DISK ORIVE
DATA BUS 5-
T0
"\
./DISK DRIVE
INDEX
WRITE FAULT
RYA
RYB
.DISK DRIVE
STATUS
m CLOCK STATUS
CKS
AWL
"
ALWAYS LOW
VOO
TT
Fig. 4-80
NECUPD372FDC
181
Fig. 4-81
182
NEC 8080
Disk Controller
UI4
UPD372D
*=:
ifc:
r<J-
-rlsrO-
C-tNT*
RESET
c-t^a
unsAK
4TSJ5Til
zS**{-InTA
|ffl
^ READY
=B>-
Inras
Jam MTA
LIST
MUTT NO.
CK IP
OTT
1
|K>3720
tPDT.101AI.-4
UTO2J04
2
2
1
4
2
3
7400
7404
740*
741C
7430
7432
7474
74123
74123
74137
743C3
uPOtOtO*
||PM2I(
UP6K24
PM2M
M02
RESISTOR
NETWORK
spwmueno.
14C13IXS7*
Fig. 4-82
NEC 8080
TOTAL
Disk Controller
183
Summary
The FD1771D illustrates how it is possible to integrate most of the
functions required for the control of a regular floppy-disk into a single chip.
It provides essentially all the facilities needed to control and format
the
disk.
OTHER
FDC's
The NEC FDC is called the UPD372D. It is compatible with the IBM
3740 as well as the S
ART mini-floppy. It provides the usual facilities,
such as CRC-generation, programmable step-pulse, track-stepping rate,
HUG
the others.
CAL COMP
ORBIS
74,
SYCOR
145.
are:
CDC BR
140,
PERSCI
75,
803,
GSI
PERTEC
FD400,
Fig. 4-47.
The Motorola
This
FDC
6843FDC
is
macrocommands
1.
Seek track
2.
Seek (SEK)
3.
Single-sector- write
4.
SSW
5.
6.
Read
7.
Multiple-sector-write
8.
Multiple-sector-read
9.
Free-format-write
10.
184
INNOVEX 210,
POTTER DD4740,
(STZ)
(SSW)
CRC
(RCR)
Free-format-read
(MSW)
(MSR)
(FFW)
(FFR)
(SWD)
It
provides 10
RS0
I
DATA OUT-W
RSI
I
RS2
CS
R/W
'
READY
(RDY)
SET-UP-W
I
in
I]
I]
SECTOR ADDRESS-W
D7
Tro
CLOCK
BUS DIRECTION
FI
DIRECTION (HDR)
HEAD
LOAD (HLD)
WRITE GATE
(WGT)
CRC CONTROL-H
CD
(DM
RESET (FIR)
HEAD
I
M
I
INTERRUPT STATUS-R
RESET
-STEP (STP)
GENERAL COUNT-W
ERROR STATUS-R
END
ZERO (TRZ)
MA
INDEX (IDX)
TRACK
CAPSTAN STATUS-R
DATA IN-R
VFO
CONTROL (VFOC)
+6V
-GND
Fig. 4-83
It is
for settling-time.
three
The
KPS
Format
for seek-time
It
maximum
MPU
load
MPU
is
and
FDC requires
DMA channels.
suming 256
Register
time. As-
12.5%.
The
Fig. 4-84.
It
uses three
refreshes channel
1.
The
DMA
FDC
FDC
in
in Fig.
4-86. Typical
floppy disk routines for the Rockwell PPS-8 appear on Fig. 4-87.
185
Fig.
186
4-84 PPS-8
FDC
TT77
Fig. 4-85
PPS-8FDC
(=5
187
01550000
NOOP
01550001
START
01550010
LOAD
01550011
CLEAR
1 S S 1
READ DATA
OlSSllOO
1 S S 1 1
1 S S
1 S S 1 1 1
NOOP
-
OOOOIOOO
Fig. 4-86
188
READ STATUS
NOOP
1 S S 1
READ STATUS
UNDEFINED READ
READ INTERRUPT STATUS
Commands
CPU ENTRY
SERVICE ROUTINE
POWER
HEAD MOVED
INITIALIZE \ TO TRACK
TINE
SERVICE ROUTINE
9 ^
SYSTEM
"\
REGISTERS
INITIALIZED
FDC
GENERATED
COMMAND J
S
in.
LOAD
^/COMMAND/
V
/
ENTER FROM
DMA BLOCK
TRACK /
SECTOR/
SET
INTERRUPT
FORMAT
/
I/ACKO
Automatic/
IS
~EL\
/
UP
DMAC
)
\ CHANNEL /
STANDARD
CPU STORES
PPS-8CPU
REGISTERS
IN HACK
restart
FROM
"RETRY"
"Vjy
/ OUTPUT
"START"
TO FDC /
PROCESS
APPLICATION
UNTIL
INTERRUPT
_J__
r~
UCOMMAND
/
commanc
7/
INTERRUPT
SERVICE
FDC
7 RESPONDS
/ READ
/INTERRUPT/ WITH
/ STATUS /
ADDRESS &
LOAD ROUTINE
,r
i__
.
'
ROUTINE
TRACK MOTION
AND HEAD
VQ
FROM FDC
CONTROL
(NEWFDC
ON
CPU INTERRUPT
1>
TO FDC
CONTROL
STATUS
CPU RETRY/TERMINATE
SERVICE
DISK
OTHER
OPERATION
NOT
COMPLETE
SERVICE ROUTINE
INTERRUPT
v^WHY""
y^
DID
TO CPU
INTERRUPT
SERVICE
ENTER ERROR
PROCESSING
SUBROUTINE
RETRY
DISK
ROUTINE
OPERATION
ROUTINE
DISK
OPERATION
COMPLETE
RETURN
TO
INTERRUPTED
PROGRAM
3=1
c
EXIT
l_
Fig. 4-87
Software Flowchart
189
190
CHAPTER 5
ANALOG TO DIGITAL
AND DIGITAL TO
ANALOG CONVERSION
INTRODUCTION
In any system,
must be measured, or generAnalog signals assume a continuous range of values, whereas digital signals assume only a finite number of
values. As an example, a binary signal is a digital signal which assumes one
of two values, either "on" or "off ("1" or "0"). A typical example of an
ated.
They
signals
analog signal
is
The temperature,
number of intermediate
infinite
values.
The
is
said to be
will
be presented
below.
We
will
consider successively:
a D/A converter
a A/D converter
the sampling process
analog multiplexing.
real
(or
real
(or
DAC)
ADC)
collection system.
A CONCEPTUAL D/A
Let us consider the problem of converting a binary number into an
analog voltage. This
is
19 *
simple solution
is
For example,
bit
The
is
bit-
is
proportional to
will generate a
bit.
will
voltage 2V(2*); bit 2 will generate a voltage 4V(2 2 ); and, bit n will generate a
voltage 2n
x V. The
The
result
is
simple 4-bit
D/A
appears on Fig.
5-1.
This
D/A
proportion
1, 2, 4, 8.
This results
in gains of:
this circuit.
OPERATIONAL
AMPLIFIER
V
A Simple 4-Bit D/A
5-1
Let us begin with all the switches in the open position. Since there is no
input to the operational amplifier, the output will be "0". Closing the bit
"0"
switch numbered
will
apply the
-10V
to the gain of
-A
X
at this point).
The
resulting output
is
10.0
is
5.0
3.75V. If
2.5
all
1.25
we have converted
into a voltage. It
is
We
192
will
now examine
D/A
converter.
Practical
The
D/A
monolithic
D/A
summed
converter. This device has four bits of resolution. Practiinstead of voltages, due to the fact that currents
on and off accurately. To provide a voltage output, the
of the converter
done by an operational
is
is
have eight
easily
bits
of
resolution.
DATA
LINES
v
BIT
SWITCH
BIT SINK
r~r
RES. NET
A Practical
5-2
Converter Schematic
They
are:
The
The
The
R-2R
is
The R-2R
established by
its
position
on the
_n
resistor-network produces a 2
The
series
the current either to the bit-sink bus, which connects to the current-to-
ANALOG CIRCUITRY
A/D
193
voltage converter
ampere,
or to ground.
Uo ampere, Vso ampere, and Vieo ampere. These elements combine to perform the conversion from a 4-bit binary number into an analog
voltage.
LOGIC
INPUTS
nil
"
BIT SINK
NIK
SWITCH
REFERENCE
CURRENT
OUT
nn
LADDER NETWORK
5-3
1
o^o
q^o
]/
ON "V
ALL ^
1
0^0
rt>
EMITTEBlS
+
]/2oV
5V
100
i^SV
200
VW-r
-10V
5-4
194
qSo
1/40 | 1/80
100
..25V
100
t.625
~
ICO
-10V
An
current between the bit-sink bus to the amplifier and ground. Fig. 5-4 shows
When the
a logic "0", which corresponds to 0V, the bit-sink will draw current
is
Q4 to the bit-sink bus. When the input is a logic "1", which corresponds to an input voltage greater than 2V, the bit-sink will draw current
through Q3, instead of Q4, disconnecting the bit-sink bus from this sink bit.
through
The
four binary signals will switch the four bit-sinks on and off the bit-sink
bus.
The
resulting current
is
'
FROM OTHER
SINKS
Detail
By extending
tors,
we can
Any more
the
R-2R
The
Bit Switches
more bit-sink
more than
transis-
10 bits.
cannot overcome. In
fact, 16-bit
an accuracy of
remember
cali-
part in 65,000!).
Real Products
real
D/A
ANALOG CIRCUITRY
195
TABLE
5-5
D/A Converters
Type#
Manufacturer
MCI 408
Motorola
PMI
PMI
Datel
Burr-Brown
300ns
DAC-08
DAC-03
AD7520
DAC-4Z12D
DAC70/CSB
Analog Devices
Speed
Resolution
100ns
10
250ns
10
500ns
12
lus
16
75us
THE A/D
Now
that
an analog
signal,
it
into a binary
we must
first
sampling.
Sampling
The
binary
one point
Fig. 5-6,
in time.
This
is
known
indicated.
The sample
samples which
waveform,
We must collect
The frequency
**time
5-6
196
Infrequent Sampling
in
at
which
accurately
The answer
lies in
average frequency.
Fig.
in
We must sample
we must sample
5-7
illustrates
As
our system.
at least 10
the
results
at least twice
a rough rule, in
of more
frequent
sampling.
Frequent Sampling
5-7
The analog
time
it
input to a converter
using a sample
and hold
sample
must be
This device
may be accomplished by
will
it
in
and hold
the
in
allows us to converge towards the correct value of the analog input signal.
In Fig. 5-8,
we have connected
UNKNOWN
COMPARE
D/A
converter to the
IF LESS THAN
1 IF GREATER THAN
MSB
ANALOG CIRCUITRY
LSB
-
A/D
197
signal.
bit.
Fig. 5-9 illustrates such a guessing procedure for our 4-bit converter.
procedure
is
known
sion.
-JUL
INPUT
.625
1/2
GUESS
5-9
Using
TIME
this
the binary
A/D
.6875
conversion.
function in hardware.
The
other alternative
is
to
198
complete
OUTPUT A BIT
TO D/A AS A
YES
OUTPUT TO SAME
BIT AS BEFORE
A "0"
SIGNIFICANT
GO TO NEXT
LEAST SIGNIFICANT BIT
5-10
monolithic
A/D
approximation-register,
is
illustrated
in
Fig.
5-12.
Besides successive-
ANALOG CIRCUITRY
A/D
199
ANALOG
INPUT
TO +10V
CLOCK INPUT
2.25 MHZ
A/D
5-1
Using a
SAR
<
OOS9
"
!
O DB8
+rr-L
D8
ososv
ffs
OSRO
+~
COW
a
,,,,.8$
g;SS
8SEN
OLBEN
OSYNC
FTTl
IgVcc
5-12
200
O HBEN
strt
ctK
DGND
Vpo
Monolithic
A6N0i
A/D
INTEGRATION
The second way of performing
integration.
unknown
it
is
analog
voltage,
voltages
is
known
reference.
charge to reach "0". Fig. 5-13 illustrates the timing diagram of such a
technique.
CHARGE
TIME PULSES
1000
1000 + N
INPUT VOLTAGE
Integration Timing
5-13
known
voltages,
as
it
quad slope.
In addition to
more accurate.
ANALOG CIRCUITRY
A/D
201
wmm
5-14
DIRECT COMPARISON
Direct comparison
is
in
is
required. Usu-
contains
comparators (where n
binary output word desired). Let us examine
is
the
how
number of
this
bits in the
works.
comparators below the fifth one are on, and all above it are off, then
the
priority encoder will encode the eight inputs into a 3-bit
binary number,
00a. Other inputs will be encoded into other 3-bit
representations.
Such systems provide a resolution of five bits in less than 100 ns per
1
conversion.
complex
The need
priority
for anything
However,
$50 that
202
will
beyond
AMD
perform
3-bils
of resolution.
comparison
in less
than 50 ns.
PRIORITY ENCODER
V REF7
Output Control
\V7Vx
^^
8 to 3 Priority Encoder
ANALOG CIRCUITRY
A/D
203
TYPICAL DEVICES
Table 5-16 lists examples of conversion devices and the technologies
used to implement them. In general, the faster the conversion,
the more
expensive; the more accurate, the more expensive; and, the more
external
TABLE
5-16
A/D
CONVERTERS
Type of
Type#
Manufacturer
Resolution
Speed
National
MM5357
40us
PMI
AD-02
AD7570
8us
10
18us
ADC-EK12B
12
AD7550
13
24ms
40ms
Analog Devices
Datel
Analog Devices
A/D
Conversion Cost
SA
SA
SA
$10
$70
Integrating
Integrating
$25
SUMMARY
The
three techniques of
tegration,
ules.
The
A/D
and
converter
is fast,
converter
is
of
but with
medium
little
in-
moddirect
The successive-approximation
accuracy.
the time
maximum
most time
to
Interfacing the
D/A
204
is
needed. This
is
word
easily
shows such an
may be
8 BIT
D/A
ANALOG OUTPUT
DATA
BUS
A
^t.i
STROBE
8 BITS
5-17
Parallel
HIGH
DATA BUS
J\
LATCH
13 BIT
MSB
JS
~v
V
LOW
J\
LATCH
LOW
HOLD
5 HIGH
BITS
J\
LATCH
D/A
LOW
BITS
5-18
is
a problem.
When
the
first
some microseconds
later
we change
latch
new
is
loaded, the
D/A
convert-
needed bits for the D/A. The effect causes a glitch on the D/A output
because of the input change. All input bits to a D/A converter must be
ANALOG CIRCUITRY
A/D
205
changed
at the
indicates
how an
same time
in
extra latch
added
D/A
essor.
is
The 74LS374
octal latch
is
ANALOG
OUT
5-19
SC/MP D/A
Interface
(DA 1200)
1
206
Interfacing the
As D/A's
A/D
A/D
port. In addi-
tion, the
The A/D
Five
A/D
for processing.
interrupt basis.
MM5357 A/D
converter.
The
device has
an end-of-conversion
The
start-conversion line
(SC) may be activated from an output port bit, or it may be tied to the
end-of-conversion signal (EOC). If SC is tied to EOC, as soon as a convercomplete, a new one will immediately begin. The end-of-conversion
can be connected to an input-port bit, so it may be polled. EOC can
also activate an interrupt input, depending on the software considerations.
sion
is
signal
8-BITS
OUTPUT ENABLE
SC
EDC
CLOCK
+5V
-12V
-5V
The
5-20
MM5357
Converter
Fig. 5-21 illustrates the use of an A/D converter, where the status of the
conversion can be read on the data bus, without the use of bus drivers, or a
separate input port. The Analog Devices' AD7550 accomplishes this by
ANALOG CIRCUITRY
A/D
AND
D/A CONVERSION
207
low byte, high byte, and status outputs. The only signal required
is
the start-conversion signal, which must be generated
from an output port
for the
bit.
8-BIT
1 1
DATA BUS
(DC
D7)
>
5-21
Most systems
inputs,
require
we can connect
comparator.
shows a technique
The peripheral
D/A
D/A converter
bit
be coded
in
208
DATA BUS
8 BITS
MM4357
r4LS04A OE
71
TE
S(
8205
D-
>
-i/o
rfl.
Four
5-22
MM5357 on
an 8080 Bus
*2-^>o-
V |N (FULL SCALE)
Mf
<RI
+ R2)
Pace
500
+5V
-15V
(FULL SCALE
OHMS
<?
VeE
VrEF(YF
TT
z=[>^-
10MPENSATION
(+5V)
30 PF
l-VN/V*
GN
V REF()
RANGE
A1A9A3AdARAfiA7 A
i
,,
,,
,i
,.
i,
CALIBRATION)
"R3
+5VO-W*-0-15V
+5V
10K
)
OFFSET
ca
HI
PB1
PAC
MPU/PIA SYSTEM
5-23
Using a
ANALOG CIRCUITRY
D/A
A/D
A/D
209
More Channels
need arises for more analog input channels, or it is too expensive
to
A/D per channel, another alternative exists for design. More
channels can be added through the use of analog multiplexing.
The multiIf the
have a single
sample inputs.
It is illustrated in
Fig. 5-24.
A/D
The
is
selected from
entire
A/D
many
system
will
OUTPUT
11111
A3
5-24
A2
A1
An Analog
A0
ENABLE
Multiplexer
The MP21
A/D
contains all necessary components to provide a comsystem for a 6800 microprocessor. The block diagram in Fig. 5-25
210
or 16 single-ended inputs.
address-bits and latched
The channel-number is
on a read-command by the
control-logic.
ANALOG INPUTS
???????? ????????
8 CHANNEL
ANALOG
8 CHANNEL
ANALOG
MULTIPLEXER
MULTIPLEXER
ADDRESS
DECODER
AND
CONTROL
CONTROL
LOGIC
LOGIC
GAIN
lOFFSET
INSTRUMENTATION'
AMPLIFIER
8=T
ADJUST
{amplifier
IA
OUT
POSSIBLE
R/W~
SAMPLE
AND
-o-l HOLD
HERE
CONTROL LOGIC
[HALT O*.
*INT
CH-
Q+|TRI-STATI
S=
8 BIT
OUTPUT
A/D
CONVERTER
6ia
a <
The
5-25
The
Internal
MP21 Schematic
conversion
ditional multiplexers
can be added
number
of input channels.
The
conversion.
is
the 8-bit
The end-of-conversion
A/D
ANALOG CIRCUITRY
A/D
will
AND
that the
D/A CONVERSION
module
211
will
ADDRESS BUS
v
W
I-
D
0.
z
o
o
RESET
17
VMA
45
40
VMA*
oo
NR/W
Q.
42
34
R/W o
5 02
46
37
02
IRQ
<NT
HALT
44
z 2u5 s
DATA BUS
5-26
Interface
There are two basic techniques for extending the resolution of our A/D
conversion without changing the basic accuracy of our A/D converter.
offset.
Scaling
If the input signal is 1.0 volts
we
volts,
ter,
more
the input amplifier in order to attenuate the input signal. This will allow us
to measure larger voltages than could otherwise normally be measured.
By
obtain
maximum
becomes
evident.
We scale
AID
the input to
converter.
Offset
By connecting the output of a separate D/A to the offset input before our
we could automatically correct for offset errors, or we could
amplifier,
212
in small
accuracy further.
changes around
this value,
we can
offset the
D/A
is then
by an equal and opposite amount. The
volts. Adding the two together, we get some small value which
depends upon the difference between the offset D/A and our input voltage.
Now, we increase the gain of the input amplifier so that any difference
between the input 10.0 volts and the offset 10.0 volts can be measured with
input
-10.0
the
A/D
accuracy of the
full
Summary
of
converter.
is
listed in
Table 5-27.
A/D OUTPUT
GAIN
OFFSET
IXXXXXXXXXXXXXXXXXXl
(+ 10 VOLTS)
x 1/2
+ 10 VOLTS
x 1
x 10
x 100
5-27
Of
Scaling, Offset
own
in the
SUMMARY
Our microprocessor can now be used to gather information, process it,
in a new form in the analog world through the
use of these conversion products. The D/A or digital-to-analog-converter
providing the microcomputer with the means for generating the analog sigand output that information
nals,
and the
A/D
measuring the analog signals, form the basis of any conversion system. The
use of sample-and-hold, multiplexers, and scaling/offset techniques, allow
us to quantify any signal, process
it,
and pass
it
back
in
require.
One
This
last constraint
will
be examined
may be to
in
ANALOG CIRCUITRY
Chapter
A/D
in
a standard form.
6.
213
ANALOG CIRCUITRY
214
A/D
AND
D/A CONVERSION
CHAPTER 6
BUS STANDARDS
AND TECHNIQUES
INTRODUCTION
Connecting more than one module requires a communication path. Each
module must be able to talk and listen to its neighbors. The components on
a module need to communicate with one another. The problem of component interconnection has been addressed in Chapters 2 and 3. The
techniques of module-to-module, and system-to-system communication will
be covered
Two
They
in this
bus types
will
be distinguished:
parallel
buses and
bit-serial buses.
are:
parallel
microprocessor SI 00 Bus
microprocessor 6800 Bus
IEEE-488 general interface bus
IEEE-583 CAMAC interface system
serial
munication
CAMAC
in the
case of IEEE-488.
standard covers
all
communica-
CAMAC
is
the
level
on up.
Serial
tions
lines,
all
on some form of
rely
cover
chronous.
communication.
and data
two types of standards: asynchronous and syn-
BUS STANDARDS
bit-serial
is
less
than
215
is
An example
PARALLEL BUSES:
Parallel buses transfer all bits of information across separate wires, at
same
the
time. Lines
must be provided
address-bus, and lines for the control-bus. Each set of lines contains infor-
16 address,
and
5-12
control lines.
The 8 data
The 16 address
transfer
lines
memory
is for.
determine what
lines will
line,
an interrupt
line,
DMA
line,
line.
In this basic system, the control bus will have the timing
Fig. 6-1.
ADDRESS
V////M
*x\\\\\^
VM
R/W
DATA MUST BE
DATA
V//////K
Ssr-<xs^^
MEMORY FETCH
ADDRESS
x^m
w///k
R/W
VM
DATA WILL REMAIN
DATA
J\^
W RISES.
J\
MEMORY STORE
6.1
216
a valid
shown
in
These 29 signals are all that are needed for most simple parallel buses.
Timing will vary, and separate read and write lines may be used, but all
buses function
a similar fashion.
in
Future systems
24 address
flexible input-output
THE
many
lines. In addition,
many
as
management.
BUS
S100
The "hobby-computer" market was revealed at the Atlantic-City conThe impact of one company, however, was greater
than most at the time. This was MITS, the producers of the Altair microcomputers. The bus they used in their 8080-based system had 100 lines.
Other manufacturers (in particular IMSAI) realized that making their
memories and peripherals compatible would help them sell in this new
ference in August 1976.
market.
Now
The bus signals and definitions are presented in Tables 6-2 through 6-8.
Some problems of this bus are: clock lines adjacent to control signals,
pin layout problems, and power supply distribution.
The Ol 02, and 2MHz clock signals are near nine other control signals.
,
fall
most
blow out;
well, let us
at worst,
power
if
hope
it
doesn't.
At
may
may be damaged.
distribution of voltages in
Variations in
ity
costing
difficulties.
The
solution
is
way to
own problems.
The interrupt
controller board
on the bus.
BUS STANDARDS
No
standard
way of using
these
an interruptis
established
217
THE
S-100
BUS (ALTAIR)
PIN
NUMBER SYMBOL
1
+8V
NAME
FUNCTION
+8 Volts
Unregulated voltage on
supplied to PC
boards and regulated
to 5V.
bus,
+18V
+18 Volts
Positive
pre-regulated
voltage.
XRDY
EXTERNAL READY
CPU
Board's ready
cir-
cuitry.
VIO
Vectored Interrupt
LineO
VI1
Vectored Interrupt
Line
VI2
Vectored Interrupt
Line 2
VI3
Vectored Interrupt
Line 3
VI4
Vectored Interrupt
Line 4
VI5
Vectored Interrupt
Line 5
10
VI6
Vectored Interrupt
Line 6
11
VI7
Vectored Interrupt
Line 7
12
*XRDY2
EXTERNAL READY
second
ready
New
line
external
similar
to
XRDY.
13
to
TO BE DEFINED
17
18
STAT DSB
STATUS DISABLE
6.2
218
Altair
Bus
PIN
NUMBER SYMBOL
19
C/C DSB
NAME
COMM AN D/CONTRO L
DISABLE
FUNCTION
Allows the buffers for
the 6 output command/
control
lines
to
be
tri-stated.
20
UNPROT
UNPROTECT
Input
to the
protect
memory
given
21
SS
SINGLE STEP
ADDRESS DISABLE
the
the process of performing a
single step (i.e., that SS
flip-flop
ADD DSB
on
board.
that
Indicates
machine
22
memory
flip-flop
in
is
on D/C
is
set).
23
DO DSB
24
02
PHASE
CLOCK
25
01
PHASE
CLOCK
26
PHLDA
HOLD ACKNOWLEDGE
Processor
control
command/
output
signal
to
the
HOLD
signal;
and
HOLD
after completion
27
PWAIT
WAIT
Processor
control
command/
that
appears in response to
the
READY signal
going
low;
indicates
processor will enter a
series of .5 microsecond
WAIT
READY
signal
states
again
until
goes
high.
BUS STANDARDS
219
PIN
NAME
NUMBER SYMBOL
28
PINTE
FUNCTION
INTERRUPT ENABLE
command/
Processor
control output signal ;
indicates interrupts are
enabled, as determined
by the contents of the
CPU
interrupt
internal
flip-flop.
flop
is
Interrupt
When
set
the flip(Enable
instruction),
reset
(Disable
it
Inter-
29
A5
Address Line 5
30
A4
Address Line 4
31
A3
Address Line 3
32
A15
Address Line 15
33
A12
Address Line 12
34
A9
Address Line 9
35
D01
36
DO0
37
A10
Address Line 10
38
D04
39
D05
40
D06
41
DI2
Data
42
DI3
Data
In
Line 3
43
D17
Data
In
Line 7
44
SM1
MACHINE CYCLE
In
(MSB)
(LSB)
Line 2
(MSB)
1
Status
output signal
that indicates that the
processor is in the fetch
cycle for the first byte
of an instruction.
220
PIN
NUMBER SYMBOL
45
SOUT
NAME
OUTPUT
FUNCTION
Status
output signal
that indicates the address bus contains the
address of an output
device and the data bus
will
PWR
when
data
is
active.
46
SINP
INPUT
output
Status
that
signal
PDBIN
47
SMEMR
MEMORY READ
is
active.
output
Status
signal
48
SHLTA
HALT
Status
that
HALT
49
CLOCK
CLOCK
to
output signal
acknowledges a
instruction.
02 CLOCK'
50
GND
GROUND
51
+8V
+8 Volts
Unregulated input to 5
volt regulators.
52
-18V
-18 Volts
Negative
pre-regulated
voltage.
53
SSWI
b)
BUS STANDARDS
c)
Disable
the
CPU
Board
Data
Input
Drivers (DI0-DI7).
221
PIN
NUMBER SYMBOL
54
EXTCLR
NAME
FUNCTION
EXTERNAL CLEAR
Clear
for
signal
devices
I/O
(front-panel
switch
closure
to
ground).
55
RTC
REAL-TIME CLOCK
60HZ
signal is used as
timing reference by the
Real-Time
Clock/
Vectored
Interrupt
Board.
56
'STSTB
STATUS STROBE
mary
purpose
strobe the
latch
to
is
8212
status
so that status
is
up as soon in the
machine
cycle
as
set
This
signal
used
by
Display/Control
logic.
possible.
also
is
57
DIGI
Output
rectional
DIGI
is
data
bus.
HIGH,
the
is
LOW,
FRDY
Output
if
the Display/
Control
logic
have control.
58
If
CPU
signal
drivers
from D/C
59
to
TO BE DEFINED
67
f
New
222
PIN
NUMBER SYMBOL
68
MWRITE
NAME
MEMORY WRITE
FUNCTION
Indicates that the data
on
present
Out Bus
into the
tion
is
the
Data
to be written
memory
loca-
on the
currently
address bus.
69
PS
PROTECT STATUS
memory
the
protect
the
memory board currently addressed.
on
flip-flop
70
PROT
PROTECT
board
currently
ad-
dressed.
71
RUN
RUN
/RUN
flip-flop
i.e., machine
mode.
72
PRDY
PROCESSOR READY
is
64
Reset;
is
in
RUN
to the
circuitry.
73
PINT
end
flip-flop
is
reset,
it
will
BUS STANDARDS
223
PIN
NUMBER SYMBOL
74
PHOLD
FUNCTION
NAME
HOLD
command/
Processor
control
input
that
signal
requests
processor
HOLD
the
the
enter
state; allows an
machine cycle.
75
PRESET
RESET
command/
Processor
control
activated,
the
of
while
input;
counter
the
content
program
cleared and
the instruction register
is
76
PSYNC
SYNC
is
set to 0.
Processor
command/
control
output; provides a signal to indicate the beginning of
77
PWR
WRITE
Processor
command/
78
PDBIN
DATA BUS
IN
is
is
active.
Processor
control
cates
circuits
bus
is
mode.
224
79
A0
Address Line
80
A1
Address Line
81
A2
Address Line 2
(LSB)
1
PWR
command/
output; indiexternal
to
that the data
the input
in
PIN
NUMBER SYMBOL
NAME
FUNCTION
82
A6
Address Line 6
83
A7
Address Line 7
84
A8
Address Line 8
85
A13
Address Line 13
86
A14
Address Line 14
87
A11
Address Line
88
D02
89
D03
90
D07
91
DI4
Data
In
Line 4
92
DI5
Data
In
Line 5
93
DI6
Data
In Line
94
DM
Data
In
Line
95
DIO
Data
In
Line
96
SINTA
INTERRUPT
ACKNOWLEDGE
(LSB)
INTERRUPT
97
SWO
WRITE OUT
Status
request.
output
signal;
ation
the
current
be a
WRITE memory or
output function.
in
machine cycle
98
SSTACK
STACK
Status
will
output
signal ;
99
POC
POWER-ON CLEAR
100
GND
GROUND
BUS STANDARDS
225
as Z-80's, 6502's (and even 6800' s) can also be used (and are used) in S100
systems.
The
far
more
than anyone will ever need of these, and suffers from being designed before
a system-controller chip
many
was made
of the signals are due to the original Intel problem with pin limita-
tions, as discussed in
Chapter
2.
Obviously, a
won't be
this is
why
it is
it
a standard!
The SI 00 bus is a practical bus, and will perform well in most applicaThe problems mentioned here should be avoided, when new bussing
schemes are being considered in the next few years for fu-
tions.
ture systems.
Mg
T
01
T
|
T
|
T,
,
J\
02
T.5-0
7-0
/
/
BYTE
ONE
STATUS
BYTE
TWO
\mSBM3./
^_
s~^.
PDBIN
PWR
STATUS
INFORMATION
SMEMR
6.9
226
T"
/STATUS
\_kSB _S/
PSYNC
Memory Read
SMEMR
Cycle on SI 00 Bus
The bus
interrupt
provides: 8 data
and 39 control
in,
lines.
use.
The data-bus has been changed from the normal bidirectional 8080 bus
two unidirectional data buses. One for data-input to the processor, and
one for data-output from the processor. In this system, there is no real
to
advantage to
together.
more
this, as
There
no
two buses
pins.
The address-bus
found
many
also
is
in
is
16-address-lines,
which are
The power-supplies
are
most
interesting.
15-0
7-0
PSYNC
PDBIN
PWR
\
STATUS
INFORMATION
6.10
BUS STANDARDS
wo
Memory
227
power
is
It is
simplified,
a good choice
and
is
it
tween modules.
The
example
at the
end of
this chapter.
Timing diagrams
is
for
discussed
in the
memory-fetch and
store cycles are presented in Fig. 6-9 and 6-10. They illustrate the basic
timing of the 8080 system, and the basic signals used for these transfers.
signals are
by these few
6800
all
memory
lines.
SYSTEM BUS:
Described here
is
was
well
The
lines.
data and address buses are quite the same as any other system's
needed.
control bus.
This bus provides clean, concise signals for fetching and storing information. It
and
<E>,
is
<1>1,
drive and 4>2-drive clock signals are present on this bus for no
high-speed clock
is all
that
One
well-isolated
to un-
IEEE-488-1975
This bus
is
and others can be equipped with a 488 bus. The 488-bus was a
years of discussion in the
228
IEC
result of three
(International Electrotechnical
Commis-
CLOCK: The
as
Asynchronous
Communication
Interface
Adapter
(ACIA).
RESET:
HALT:
The Halt
line
is
(RUN), the MPU will fetch the instrucaddressed by the program counter and begin program
execution. When the Halt line is low, all of the activity within
the MPU will be halted. The Bus Available (BA) signal will
then go high and the Read-Write (R/W), Address and Data lines
will all be in the high impedance state. With BA high, the front
panel addressing and data deposit functions will be enabled.
When
tion
R/W:
When
(READ), data
VMA:
is
written into
halted,
R/W
is
in the
low
state
MPU
(WRITE),
memory
will turn
VMA
The
bus.
DBE:
R/W-P:
Read/Write-Prime
The
signal
and 02.
BUS STANDARDS
61 *
is
enabled and
229
IEEE approved the IEC draft, resulting in IEEE-488Hewlett-Packard was one of the prime influences in the development
of this bus, and the handshake technique used is patented by Hewlettsion). In 1974, the
1975.
HPIB
is
sometimes called
(8)
^>
DATA
DAV
NRFD
BYTE
TRANSFER
CONTROL
NDAC
GENERAL
INTERFACE
MANAGEMENT
ATN
SRQ
REN
iz
iZ
5Z.
DEVICE A
DEVICE D
TALK
LISTEN
CONTROL
EX:
6.12
The
488 Bus
COUNTER
Signals
more of the
following:
controller
2.
3.
The bus
listener
talker
The
commands
bits).
Since this system has no address or complete-control buses, the data bus
is
used to perform
all
these functions.
The
how
it is
The
used.
The
are:
End-or-Identify.
230
Attention,
to eight bits.
when
When
command
or
seven-bit address.
known
state.
It is
similar to a
system-reset.
Service Request,
when
Remote Enable
sets the
mode
End-or -Identify
is
used to
end of a data
transfer.
The "handshaking"
function
is
"Please give
it
to
me,
line says,
"How
am
ready".
The
here
it
"OK,
is",
DAV
infor-
and
NDAC
to accept data).
by
NFRD
listening de-
The
DI01-8
(COMPOSITE)
6.13
Note how
next transfer
all
listening devices
is initiated.
BUS STANDARDS
If
it
appears complex
it is!
231
requires complete
Some
knowledge of
all
7>
7>
ATN
-EOI
-BYTE
-+XFER
-*. JDAV, NRFD, NDAC
I
iz
iz
&
IE
i_jl
SOURCE
-I
LISTEN
HANDSHAKE
7T
DEVICE
DATA
LAST
BYTE
INDICATOR
<:
6.14
Talker
7^
-*
ATN
*-E0I
BYTE
XFER
rr
6.1 4^
Listener
by using
command,
The
EOI
line
is
is
ATN
signals.
to indicate the
sent next
byte,
handshake
may be used
command-
recognizing
Upon
The
When
the transfer
The
is
command
is
its
lis-
by
The EOI
complete.
summary, the IEEE-488 bus represents quite an advancement in intelligent data acquisition systems. As more manufacturers produce compatible
equipment, the standard will become even more widespread. In fact, the
Commodore Business Machines home microcomputer system is equipped
In
232
computing as well as
may
new
indicate a
trend in
home
in industry.
The example presented here illustrates how a 6800 system can be interThe schematic appears in Fig. 6-15, and contains two
PIA's, bus transceivers, and some random logic for the control lines. The
RAM
ROM
data
LL
=>
data
)L_D[
address
TT
buffers
control
dJ
mode
switches
control
Ti
l_y_y_y_ y
6.15
6800
to
T-"l--
212L
488 Bus
-L-a|o-o>-
Interface
CAMAC
The IEEE-583
is
known
Automated-Measurement-and-Control-Standard or
cover
as the
CAM AC.
"ComputerThese also
The
is
is
the
tion, there are standards for the inter-rack bus: the "parallel
serial inter-rack
It
the
addi-
highway," and
was developed
CAMAC
is
and
all
domains of the
systems are
CAMAC
sub-unit.
It
CAMAC
"crate".
The
crate
is
BUS STANDARDS
The
233
6.16
234
HP 1600S
Analyzer
# a * * ate ** * ** ?
5
6.17
BUS STANDARDS
CAM AC CRATE
with Modules
235
-\
P p \.%* p p
*\
a
I
6.
236
CRATE and
Power Supply
size
all
specified.
Power-Supply
The power-supply
is
Remember
standard.
that the
all
covered
often ignored,
in the
is
the
most important unit in any system. Any flaws in the power supply will
show up everywhere else in the system. Thus, CAMAC does something no
other standard does: it guarantees the user that the power supply will be the
least of all problems in the system. Fig. 6-18 illustrates the crate and
basic
Dataway
The CAMAC Dataway bus consists of the following lines: three control,
command, five address, twenty -four read, twenty-four write, two timing, and four status. The lines are described in Table 6-19.
five
The
used to put
all
lines
all
known
These
signals are
state.
Some
The
32
read, write, and status transfers. Others are either reserved for future use,
or not defined.
write lines
is
informa-
tion. 24 bits allows for simultaneous transfer of three 8-bit bytes for efficient
systems contain microprocessors, these 24
operation. Since some
CAMAC
lines
could carry the address and data from the microprocessor. Since data
transfers
may occur
CAMAC
when data
The
are valid.
status lines are used to monitor the requests for service to the
controller
interfaces.
summary, the
all
It
It
cov-
conventions.
BUS STANDARDS
237
Designation
Use in Module
Sets registers or control functions in a module
to an initial state, particularly when power
Initialize
turned on.
Inhibit
Clear
Commands , addressed
Function codes
Fl,2,l,8,l6
Addressing
Station number
Al.2,4,8
R1-B21*
W1-W2U
Timing
Strobe 1 and Strobe 2
S1.S2
Status
Look-at-Me
Q-Response
Command Accepted
Busy-
6.19
238
Dataway
Signals
SERIAL STANDARDS:
one or two wires to carry all necessary
between modules or systems. In order to transmit address, data, and
control, they must be sent bit by bit.
Serial transmission requires only
signals
Described here are the RS232C, RS422 and 423, asynchronous and syn-
EIA-RS232C
The
RS232C covers
the electrical specifications for bit-serial transmission, as well as the physical specifications. It defines the
(modems).
nominal plus and minus 12 volt pulses to
shown
the
first fifteen in
specifies a 25-pin
connec-
REC DATA
(FROM COM)
REQUEST TO SENT
(TO COM)
CLEAR TO SEND
(FROM COM)
(FROM COM)
(TO COM)
RING INDICATOR
(FROM COM)
(FROM COM)
(FROM COM)
(TO COM)
(FROM COM)
TRANSMITTER TIMING
(TO COM)
TRANSMITTER TIMING
(FROM COM)
RECEIVER TIMING
(FROM COM)
6.20
The secondary
serial
channel running at a
second channel
channel
is
is
EIA RS232C
Signals
when
first,
it is, it
The second
for the
BUS STANDARDS
are
239
used to send
serial
The
bit rate
may
1,200
9,600
600
75
4,800
300
50
2,400
150
110
Other rates are also occasionally used. The teletypewriter terminals run
at
110, 150, or 300 bits/second. CRT terminals typically use any of
the speeds
above 1,200.
Quite often,
serial
the
bandwidth. Quite often, voice-grade lines are too noisy for high-rate
comMore expensive data-grade lines must be used.
munications.
The other signals are used to indicate the status of the modulatordemodulator (modem) communications link. Signals such as: "request-tosend",
"clear-to-send",
modem
"data-set-ready",
"data-terminal-ready",
link.
PHONE LINE ANSWERED
(2)
REQUEST TO SI ID
CLEAR TO SEND
A/VIA
6.21
240
are
The
in
is
most buses especially the IEEE-488. The difhandshake is used only at the beginning, and
RS232C
is
popular, as almost
all
convert
used
is
all
in the
similar standard
mechanical teletypewriters.
loop devices to
EIA-RS232C
is
current-
A good thing to do is to
communications become standardized. A loop-to-EIA converter for a teletype is shown in Fig. 6-22. Also useful is what is known as
auto-loop back, shown in Fig. 6-23 This is where the computer, terminal,
or modem, does not have the full standard implemented. The jumpers
this
way,
all
"OK"
all
conditions are
+ o-
15V
KEYBOARD
- o~
TO COMPUTER
-v/vr
2Nl(0l
+ o-
10K
vv
PRINTER
1N91U
FROM COMPUTER
JT"
6.22
L-LKi-tSS
U,
5,
8, 20
TOGETHER
ON EACH PLUG
y\
X
MODEM
OR
TERMINAL
RS232C LINK
N
6.23
BUS STANDARDS
RS422 and
RS232C
423:
transmits signals as single-ended voltages.
The "mark" or
represented by the voltage between two wires. Thus,
the transmit path has two wires, and the receive path has two
wires. The
advantage is that the path may be physically longer between devices, due
"space" condition
is
to
CHARACTERISTIC
MAXIMUM BITS/SEC.
DATA "1' * MARKING
DATA "0' SPACING
SHORT CIRCUIT
RS232
RSU22
100 ft.
2 x 10
-I.5V
+1.5V
RSU23
5000 ft.
10 6
1*
-36V
+36V
VA
VA
100
300
100
5000 ft.
105
VB
VB
100
rate
VA = VB = +
100
fflWER-OFF LEAKAGE,
RECEIVER INPUT,
MINIMUM
6.24
100
100 mV (differential)
infrequent need for such high data rates and line lengths.
Of course, the data sent back and forth may be formatted in many ways.
The topics of asynchronous, and synchronous data transmission and stan-
ASYNCHRONOUS COMMUNICATION
When
tion,
242
data are sent in bursts of equal duration, without clock informathey are being sent asynchronously, without a clock. When data are
{>
TTL
~L
>
-it
12 VOLTS
MC1U88
MC
ll*89
TTL
JT"
COMMON GROUND
RS!+22
^t=%>
I
MCI It
NO COMMON GROUND
(UNBALANCED DIFFENTIAL
TRANSMISSION)
=>
RSi*23
4f(BALANCED LINE)
6.25
Drivers for
sent with synchronizing character codes imbedded within the blocks, they
are being sent synchronously: with a clock.
change".
It
~^~
HARK
SPACE
lihhUlsUHsl
9.09 ms
An eighth bit
MSB
ISB
*H
DATA READY
6.26
BUS STANDARDS
Serial
Data Format
243
may be used
for parity.
EBCDIC is similar except that the 128 codes are encoded differently.
Simple code-conversion ROM's can convert ASCII to EBCDIC, and
EBCDIC to ASCII. Such a
has 8 inputs: seven address-lines for the
data input, and one address-line to specify the conversion (either ASCII to
ROM
EBCDIC
or
character.
The
small
EBCDIC
size
ASCII).
to
of this
It
it is
relatively inexpensive to
is
program
or purchase.
Who
another.
BIT NUMBERS
l
1
1
'
'
b7
1
*>6
b5
b2
>1
1
1
1
1
6.27
NUL
DLE
SOH
DC1
STX
DC2
ETX
DC 3
EOT
SP
DC 4
ENQ
NAK
ACK
SYN
BEL
ETB
BS
CAN
HT
EM
10
LP
SUB
11
VT
ESC
12
PP
PS
^V
1
1
\hex
HEX
244
13
CR
as
IK
SO
RS
15
SI
US
<
>
~
DEL
XKo
a.
ffi
ocm
6.28
BUS STANDARDS
ft
38
SYNCHRONOUS COMMUNICATION
An asynchronous transmission format contains at least two extra bits per
When data are sent as a continuous stream of bits,
incoming data.
To
prevent
its
this,
hundred or so bytes. There exists the necessary logic, at the receiving end,
decoding circuitry, often enought to remain locked in.
Using this method, known as synchronous communication, there will only
to resynchronize the
be eight extra
bits, for
every 800
bits.
This
is
1%
20%
was described
earlier
is
tape-recording standard.
links.
The format
is
similar to
KIM-1
most syn-
chronous formats. In general, the transmission begins with a few synchronizing characters, continues with long data blocks interspersed with
synchronizing characters, and ends with a parity or check-sum character,
plus end-of-record character. Upon receiving a block, if the checkcharacter does not agree with the data, the receiving end will ask the transmitter to retransmit or try again.
[SYNC
CHARS
'PREAMBLE
REC
ID
DATA
DATA
|CHECk|eN0
"""
--
SYNC CHARS
POSTAMBLE
"MAY NOT
BE NECESSARY
NOT BE NECESSARY
IBM
Bi-sync,
SDLC,
communications control
mats.
An
abilities. Basically,
complexity and
differ in
they are
all
synchronous
is
for-
much more complex than in asynchronous communisynchronous communication saves as to the number of bits
transmitted, extra bits are sometimes added to each block so that, not only
errors can be detected, but they can be corrected. This
sion
may
means retransmis-
not be necessary.
246
in Fig. 6-29
shows a
conversion capability.
S100 BUS:
The
one
6~\f->
HF*
6.29
BUS STANDARDS
247
triple three-input
LM324 quad
resolution
both D/A and A/D
D/A conversion 20us
A/D conversion 1ms
0-10 input and output with extra 1000 gain stage for low-level
1
8-bit
for
in
in
volt
to
inputs.
The
circuit will
component.
The Hardware:
The output
output ports
the latch.
is
connected to an 8212
all
latch.
memory
data transfers to
Each
bit is
or
loaded by an input of
% of a low-power-Schottky
input load.
The 74LS138 decoder, along with the 74LS10 and 74LS04 decodes the
output to port "F8" (hexadecimal). The address is partially decoded by Vt,
of the 74LS10 so that bits A7, A6, A5 must all be "l's" to enable the
74LS138 decoder. Then the bits A0, Al, A2, A3, and A4 are decoded by
the 74LS138. The first output represents "F0" on the low eight addressbits.
The
true.
other chip-select
This
is
output of the
is
done by inverting
NAND
is
latch.
PWR false
it
with
and
SOUT
SOUT. The
of the 8212.
is
is
when
the
instruction
is
order to convert
used.
It is
The output
"00" and
it
is
"FF"
now
of the
(hexadecimal).
comparator section.
V\
a voltage between
248
implemented with
Ml
Ml
T,
Tj
Tl
T,
..
n
/
'
T)
~
I
\jimknown/
BYTE
ONE
o,.
T,
r
SYNC
r\
Ml
Tl
BYTE
FLOATING
v..
'u
Tl
p-
'
n"IT
DEVICE
I/O
NUMBER
r~
T|
TWO
/
M,
Tl
ACCUft
ULATOR \
~~\
OBIN
/
WB
\
STATUS
INFORMATION
6.30
The
third
version.
D/A.
If
op-amp
is
The op-amp compares the unknown input with the output of the
the unknown signal is too small, a variable-gain amplifier, im-
is
no damage
is
clamped
to
decoding
below 100
TTL
tri-state driver
signal.
Note
the
be caused to the
will
levels
volts.
by the
resistor-
"F9"
(hexadecimal).
The
done similarly to the output port, except that the second output
of the 74LS138 is used to decode the address "Fl." In addition, the control
lines
is
PDBIN
and
SINP
are
"ANDed"
By
bit,
driving bit 7,
and
we can
voltage. Outputting a
will
new
we
"Fl",
unknown input
"F7" again,
Power
is
supplied by the
+5
op-amp package.
Note that three of the bus
shows how this is done.
+ and -
all
Vcc
pins,
and
the
BUS STANDARDS
drivers
were used as
249
M,
M,
Tj
T,
T.
M]
T2
T,
r\
T,
T,
T,
T,
r\
T,
01
I/O
.
*l-0
"i
i
Ojo
SYNC
\ unknown/
BYTE
ONE
TWO
FLOATING
oeiN
I"
__v~~
v_
INPUT DATA TO
ACCUMULATOR
BYTE
!
READY
OEVICE NUMBER
"~"7
'
r-
r~
'
V.
\
'
v_
....
i
WAIT
..,..
WR
'
STATUS
INFORMATION
6.3
-|-5V
1^18125
OUTPUT
240
INPUT
Use of 74LSI25 As
6.32
An
Inverter
When the input is low, the driver is enabled, and the output will be pulled
logic "1". When the input is high, the driver is disabled and the
up to a
240-ohm
it
"0".
We
parts count.
The Software
For
if
vout
-3
39.0625 x 10
convert
= Numi
to
binary
250
Bin2
39.0625
number
is
milliis:
2.5
OIOOOOOO2
64io
39.0625 x 10 3
MOV A, M
OUT FOH
QUESTION: What
get value
output
from memory
In
to output
is
is linear.
this
converter?
natively,
frequency
value,
we would have:
states
we need
Vi
of the highest
= fmax
conversion
or
1
V2
20 x 10~ 6
In practice, our
program
will
we
= 250 Khz
sounds.
Analog-to-Digital Conversion
To
perform the
A/D
approximation algorithm
is
conversion,
in
we need
to
this into
A
how
program that
this
"JC"
instruction. This
is
done so
flowchart.
BUS STANDARDS
251
CALL CONV:
Set Guess = HI
^IS IT BIGGER
NO
last guess
to small
_
~YES
6.33
is
373.5
We
uS according
mately.
QUESTION: What
252
is
we can sample?
GUESSOUT:
MVI
MVI
MVI
MOV
A,C
OUT
DAC
MOV
RRC
A,B
D, 80H
B, 80H
C,
80H
RC
BIGGER:
B,A
IN
RLC
JC
MOV
RRC
SENSE
MOV
CMP
AND
MOV
RRC
MOV
NOP
JMP
6.34
BUS STANDARDS
guess in C
OUTPUT GUESS
done if carry bi
set
MOV
MOV
MOV
ORA
MOV
CMP
JMP
temp mask in D
mask in B
bigger
A,D
D,A
A,C
B
C,A
E,M
GUESSOUT
A,D
C
A,D
D,A
GUESSOUT
253
ANSWER: Again,
it is:
Vi
= fmax
conversion time
1
!/2
1316
HZ
6
380 x 10~
This
If
we know
simple fashion.
our input
The
is
a slowly-varying waveform,
we can convert
in
y>
S
cowrr
DOW 1
STORE IN
TABLE
6.35
The
routine, as
every 45 uS.
Note how
254
coded
As soon
in Fig.
new guess
in
memory
program
will exit.
MVZ A, 80H
LOOP:
OUT DAC
OUT GUESS
MOV M,A
STORE GUESS
INX
MOV B,A
MOV A,L
CPI
RZ
MOV A,B
IN SENSE
RRC
JC
BIGGER
INR A
CMP E,M
JMP
BIGGER
LOOP
DCR A
NOP
JMP
6.36
BUS STANDARDS
LOOP
Software For Slow Guess Table Converter
255
"IN"
comparator.
This scheme does not really convert to a number, for each sample:
merely
volts
=
numbers
the
change
So,
1
we
x 10
by
this
.86 volts/second,
seconds
be accurate.
are limited
it
that, as long
no more than:
39.0625 x 10
45.0
means
method
we
find that
it is
1000 volts/second:
much below
Hz.
6.37
sine
wave
SUMMARY
We
It
was
D/A and
A/D-converter.
To
CAM AC,
the job of
make
We
have seen
how
the
many
The design
will
and systems.
is
users of the
large
need
If at all possible
may be
256
and
serial
bus
The
serial
modems,
BUS STANDARDS
in
RS232C standard
is
the
for-
Chapter
from cassettes
4.
257
9*
fa**f^
2S8
CHAPTER 7
THE MULTIPLEXER
A CASE STUDY
INTRODUCTION
This system
is
intended to concentrate 32
EIA RS232C
compatible
ter-
Each terminal
Thus, the host comline.
Designed for a
changes
in the
PDP
1/70
the system
is
is
The
cost of
is
terminals.
PROGRAM
*"
BOOT ROM
SERIAL
CENTRAL
DATA BUFFERS
INTERFACE
PROCESSOR
CORE OR RAM
AUTO-RESTART
POWER FAIL
SERIAL LINK TO THE
HOST COMPUTER
'
'
N-CHANNEL
TERMINAL
SERIAL INTERFACE
o]
A
***** Z-_^^J
[,,
7.0
USER
TE RMINALS
'
System Oveivi ew
259
USRT,
8259 interrupt
connection. This does not even include the cost-benefit of fewer telephone
lines
and modems.
THE SPECIFICATIONS
The
ability to
facil-
Given that the 8080A could execute roughly 300 instrucbetween characters at 9600 baud, if it were to service 32
terminals on input, it would have to have less than 300 instructions in the
fast as possible.
Any
time
prototype was
The
left
all
all
coding being
for
it
any
when
baud
for
all
demand from a
when
there
was a
specific
single user.
ARCHITECTURE
The
is
has
its
the 8080
RAM
1,024 bytes of
EAROM
interrupt-controller
Each
terminal, through
sociated with
it,
its
USART,
is
on the bus.
RAM. The
of the available
260
E1ARS232C LINES
i A A n
TO
TERMINALS
llli
CHANNEL
CPU
USART
(8080)
(8151)
(8224)
INTERRUPT
AND
32-
STATUS
8251
37
jt
UPT08
AND
STATUS
USART
CARDS
91L02
(8708)
CARD
8251
RAM
ROM
(82S9)
USART
CARD
4
(8228)
CONTROL
USART
31
Jt
it
IW
-DATA
-ADDRESS
-CONTROL
7.1
at
and terminal-
in the fol-
lowing section.
SOFTWARE
flowchart of the software appears in Figs. 7-2, 7-3, 7-4 and 7-5.
The
software can be divided into four parts: the initialization routine, the polling
routine, the interrupt routine to
interrupt routine to
The
initialization
one
at a time.
debug board
is
installed.
This
is
roughly
all
It sets
mode, speed, and number of bitsper-word on the USART's. This section of the program is 60% of the code
used for the whole application.
the stack-pointer, resets and sets the
261
INITIALIZATION PROGRAM
ANDAUTO RESTART
DETECT AND ALARM
CHANNEL SERVICE
INTERRUPT SUBROUTINE
TERMINAL TO BUFFER
AND BUFFER TO TERMINAL
INTERRUPTS
INTERRUPTS
BUFFER TO CHANNEL
FULL INTERRUPT ROUTINE
7.2
262
THAN X OF THE
2708
USED
7.3
Loop
Fetch character
waiting in host
USART
Status Request
Send status
Update status
Place in last
tuffer pointed
Update last
tuffer pointer
7.4
Mux
Interrupt
263
RETURN
Empty queue by
one character
RETURN
7.5
264
Multiplexer Software
Mux
to Host
Queue Interrupt
The
up by the initialization
see if there has been a character typed by a terminal, or
program, testing to
if
there
is
terminals
(it
takes
list
set
busy"
is
busy
interrupt
comes
in. If
the channel
when
the "channel-not-
is
is
the end of the line, in the queue. In this way, the queue-service routine
primed and
continue to interrupt,
will
is
sent
character
is
transmitted, or,
each terminal
is
if
is
first,
to
is
placed at
empty
all
is
the
is
is
own
its
priority
if
there
is
in the buffer
system
The
still
polls
character,
if
there
is
it
primes
it
by sending a
character.
The
or host-machine, before
ready, an interrupt
is
it
executes.
When
come from
a character
is
the
1/70,
received, and
if it is
data, places
it
in the
appropriate output buffer area. After this, polling resumes. Other characters
commands.
The host-interrupt routine may
interrupt at
soft-restart
polling. It
first saves the status- vector of the machine, then picks up the character that
caused the interrupt. If the most-significant-bit (MSB) is a "1", the charac-
ter is
a tag, or a command. If it
is
a tag,
it is
characters are loaded into the buffer pointed to by the last tag.
status of that
USART.
CASE-STUDY:
"Status-change"
A 32-CHANNEL MULTIPLEXER
265
transfer
or
off,
these
commands
require
is
allowed to poll
all
the terminals.
Thus, interrupts are locked-out and characters may be lost. These commands are usually used to re-initialize the system from the host, after the
host crashes.
The
most-significant-bit being
by the
a
new
The
CPU
is
last
PROM
and
ROM,
same
we
Module
CPU
CPU-board
Int
Req
V
7.6
266
buffer, until
sent.
of the necessary
mable
"0" means
tag
In Fig. 7-6,
all
is
CPU Board
Schematic
These functions
are
the necessary timing from the 18 megahertz crystal to drive the two-phase
It
also
necessary.
The 8228
all
of the modules
in the
system can be
Also on
this
this
device
EPROM
is fully
decoded. The
The
is
will
hexadeci-
selection
EPROM,
EPROM
"03FF"
this
7.7
as well as the
MEMR,
first
go
output
to a l-of-8 decoder,
is
selected.
Then
first
four
an 8205.
If
output
is
this
RAM Board
267
last
two address
then the~CS
is
is
held
also ena-
cells'
RAM
Modules
There are two memory-cards in this system. They are both identical,
is for addresses "1000" hexadecimal through "1FFF"
hexadecimal, and the other is for addresses "2000" hexadecimal through
"2FFF"
except one
RAM
RAM
receivers,
and address-selection
single
4,096 x 8 bits,
that
we need
we need one
logic.
1
bit,
memory
bytes.
^-Ds=
CELL ARRAY
ROW
32
SELECT
ROWS
-Cs=
A9
7.8
268
A8
A7
A6
Detailof91L02C
A5
array.
Note
Since, for any group of 1,024 bytes, eight 91L02's will need to be enabled, the chip-selects for each of the groups of eight are tied together.
there, these four group-selects
go to a
c
c
c
c
c
c
3'
A4
3*
AD
~\gno
A6
A5
RAN
A1
A2
A3
From
l-of-8 decoder.
3'
3'
Pinoutof91L02C
di
DO0
di 1
DB
,,
DB 1
,,
db2
(l
DB 3
3-
DO 1
s
^
DI 2
D02
DI 3
DO 3
CS
DIEN
7.9
269
The data
bits are
fashion,
all
drivers.
An
Two
data outputs from the 91L02's go to the 8216 bidirectional busillustration of the 8216 appears on Fig. 7-9.
of these devices
ill
The
DIEN
signal controls
The~CS enables
listened to.
is
DO outputs. IfCS
is
high,
all
is
to,
and
driven
the outputs to
of the
DB and DO
The
direction of data-flow
low, the
RAM
will
is
determined by the
DI
The
it is
bus-
drivers will be enabled, to drive the 8080 data-bus with this data.
At all
other times, the memory-array listens to the bus. The only time it will write
memory
is
when
the
selected.
we
will
be "1".
To
set the jumper to the opposite of what the high four address-bits
should be. If we want "0010", for A15-A12, the jumpers should be tied to
"1", "1", "0", "1", respectively. In this way, the board will
respond only
when an address lies in the area of 0100XXXX
2 This is pages
XXXXXXX
The
"1FFF"?
USART
Board
all
priority-encoded status-generation
270
USART's,
is
shown. This
PROM.
j a
o 8 5 =
AA
OC
cc
o
<
I
OC
Q
D
<
m
3
=>
OC
I-
oc
a;
HI
Z
a
o
P
c EF
V
KNI
u>r
7.10
USART
Board
271
The 8251 is the basic serial interface element. Grouped four to a card,
they are connected together on their data-buses to form an on-card databus. Similar to the memory card, this on-card bus is buffered by 8216's onto
the system-bus. This
LSTTL
loads.
is
The 8251
since the
is,
they appear as
A15
bit
high,
is
output. This corresponds to locations from "8000" to "8FFF" hexadecimal. Note that since the lower eight address-lines are not decoded, these
are "don't cares" in our memory-mapped I/O map.
The
first
card starts at
"80XX"
(where
USART
"XX"
means
do
from
Note
is
a special
The
is
registers.
function of this
for the
first
card and
"77XX"
terminal.
each
How
USART,
One
is
this
of 16 possible bytes
may be
PROM.
PROM's
The
is
are
made
RxRdy
selected
lines are low, the byte of status is all zeroes, indicating that there is
"nothing" to do for
this board. If
To make
it
sure that
easy to
location contains the value "81":
is
it is
272
waiting.
which
is
status
PROM.
waiting.
What
is
more, the value "81" can be masked, to form the tag for
"87". In
locations contain "83", the next four "85", and the next
this
way, a
priority table
is
formed so
each
that, as
USART
ready with a character, fetch the character, and generate the proper tag
There are two interface chips to take the TTL serial inputs and outputs
USART's and convert them to EIA RS232C +12 and -12 volt
from the
serial pulses.
19,200
XTAL
9600
4800
COUNTERS
2400
1200
600
2's
300
150
T
7.11
The
110
are
The Host
Interface
all
Two
of the
simple dividers
common
serial
Board
273
CONTROL
WIBKB
T X RDY
POWER
UP
7.12
USART,
as these rates
may
differ
The
the
USART,
Number 1 is to signal that a character has been received from the host, and
should be processed, and number 7 indicates that the USART can be reloaded to transmit another character to the host.
The 8259 interrupt-controller is set up by the initialization routine, to call
the service routines at the proper locations, and service the interrupts on a
rotating basis. After an interrupt has been serviced, the software will reset
the corresponding bit-flag in the 8259, and proceed with polling, until a new
interrupt arrives.
Fig. 7-13 illustrates the initialization procedure of the
274
OPERATION
CONTROL
WRITE I/O
F8
WRITE I/O
F7
WRITE I/O
F8
WRITE I/O
F7
WRITE I/O
F7
WRITE I/O
F8
7.13
0000
0000
0001
000U
0005
0008
0009
000A
OOOB
000C
OOOF
0011
0013
ORG OH
NOP
LXI SP.2FFFH
00
31FF2F
F3
C3D700
0031
0032
0038
0038
0039
003A
003B
003C
003F
OOUl
00U3
OOUU
0OU5
DI
F5
CDU900
3E08
D3F8
Fl
OOllt El
0015 Dl
0016 CI
0017 EF
0018 FB
0028
0028
0029
002B
002D
0030
INITIALIZATION STARTS
JMP INIT
PUSH B
PUSH D
PUSH H
PUSH PSW
CALL INT70
MVI A.0008H
OUT 00F8H
POP PSW
POP H
POP D
POP B
RST 5
EI
C5
D5
E5
0019 C9
0020
0020 CDC700
0023 C7
RSTU:
RET
ORG 0020H
CALL SND50
RST
HOST DECODES
FLAG
POP STATUS VECTOR
PRIME QUEUE
ORG 0028H
PUSH PSW
IN OOFAH
ANI 0001H
JZ POPAF
RST 7
F5
DBFA
E601
CA3100
FF
Fl
POP PSW
RET
ORG 0038H
PUSH B
PUSH D
PUSH H
PUSH PSW
CALL OINT
MVI A.0008H
OUT 00F8H
POP PSW
POP H
POP D
C9
C5
D5
E5
F5
CD1802
3E08
D3F8
Fl
El
Dl
7.14
SOFTWARE RESET
275
RST0;
Hardware Initialize
RST1;
RST4;
RST5;
Channel to Host is
not-busy check. Mux
to Host buffer queue
should be emptied.
RST7;
Channel to Host is
not-busy.
Check
buffer queue for
characters, if any
transmit, if not,
return.
7.15
276
Vectors in Software
The
ters
in
both directions.
this
is
full
The
charac-
every character generated, the host must process and return the echo.
ADM3s
output. There are also four 300-baud terminals and four 300-baud dial-up
lines
on the multiplexer.
is
can get
rid
is
95% of
Maximum
rates
it,
measured are
15
characters-per-
and typical
figures
characters
Average out-
maximum
at least indistinguishable
7J6
P.C.
BOARDS
CPU
277
7.17
RAM
c.M)a.H
ill
7.18
278
mm
TERMINALS' USARTS
31
Bflfl
7.19
CONCLUSION
In this chapter, a
cussion of
integrated into
step-by-slep dis-
modules created a subsystem and then the overall system, should enable the
reader to follow through most any other microprocessor interface applicadiscussed in
tion. This particular application utilizes most of the techniques
integrating
management,
I/O
previous chapters: interrupts, memory and
special techniques for software reduction in hardware,
interface
279
2.
CENTRAL PROCESSOR
MAIN MEMORY
J.
DISK STORAGE
1.
4.
TAPE DRIVES
5.
COMMUNICATIONS PROCESSOR
6.
PRINTER
7.
REMOTE MULTIPLEXER
REMOTE MULTIPLEXER
COMMUNICATIONS CHANNELS
on o
k
USER TERMINALS
7.20
280
OVERALL SYSTEM
CHAPTER
TESTING
INTRODUCTION
What do you do when it doesn't work? What went wrong and why? The
debugging process, also known as testing or trouble-shooting, is an integral
part of any system design. Murphy's Law usually holds: if anything can go
wrong,
it
will.
When
Problems such
induced
failure, will
as:
component
failure,
will
be
will also
be
presented.
The
example
illustrates the
"One
debugging phase
in the actual
be presented. The
7.
essential
in a
circuit;
component
failure
a short or
including
software bugs; and noise or interference
open
on the integrated
circuit.
Make
sure
although
you look-up
is
Do
tested" with a simple continuity-checker that emits a tone for a short, and
no noise
for
an open. Such a tester leaves both hands and eyes free to keep
Component
Failure
Components such
as
resistors,
DIGITAL TROUBLE-SHOOTING
capacitors,
inductors,
transformers,
281
short,
no component
ponent
is
or MTBF. This
in
is
all
last in a given
shown
experience
is
as
statistical prediction, in
environment.
Table
known
its
Each com-
mean-time -between-failures
TABLE
8-1
(%/l,000 hr)
Component
Failure Rate
1.
Capacitor
0.02
2.
0.005
3.
Connector contact
Diode
4.
0.013
0.015
5.
Quartz crystal
6.
Resistor
0.002
7.
Soldered joint
0.0002
0.05
8.
Transformer
0.5
9.
Transistor
0.04
10.
Variable resistor
0.01
1 1
Wire-wrapped joint
0.00002
Some
assumes that
all
component
rule
is
to
in
this table
accelerated-life-tests
Failure-rate
is
part.
1/MTBF. Knowing
defined as
is
add the
The
time-between-failures
chips,
one
is
same environment
What
failure-rate?
282
as the
Using Table
components
8-1,
we
that
find:
were
tested.
to be used in the
is
the system
four IC's
.06
crystal
.05
ten resistors
.02
ten capacitors
.50
P.C. board
.60
transformer
.50
diodes
.052
TOTAL
This yields a
MTBF
for the
system
of:
1/1.82%/1,000 hours or
60,000 hours
Suppose we made 1000 of these systems, and used them in the specified
environment? After 1000 hours, it would be most probable that 18 would
have failed. After 10,000 hours, 180 would have failed.
How often do parts fail? This simple question, which we have answered
on an average basis, tells us nothing about the distribution of failures. It
gives the
tics
#/l000 HR.
FAILURE
INFANT
MIDDLE-AGE
OLD AGE
LIFE
8.2
Most
failures
%/1000hr
Failure versus
Age
in
"New"
DIGITAL TROUBLE-SHOOTING
283
"burn-in" test
tries to
weed out
The Table
is
industrial,
all
the
toy;
if
would not
it
We
lem
is
may be
part
toy
may
last five
The
minutes.
how
well a
component
but
is
separate prob-
will last,
it
used as a
application's
be used.
reliability statistics to
ways of measuring
Quality refers to
reliability.
The
Contrary to
lead to different
may
doing
also
its
job.
work longer
easily
part basis.
Software
Software can be
in the
program
a mistake was
at fault.
to handle a
made
in the part
is
a special routine
that,
when
coding,
when power
until the
meet
specifications.
second example
is
after that.
identify.
who
is
at fault,
Noise
Noise
is
electromagnetic
field.
citizens'
Thus,
fields
is
a current
in
a wire, there
284
an
all
an antenna. Not only can noise come from the outside, but
ated inside your system.
is
it
can be gener-
Four examples
1.
When
their
too
are:
many
enough
If
two wires
one induces a
pulse in the other, because of the transformer action between the two.
The induced
pulse
be incorrect.
To
may
reflect,
prevent
and toggle a
this,
flip-flop,
in
Regulator
2>
-*-
+6.0 vo
Ractifiar
8.3
4.
is
power
line.
supply
in Fig. 8-4,
moment, data
117
are lost
filters. If
in
a plain power
happens
at a crucial
fails.
Azr.
2000 V p-p
nioM <pike
VAC
that glitch
line voltage
.0
p-p
noisa spike
10.0
p-p
8.4
DIGITAL TROUBLE-SHOOTING
Filter
285
The
solution here
to use a line
is
filter,
Isolated
Shielded Transformer
of
Common
Components
correct,
fail at
Filter
fault in
all
may
How
a rational fashion?
section will deal with the tools used to find the faults and
Equipment-
Failures
The next
in
8.5
Summary
Grounds
in Fig. 8-5.
each problem
be discussed.
We
will
which can be
own
Tools
will
limitations.
Table 8-6 presents a short summary of problems and tools. The discusexpand on each problem what a tool can $&
it,
it
would
take.
Simple Problems
Short and open conductors, wrong voltages
mon
Any ohm-meter
(DVM)
or volt-ohm-milliampmeter
and currents.
If
286
will suffice, to
(although time-consuming) to
(VOM)
right currents
make
digital
it is
check voltage
an easy matter
can
voltmeter
it
belongs,
PROBLEMS k TOOLS
You have
Equipment
You can solve
problems like:
PROBES
shorts, opens,
wrong voltages
yes
bad resistors,'
caparitors
unknown logic signals
bad- fault tree
already generated
unknown logic signals
bad-fault tree
available
software problem
te
OSC.
D.D.A. I.C.E.
EMU.
no
yes
maybe
no
SGH.ANA.
maybe
,,._
yes
no
no
yes
no
no
no
yes
yes
yes
yes
yes
no
no
yes
time
consuming
no
yes
time
consuming
yes
yes
no
no
no
maybe
yes
yes
yes
yes
no
Eventually
yes
In an average time
yes
yes
yes
yes
yes
yes
TABLE OF ABBREVIATIONS
VOLT-OHM-MILLIAMPMETER
LOGIC PROBES
SIGNATURE ANALYSER
OSCILLOSCOPE
DIGITAL DOMAIN ANALYSER
IN CIRCUIT EMULATOR
SOFTWARE EMULATOR OR SIMULATOR
VOM
PROBES
SGH.ANA.
OSC.
D.D.A.
I.C.E.
EMU.
8.6
DIGITAL TROUBLE-SHOOTING
287
The
VOM
it
The
all
such voltages,
on the power
supplies.
1.5 AMPS MAX.
+5 VOLTS +
8.7
To measure
VOM
Any dynamic
may
it
through the
meter, the current was measured. Be sure to check that these measure-
ments are within the required tolerances. Improper values may indicate
later trouble.
Bad Components
Resistors, capacitors, diodes,
known good
devices.
and
transistors can
all
the
be checked against
DVM
or
VOM
to
determine whether they are basically functional. Other special test equip-
ment
288
is
needed
for diodes
and transistors
When
Once
is
working,
all
devices
in
the entire
the prototype
in
in production,
due to
lems.
at all. Inter-
problems
first,
will require
is
the
is
be completely
first step:
Design Problems
You
make mistakes
we might
but you
didn't.
Yes,
we
all
as well admit
it.
of each follow.
Improper Use:
Passing too
much
its limits.
will
line
cause
is
it
it
burn up.
Every
common. For
the most
may
to
to short.
Improper Specification
If we believe
20
sheet
upon
More
example,
improper specification.
this is
It
when
it
specification.
full
if
in
time
is
of little
an intermittent
fashion in the case of overloading bus lines, and in burning and smoking
parts, in the case of overvoltage/current.
DIGITAL TROUBLE-SHOOTING
289
8.8
290
Logic Probes
The burning
design so
The
it
will
intermittent problems
checked,
parts
you have.
require
that
all
input-output loading be
all
can of freeze spray and a heat lamp can locate temperature sensitive
easily,
by
selectively heating
pected parts.
Logic Probes
The probes
undetermined by using an
termined states: unless
floating,
something
will indicate
whether a
it is
may be wrong.
signal
Watch out
it is
static
a 0,
is
1,
or
for unde-
supposed to be
DYNAMIC PROBLEMS
In operation, the system doesn't work.
The
VOM,
logic
probe
not indicate time. Thus, they are of little use in the dynamic case.
devices which will indicate that the logic level timing is correct.
etc. will
We need
The Oscilloscope
on a
typical oscilloscope of
aTTL
The
is
logic
logic
"0"
any voltage between -0.6 and +0.8 volts. The logic "1" signal
from +2.0 volts to +5.5 volts. Anything in the zone from +0.8 to +2.0 is
signal
is
for
considered undefined. Transitions from one level to the other should occur
in much less than one microsecond to avoid noise problems. The oscillo-
scope
will indicate if a
bad
we have
DIGITAL TROUBLE-SHOOTING
For example,
if
two
TTL
go
in
291
lVOLT/DIVJSION
may be
the gates
seconds
TTL
8.9
10 ns PEE DIVISION
Logic Signal
at a time,
no harm
will
fault will
"0"
level
is
how
cause
the logic
not correct.
t>7^
10 TTL
8.10
LOADS
1.2 VOLTS
RISE DUE TO 20 ma
EXTRA CURRENT- NO LONGER BELOW 0.8
VOLTS
where the
fault lies.
Observing chip-select, control and bus lines with the oscilloscope will
clue you to load problems, timing problems, and noise problems. Make sure
that the logic levels are well defined.
volts.
TTL
trouble.
292
TTL
a hi
******
.
^ ^
'
'
* I *
1600S Analyzer
293
STATE MEASUREMENT
All system timing and system logic levels are correct
any single
bit or line
We could gather
16 oscilloscopes together,
is is
all
when observing
this reason,
we
de-
RAM
128*3
6800
T^T^h
T^.
What does
nodes
in the
octal,
hexadecimal, or
will
system, simultaneously.
in the
It will
It
allows to observe up to 32
when
trigger set.
Each
Available analyzers
fall
into
two
known
bits,
traces.
a given combination of
set
It
or
of
as a state.
Timing-oriented
analyzers
are
merely
multi-channel
oscilloscopes.
problems
are suspected.
program by monitoring
all
294
faults.
ef-
"snapshot" of the
HPf600S
state of the
to
Table 8-11
clacks, four
will
take a
We will
use the
trigger qualifiers,
in
The
lists
probes were attached to the lines indicated. The clock was connected to
Ifi
<t>2.
n/ H
ADDRESS
fEB
CB
L&B
DAM
MSB
LEB
is
The
displayed.
The
triggered
The
by the
6800 Interrupt
finished. Instruction
is
is
an
"F2" hex
at
"1385" hex.
location
2.
HP1600S
8J
status
is
flags, are
is
at locations
index-register,
in
"3FF" hex
accumulators,
and
the stack.
CB2
8.12
Interrupt Sequence
READ /WRITE
VMA
DATA
ADDRESS
0001
0001
0001
looo i
01 tl
um
oo m i r
QUI
ut
OOOO
oooo
oooo
0000
OOII
ooii
ooii
OOII
mi
1 1 1 1
MOO
Mil 1011
nil loio
mi
KKK*P
il!!liIil
v]
rn
ON STACK
|Hk3f:
|i*:*x*i*j
loot
Mil 1000
>"!
|I*MK*U1
FETCH INTERRUPT
LOAD PCH SERVICE ROUTINE
LOAO PCL ] ADDRESS
FIRST LOCATION OF
\
1001
oou
STORES
INTERNAL
REGISTERS
fjP
t5lf\\FFFIKSSS\
0001
[hikjUii
ooii
ooii
ooii
1
mm nil
mi no
mi moi
oooo
oooo
oooo
OOOO
001
Mil 0010
oooo oooo
III oooo oooo
oooo oooo
1
no
DIGITAL TROUBLE-SHOOTING
INTERRUPT
SERVICE ROUTINE
29S
3.
4.
from
this point.
With such a device we have a roadmap of where the system was, where
and where it is going.
is,
it
Some
those with the current states, and stop upon a mismatch. Others display a
bit in
Some
memory, and
a page of
store
more
indicate
if
that bit
However,
all
may
also be identified.
In-Circuit Emulation
In-circuit emulation allows to "get inside" the
going,
it is
routines to allow
you to "catch" a
what
it is
itself. It
fault
may be
It
itself,
makes
microprocessor
By checking
it
these against
located.
Signature Analysis
There are a whole range of special tools usable only once an initial
built and tested. These systems rely on the known behavior of the original system in order to predict what went wrong in the
system has been
system, in the
field.
Some
if
296
Some
trees
297
8.13
298
HP ICE
for
8080 System
Mnemonic AnaJyzer
HP
Signature Analyzer
DIGITAL TROUBLE-SHOOTING
299
Signature Analyzer
This device
values
may be
into a display
relies
on the
fact that
will
whose
bit
value, clocked
A device can
be
streams having the same value or
Thus, each node in a system will have its own signature when it is
working correctly. It will also have a special signature for each possible
problem. By using a fault-tree method, developed by using the analyzer, all
faulty
It will
failures in a system.
The four basic methods used in testing microprocessor-related equipment are: comparison testing, self-diagnostic, stored-response, algorithmic pattern generation.
Comparison Testing
device, or
techniques.
300
C=D
Be Ce
Thai
0- The
blv
Pluq
Is
An a
A1J7
All
Aie Sin
Sv^.tcn ev
o
A3 As sem
The
D.4 connected.
DiS connected f
Is
Inst.u
The Tesl
la.r-
Junipe
The
Turn
nos> ion
"""
.om
HP IB
To The
ON
I
Connect the
SIGNATURE
ANALYZER START
STOP
Inputs to
and
A3TP3 Con
CLOCK
Input lo
AjTPo and Hie GND Input
to the Chassis.. (See Note 1
nect the
lot
A2S1.
While observing
Pin 14 with the
press
Enny
marked
STORE
'.u,i:
Latii.
A1U51
in
keys)
G.-i
Inve.ie.
TURE ANALYZER,
SI
S6.
S?8.
press
Th,.
D-
AlUb3. Sw tch.-s
S10 SI 3. S23
A2W2 o.
C 31.1.'
A1U57
GUARD
A1U57
A1U57
(except the
O-
SIGNA-
TURE ANALYZER,
Keys (those
blue and the
A2W?
LINE and
keys).
T
8.14
DIGITAL TROUBLE-SHOOTING
Fault Tree
301
Self-diagnostic
In the self-diagnostic
mines whether
it is
method, the microprocessor system itself deterand if not, which part of the system is
operational,
The basic principle of self-diagnostic is to execute a "worstcase" sequence, and to observe the results. In the case of the MPU itself, a worse -case sequence of instructions is usually available from
the
defective.
all
may
it
the machine's
include
some
defective? If
what
if the
MPU itself
is
indeed
defective,
it is
of the test. Unless the timer is reset within a specified amount of time,
the alarm will go off, signaling an
failure automatically.
MPU
Such
programs are extensively used on systems enjoying idle time. It is a simple matter to write the basic test program using
most of the machine instructions, and residing in some unused portion
of the ROM. Whenever the microprocessor is idle, such a program may
be run, and thus verify the machine integrity. In addition, if it is run
continuously for a period of time, it will help isolate intermittent
failures of the system. Naturally, it need not reside in ROM, and may
be loaded in RAM from an external device.
Self-diagnostic is also used to test memory or input/output facilities.
The topic of memory -testing will be addressed in detail, in a
paragraph below on algorithmic pattern-generation. In the case of a
ROM
self-diagnostic
memory,
validation.
In
is
called
checksum-
302
simple program
ROM
ROM
which is
(a portion of the
executing in a secure area of the
assumed to be good) can read the contents of the rest of the ROM, recompute the. checksum, and then compare it to the value which has
failure has been
been stored. If a mismatch is detected, a
ROM
identified.
in view
will be issued by the program such as: "close relay A." Provided
that the feedback path be available, relay closure can be verified within n
milliseconds. In this way, the system can exercise all of the external con-
an order
trol devices,
systems
and verify
operation,
on
devices (see book C20 for a complete discussion). Such tests will
the value of input parameters to values in a table, stored in the
all
input
compare
memory,
and determine whether this input data is "reasonable." For example, when
C and over
measuring the temperature of water, temperatures below
100 C will be deemed "unreasonable." Similarly, for a microprocessor
controlling a traffic light at an intersection, detecting vehicle speeds over
200 mph will be deemed unreasonable. Naturally tests can be much finer
than the simplified examples, in a specific environment. Such reasonableness-testing will detect intermittent and permanent failures of input devices
and
will set-off
an external alarm.
Stored-response
In the stored-response method, a large-scale computer system is used
to emulate, or simulate, the device, or the board, under test. First, a program is used to measure the characteristics of the device, or system, under
test,
is
then recorded,
and
will
record essential responses of the system that will be later used as referenwill only
ces. Once these responses are obtained, in phase two, the system
run in comparison mode by executing a specific test program and measuring the response.
DIGITAL TROUBLE-SHOOTING
303
memory.
The
principle
is
essentially
is
RAM
verify that:
it
2: that
Fixed-pattern Testing
In a fixed-pattern test, identical, alternating, cyclical patterns are successively written, then read, at each memory location. This will detect gross
RAM
failures.
However,
Pattern-sensitivity
this will
a typical source of failure in high density chips. Because of the geometrical layout of the chip, some combination of bits
written at
some
is
instant of time in
memory
cells
happen
this
there is not much the user can do about it. The best that can be done
by the user is to run a worst-case program, supplied by the manufacturer,
which has been shown to make similar units fail because of the specific
will
not be considered
here as
it is
which can be diagnosed relatively easily using an algorithmic patterngeneration test. This will be described in the following section.
Galloping-pattern testing
The
on
cell
is
to the next
memory
by the
test.
content, such as
304
all
of the
In a typical galpat,
the following:
rest
location. In this
known
is
is
The
all
way,
memory cell
the memory
ones, or
all
princi-
memory
zeros.
if
writing into
memory
The
be
initialized
with a
1.
all
memory
other
2.
locations.
out until
3.
The contents of
memory
all
The
initial
is
is
carried
data pattern
is
to step one.
Many variations are possible on this basic galput. They have been
nicknamed "marching ones and zeros," "walking ones and zeros," and
"galloping patterns" (galpat one and galpat two).
Ideally,
tion,
all
memory
loca-
and
come back
to the original
its
memory
cell,
the initial
cell.
a very high
a
32
write
It is
number
K memory
will typically
zeros, or
all
all
ones, or write
its
own
It will,
for example,
address in each
memory
location, and then rotate these addresses through the available memory.
hour,
If the test uses galpat techniques, it could easily run for half an
or even for several hours. For this reason, these tests are usually run
only during the initial debugging phase of the system, or when a mal-
function
is
suspected.
microprocessor system
It is
is
is
used.
Let us
first
same outputs
Unfortunately,
as
it
original device.
DIGITAL TROUBLE-SHOOTING
305
Emulation
refers
In fact,
many
even
emulated
They
will
at the
execute
all
the instruc-
faster.
Simulation
is
ROM
and the
ROM
memory.
simulation, or emulation,
itself
performed by
is
ROM
in a final
PROM.
or
those
RAM memory
required by the
RAM-board
Typically the
ROM
resides
of the
final
there.
program
specific
not correspond to the actual address of the ROM chip in the final
system. The second problem is a synchronization problem whenever
will
a slow
RAM
is
used
and a program
initially,
emulation or
ROM
is
when
2. for
the
convenience in debugging.
on a
much more
will
not be detailed.
create for
programs
When programs
are used.
with a simulator.
resulting
It is
are developed
cross-assembler will
will
be performed
An 8080
known
output
registers are
For
is
interface.
is
306
is
program. This
then simulated by
is
In any system where the user must test real input-output in real time,
one of the most significant aids in testing is the emulation of the microprocessor, itself. This
is
called "in-circuit-emulation."
8.15
Software Development
In-Circuit-Emulation
In-circuit-emulation
system, and
is
now
was
available
originally introduced
DIGITAL TROUBLE-SHOOTING
307
facility.
development. The board with the microprocessor itself has been pulled
out of the rack and plugged into an extension board so that its com-
itself
its
socket, and a special cable called the "umbilical cord" has been plugged
into the socket. This is the cable appearing in the illustration. This 40line
cable
is
is
to completely control
from the
right)
It is
is
that
all
and
console. It
is
by
this cable
8080
by the emulator
the system under development (on the
8080 would
actual
require opening
Doing this on an
up the package, removing the lid,
are.
Using an emulator,
it is
8080
below.
clarified
as the contents
It
is
of the memory.
all
the operations
may be performed
memory.
in conjunction
In
with the
memory
is
execution,
the
When
emulated microprocessor
will
back.
of breakpoints
is
reached during
list
memory.
It
ICE,
308
In addi-
it
provides a
44 machine-cycle
trace-back.
INTEL
Whenever a breakpoint
encountered, the in-circuit-emulator stops the execution, and provides the user with a symbolic debugging facility. Typically, when an
is
error
is
is
which caused the problem. This is a tracing problem. With the traceback
capability, it is possible to examine the previous signals, and to determine
which were the instructions executed before the detection of the error.
If this historical record is
earlier
breakpoint can be
set-up and an additional segment of the history of the system will become available. This process can be repeated until the error is finally
identified.
An
or hardware
software
for
capability, as
it
to
execute.
It
is
an essential debugging
first
is essential.
all
some simple
test
programs.
Do
simple things such as: address sequentially every possible memory location,
jump to "0000" hexadecimal continually, input from a port, and output the
PROM's
so that
The
The jump-test
is
so short, that
A2
to bit
it is
all
A 15should
be
all
all
all lines
of the ad-
test.
The
there
is
a fault
is
held
bit
processor.
Now
it
can get
interesting.
larger programs,
Try
At
this point,
Remember:
if
all
a few instructions
work OK,
DIGITAL TROUBLE-SHOOTING
usually they
all
work OK.
309
/^\
s i
8.16
Debug Flowchart
si
KJr\
CD
CD
en
CO
co
LU
C_>
CD
en
Q_
c_>
310
is
most prototyping
They
situations.
(or Octal)
trates the
ROM's
Hex
typical situation.
The
following
is
list
found:
A bad address
bit
into the
it
back
PROM-programmer.
fering.
is
true of
all
logic families.
"TTL-compatible" means
it
connect to TTL
TTL-compatible! This may cause serious problems. As an example:
may cause one bit in the
a PMOS address-line to an
to go bad at random These problems are usually heat and
power-supply sensitive. Your system should work over a wide range
not that
will
it
NMOS RAM
RAM
is
at
one
correction in large
all
specifications closely.
memory
systems.
Know your buses. As a rule, connect no more than one input and one
output to any bus
line.
Overlooking
this
Don't plug
way
is
it
in
RESET
upside
common
noise sensitivity
line.
down
may cause
and
or skewed
left.
If in doubt,
measure your
the socket and call the manufacturer to find where pin one
trouble-shooting flowchart
is
circuit at
is.
IN 16,384
6
6
(if
rented)
DIGITAL TROUBLE-SHOOTING
31
1.
"V
BUZZ-TEST
CONTINUITY Aid
OPEN CHECK
WITH VOM
no
w yes
< n
CHECK POWER
SUPPLIES
WITHOUT PARTS IN
THE SYSTEM - APPLY
POWER. ARE ALL
VOLTAGES CORRECT
ON EACH IC?
u yes
POWER OFF!
(Replace burned
out part)
^yes
INSERT COMPONENTS
WITH POWER OFF.
Check twice-they
are where they
belong! POWER ON
IS ANYTHING TOO
WARM7IS THERE SMOKE?
,no
'
- WIRING ERROR
- TWO OUTPUTS
yes
TIED TOGETHER
- BAD I.C.
- NOISE PROBLEM*
no
* '*
'
il
- SOFTWARE BUG IN
TEST PROGRAM
- WIRING ERROR
- DESIGN ERROR
- NOISE PROBLEM*
no
TRY EXECUTING
SIMPLE SOFTWARE
TEST PROGRAMSDO THEY WORK?
FIX
I
- SOFTWARE BUG
- MISUNDERSTANDING
yes
ho
*"
OF COMPONENT
FUNCTION
- HARDWARE NOISE*
yes
<
8.17
This section
Week
will
Trouble-Shooting Flowchart
1:
Week
2:
Buzz-test finished.
Each module has about 20 errors out of 1000 connecPower applied and one board had a short between power and ground.
Power supply blew up. Wire found by applying large current to board with
tions.
no parts
in
it,
capacitor on a
312
memory
board.
short.
It
Week
3:
Each board being checked for logic signals, etc., separately. Average of
one more error per board found in wiring. Printed-circuit boards being made
for wire- wrap modules.
Week
4:
found
RAM
in
boards upon a
Week
all
memory
test
memory
chip
cell.
5:
Week
6:
Looks
like
Week
7:
P.C. board layout approved, about 5 errors per board found. System has
a baffling problem: will run for a few hours then give garbage to host
system.
Week
8:
P.C. boards back and debugged. Replaced wire-wrap boards with P.C.
boards, one at a time, to check for errors.
Week
9:
Still
Analyzer
Week
is
still
10:
Bad bus
driver on host
or so. P.C. boards finished. System will sometimes pick up improper data
from terminal.
routine
so
thus,
Week
In-circuit
on a trace-back
11:
unhealthy
Week
is
found.
Two
finger-
problems.
12:
bit in the
EPROM
was not cleared upon entering the interrupt routines, where an add with
carry instruction was used, instead of an add with no carry instruction. The
bit
DIGITAL TROUBLE-SHOOTING
313
it
would occasionally get the wrong data upon encountering a carry set after
an interrupt. The problem of the bad bit came by checking the PROM
against the listing four times (it escaped detection that long!). The problem
of the wrong instruction was traced back using the Logic Analyzer when it
triggered on a read from the wrong place.
Epilog:
Except
since the
ers,
end of Week
12.
have been
in
use
with ten times less downtime, than in the main computers to which they
are connected.
SUMMARY
Components, software, and noise are the only "things
to
blame"
if
what
is
Use anything
wrong,
is illustrated in
less,
Fig. 8-18.
will increase.
IMJMutf
i/
WOmCMNCH
"S
g^g^iOT
Y
A\
^H'
z
MSttMLtR-CDITOn SYSTEM
8.18
314
Note the
Prototyping Equipment
cost:
fix things,
or
large
number of
state,
trace,
and
trigger-
in any
be features of the new machines. Also their use
on minicomputers and large computers will become widespread with some
systems including an analyzer in the unit for self-diagnosis.
machine's mnemonics
will
DIGITAL TROUBLE-SHOOTING
31
316
CHAPTER
EVOLUTION
TECHNOLOGICAL EVOLUTION
Beginning with the fundamentals of system interconnection, we have
traveled through the interfacing techniques. Throughout, the direction
of the evolution has been towards the use of completely integrated interfaces. The original racks, full of circuitry, previously required, have now
been reduced to a small number of LSI chips. The future will bring more
intelligent peripheral-chips which will result in increased performance
and
flexibility.
The
is
now
a single
duced:
the
The
on
file
Intel
8048
integrates a
a single chip,
IK by
and provides 27
PROM
lines
and a 32-byte
of input-output.
register
An EPROM
as the processor
ROM,
easily
The 8041
is
peripheral interface."
troller,
and interfaces
It
CONCLUSION EVOLUTION
3 17
The Mostek
Fairchild
3870
integrates a
2K ROM,
RAM,
plus
and
is
PROGRAMMABLE INTERFACES
Because of the low-cost of one-chip processors, device interface chips
becoming "intelligent," i.e. processor-equipped. They receive instrucfrom the MPU, and implement all required control and sequencing.
The decoding and sequencing are usually accomplished by a microproare
tions
is
about 6000
to
chip.
MPU
22000
The complexity of an
transistors.
FDC
or
CRTC
is
is
15000
transistors.
As integration
progresses, the
complete controller
eventually be
will
shrunk in a single-chip.
COST
The
"PLASTIC SOFTWARE"
As soon
as a software algorithm
solidified into
be purchased
LSI
at low-cost. This
as a plastic
becomes well-defined,
is
it is
likely that
many of
can
now
be
LSI chip.
implemented
it
will
the algorithms
book
will
be
software.
Interfacing will then have been essentially reduced to the simple inter-
When
this
time comes,
it is
318
hoped
it.
that the
APPENDIX A
MANUFACTURERS
AMD
MOS TECHNOLOGY
950 Rittenhouse Road
Norristown,
346306
AMI (American
PA 19401
(215)666-7950
TWX: (510)660-4033
Microsystems)
MOSTEK
(408) 246-0330
Telex:
30423
DATA GENERAL
Southboro,
MASS 01772
MOTOROLA SEMICONDUCTOR
(617)485-9100
Telex:
Box 20912
48460
Phoenix,
ELECTRONIC ARRAYS
550 East Middlefield Road
Mountain View, CA 94043
(415)964-4321
FAIRCHILD SEMICONDUCTOR
1
Street
NY
16002
Hicksville,
(516) 733-3107
TWX: (510)221-1666
HARRIS SEMICONDUCTOR
Box 883
Melbourne, FLA 32901
(305) 724-7430
TWX:
(510) 959-6259
INTEL
3065 Bowers Avenue
Santa Clara, CA 95051
(408) 246-7501
Telex:
346372
INTERSIL
10090 North Tantau Avenue
CA 95014
(408) 996-5000
TWX: (916) 338-0228
Cuppertino,
MM
(Monolithic Memories)
ARIZ 85036
(602) 244-6900
Telex: 67325
NS
(National Semiconductor)
CA 95051
(408) 732-5000
TWX: (910)339-9240
RAYTHEON SEMICONDUCTOR
350
Ellis
Street
TWX: (718)480-9333
ROCKWELL INTERNATIONAL
Box 3669
Anaheim, CA 92803
(714) 632-3698
SIGNETICS
811 East Arques Avenue
Sunnyvale,
CA 94086
(408) 739-7700
SYNERTEK
3050 Coronado Drive
Santa Clara, CA 95051
(408) 984-8900
(910) 338-0135
TWX:
319
Tl (Texas Instruments)
Digital
P.O.
Systems Division
Box 1444
TX 77001
(713)494-5115
Houston,
TWX:
(910) 595-1139
ZILOG
1
70 State Street
Los Altos,
CA 94022
(415) 526-2748
TWX: (910) 370-7955
320
APPENDIX B
S-100
MANUFACTURERS
COMPUTER SYSTEMS
Byte Shop Byt-B
Computer Power & Light COMPAL-80 (assembled)
ECT-100-8080
ECT-100-Z80
Equinox 100
Forethought Products KIMSI connector and KIM (6502)
IMSAI 8080 Computer (chassis, power, & CPU)
IMSAI PKG-1
IMSAI PKG-2
MITS Altair8800B
Morrow's Micro Stuff Signa 100
PolyMorphic Systems POLY-88 System
PolyMorphic Systems POLY-88 System 2
PolyMorphic Systems POLY-88 System 6
PolyMorphic Disk System (1 disk)
Processor Technology SOL-PC Single Board
Processor Technology SOL-10 Terminal Computer
Processor Technology SOL-20 Terminal Computer
Processor Technology System
Processor Technology System II
Processor Technology System III
Quay Al Z-80 CPU, SIO, PIO, ROM, Programmer Board
Technical Design Labs XITAN Alpha 1
Technical Design Labs XITAN Alpha 2
Vector Graphics Vector
Vector Graphics Vector without PROM/RAM
Vector Graphics Vector without CPU
Vector Graphics Vector without CPU, PROM/RAM
Western Data Systems DATA HANDLER (used MOS 6502)
Western Data Systems DATA HANDLER (bare bones)
I
349.00
2,300.00
2,495.00
595.00
320.00
420.00
699.00
370.00
699.00
4,444.00
9,013.00
875.00
250.00
525.00
735.00
1,575.00
3,250.00
475.00
795.00
995.00
1,649.00
1,883.00
4,237.00
450.00
769.00
1,369.00
699.00
519.00
499.00
349.00
179.95
79.95
321
249.00
1,495.00
CGRS6502
MRS AM6800
MRS AM6800
R
.H .S.
SD
MPU
295.00
190.00
110.00
78.00
30.00
1 59.95
149.00
269.00
chip)
PC Board
Sales Z-80
CPU
15K Pseudo-Static
CCK
Board (64K)
322
219.95
207.95
1
,150.00
290.00
1
,055.00
349.95
98.00
123.00
143.00
190.00
1 79.00
195.00
495.00
250.00
525.00
298.00
29.00
139.00
285.00
295.00
599.00
895.00
295.00
555.00
169.00
295.00
425.00
895.00
1,195.00
1,495.00
225.00
99.95
MR8 (EPROM/RAM)
Morrow
Mountain Hardware
Omni (16K static)
PROROM
(256)
Omni
Prime
Prime
Prime
Prime
8KSCL M
M8-4
M8-4
M8-4
M8-6
M8-7
(less
memory
(16K
chips)
static)
9IL02A)
(8K 9IL02A)
(board only)
(board only)
(8K 9IL02APC
(16K
static)
static)
nS)
nS)
163.84
139.00
159.00
2,599.00
749.00
449.00
107.00
124.95
145.00
95.00
205.00
345.00
485.00
625.00
39.95
49.95
79.95
99.95
129.95
479.95
167.00
765.00
155.00
96.00
164.00
459.00
468.00
1,490.00
,580.00
1,670.00
1,750.00
154.00
295.00
1
529.00
300.00
485.00
339.00
89.95
269.00
295.00
124.00
579.00
129.95
209.00
30.00
35.00
265.00
525.00
169.00
295.00
323
RAM
435.00
574.00
295.00
299.00
265.00
89.00
189.00
PLUG
IN
Computer
145.00
164.00
450.00
165.00
209.00
SOFTWARE BOARD
Kits Power-Start
with
PROM
Programmer
165.00
220.00
189.95
224.45
180.00
245.00
164.00
140.00
425.00
520.00
520.00
295.00
129.00
159.00
Cromemco TU-ART
IMSAISI0 2-1 (one
S compatible)
(2 parts)
part,
without cables)
M ITS 88-2SIO
M ITS 88-2SIO
MITS88SIOB
(one part)
+ SP (two parts)
324
ROM
125.00
195.00
125.00
1 56.00
195.00
108.00
44.95
150.00
188.00
124.00
140.00
149.00
47.50
25.00
295.00
125.00
(7analog inputs
&
7 outputs)
ADC/DAC
MITS 88-ADC
MITS 88-Mux
MITS AD/DA
(assembled only)
(assembled only)
(assembled)
(1
(2
analog output)
analog outputs)
145.00
250.00
524.00
319.00
235.00
145.00
195.00
MODEM BOARD
International Data Systems 88-MODE
Hayes 80-103A (assembled)
Hayes 80-103A (board only)
199.00
279.95
49.95
DAJEN
DAJEN
Cassette Interface
MITS88-ACR
National Multiplex Corp No. 2 SIO with ROM
Morrow Intelligent Cassette Interface
Morrow Intelligent Cassette Interface (3 drives)
135.00
120.00
135.00
195.00
298.00
145.00
140.00
96.00
102.00
89.95
87.00
245.00
245.00
120.00
MECA ALPHA-I
System
400.00
600.00
875.00
69.95
169.95
325
189.95
369.90
339.90
IMSAI
IMSAI
IMSAI
F IF
DC2-1 & F IF
DC2-2 & F IF
INFO 2000 Adapter (without RAM)
INFO 2000 Adapter (with 4K RAM)
INFO 2000 Adapter Per Sci 1070 Controller
Micromation Universal Disc Controller
Micromation MACRO DISC System, Model 164K
Micromation MACRO DISC System, Model 256K
Micropolis 1053 Mod II (630K)
Micropolis 1043 Mod II (315K)
Micropolis 1053 Mod
(286K)
Micropolis 1043 Mod
(143K)
F
F
MITS 88-DCDD
MITS88-DISK
(Controller
&
disk)
695.00
695.00
300.00
300.00
850.00
265.00
1,595.00
2,170.00
1,095.00
599.00
1,694.00
2,789.00
120.00
160.00
860.00
229.00
900.00
1,100.00
1,795.00
1,095.00
1,545.00
945.00
1,425.00
1,215.00
699.00
695.00
750.00
245.00
1,095.00
395.00
1,895.00
1,095.00
2,690.00
40.00
190.00
326
12,500.00
14,700.00
24,500.00
3,900.00
PROM BOARD
CreaComp M 100/16 (16K, 2116)
Crea
Crea
Crea
Comp M 100/16
Comp M 100/32
Comp M 100/32
(with parity)
(32K, 21 16)
(with parity)
PROM CARD
selectable)
2K ROM/2K
PROMS)
RAM
Microdesign
MB-3
MB-3
MB-3
MB-8
2K
4K
PRAMMER
for
PROMs)
Go PROM/RAM
1702
19.00
105.00
145.00
65.00
85.00
89.00
189.00
1
702As)
(16 1702As)
(8
(without
(2708)
Xybek
485.00
560.00
885.00
990.00
145.00
145.00
65.00
56.95
120.00
135.00
179.95
269.00
85.00
399.00
165.00
99.50
95.00
49.95
49.95
34.95
85 00
65.00
(with a
1702 &
RAM)
299.00
499.00
225.00
275.00
359.00
195.00
149.00
99-9 5
327
325.00
395.00
525.00
245.00
550.00
210.00
275.00
INTERRUPT BOARD
Cromemco TU-ART
Paso Computer Group (board only)
IMSAI PIC-8 (with internal clock)
El
MITS 88-VI/RTC
195.00
20.00
125.00
136.00
REAL-TIME CLOCK
Comptek CL2400
COMPU/TIME CT 100
COMPU/TIME T 102
International Data Systems SMP-88
Lincoln Semiconductor Clock and Display Driver
98.00
195.00
165.00
96.00
95.00
AC POWER CONTROL
Comptek PC3216 Control Logic Interface
Comptek PC3216 & PC3202 Power Control Unit
Comptek PC3216 & 16 PC3202 16 Channel System
Comptek PC3232 Control Logic Interface
E.E.& P.S. II5V I/O
Mullen Relay/Opto Isolator Control Board
189.00
228.50
821.00
299.00
249.00
117.00
E.E.&
328
P.S.
BBUC
55.00
55.00
ALF
ALF
ALF
ALF
(1
channel)
(2 channels)
(3
channels)
(4 channels)
SRS Polyphonic
SRS Polyphonic
1 1 1
.00
127.00
143.00
159.00
250.00
299.00
525.00
175.00
175.00
PRT-KC
Printer Kit
495.00
88-UFC
149.00
BOARD
TYPEAWAY
225.00
Cromemco D+7AIO
Cromemco TU-ART
IMSAI
IMSAI
IMSAI
IMSAI
IMSAI
IMSAI
IMSAI
125.00
145.00
195.00
93.00
115.00
137.00
156.00
139.00
169.00
195.00
69.95
49.95
57.45
105.00
148.00
191.00
234.00
102.00
185.00
210.00
329
149.00
42.00
25.00
47.50
25.00
295.00
125.00
PROTOTYPE BOARD
Advanced Microcomputer Products Universal Proto
Artec GP-1 00
Cromemco WWB-2K
Electronic Control Technology PB-I
E.E. & P.S. Wire Wrap
E&L
IMSAI GP-88
IMSAI 88C-5 & P106-6 Intelligent Breadboard System
IMSAI 88C-3 & P106-3 Intelligent Breadboard System
MiniMicroMart C-80-WW (wire wrap type)
MiniMicroMart
MiniMicroMart
MiniMicroMart
MiniMicroMart
MiniMicroMart
C-80-DIP
C-80-BUS-WW
(wire wrap)
MITS88-PPCB
MITS88-WWB
PolyMorphics Poly I/O
Processor Technology WWB
Sargent's Dist. Co.
Seals Electronics
WWC
Tarbell Electronics
Vector 8800V
Vector 8800-A
Vector 8800-B
39.95
20.00
35.00
22.00
39.00
241.50
28.00
30.00
138.00
38.00
39.80
699.00
464.00
19.95
18.95
21.95
27.45
20.95
26.45
45.00
20.00
55.00
40.00
25.00
37.50
28.00
19.95
29.95
89.00
EXTENDED BOARD
Advanced Microcomputer Products Extender
Artec EXT-100
Cromemco EXC-2
E.E. & P.S. Extender W/C
Galaxy Systems EX-I
IMSAI
EXT
MiniMicroMart C-80-EXC
330
34 g 5
1200
35 00
34 00
25.00
39.00
24.95
"
EXB
"
QQ MM
EXT
8 -
(w/w connector)
Suntronics EXT-I
Vector 3690-12 (assembled)
25.00
ADAPTER BOARD
MiniMicroMartC80-8A (for MOD 8/C-MOD 80 boards)
Forethought Products KIMSI (for KIM)
19-95
125.00
slot
MS
w/connectors
Versatile
CRT
(assembled)
Godbout Motherboard
79.95
229 00
699.95
(18 slot)
MiniMicroMart Expander
MiniMicroMart Expander
Morrow MotherBoard
(4 slots)
(9 slots)
T&H
100.00
60.00
85. .00
118.00
200.00
275.00
10.95
17.95
76.00
19.95
235.00
316.00
149.00
49.00
TERMINATION BOARD
25.00
Godbout
II
III
(monitor)
(oscilloscope)
395.00
185.00
245.00
495.00
107.00
137.00
331
249.00
149.95
269.00
303.95
308.00
210.00
199.00
179.95
(graphics)
215.00
88-ACC-K
Environmental Interface
Environmental Interface with camera
I
(408)249-4221
Associated Electronics
NM
88003
ALF
Products, Inc.
128 S. Taft
Byte Shop
1450 Koll Circle, No. 105
San Jose, CA 95112
Lakewood,CO 80228
CGRS
Alpha Micro Systems
17875 N. SkyPark North
Irvine,
C A 92714
(714) 957-1404
Altair (see
332
Microtech, Inc.
Unknown
MITS)
CHP, Inc.
P.O.Box 18113
San Jose, CA 95158
195.00
390.00
295.00
595.00
Comptek
P.O. Box 516
La Canada, C A 91011
P.O.
Box 3313
C A 92519
Riverside,
(213) 790-7957
Cromemco
Computalker Consultants
P.O.Box 1951
Santa Monica, CA 90406
Computer
Cybercom
2 102 A Walsh Avenue
Kits Inc.
DAJEN
C A 94710
David C. Jenkins
7214 Springleaf Court
(415)845-5300
Citrus Heights,
Inc.
Data Sync
201 W. Mill
Santa Maria, C A 93454
(805) 963-8678
DigiComm
6205 Rose Court
Roseville,CA 95678
COMPU/TIME
P.O.
Box 417
Huntington Beach,
(714) 638-2094
CA
92648
& Light
C A 91604
(213) 760-0405
Crea
Suite
Comp
System, Inc.
305
Systems
154 Dunsmuir Place
Digital
1
Computer Power
C A 95610
(916)723-1050
Livermore,
CA
(415)4134078
Digiteck
P.O.
Box 6838
Duston, Forrest
Palatine,
333
Dutronics
P.O.
Stockton,
Box 9160
CA 94608
61 First Street
E.E.&P.S.
Electronic Eng.
Route No. 2
(615)984-9640
Electronic Control Technology
P.O. Box 6
Computer Group
P.O.
Box 6314
CA
94706
(800)648-5311
Albany,
Westlake Village,
CA
91361
(805) 497-7755
Galaxy Systems
Box 2475
Woodland Hills,
(213)888-7233
P.O.
CA 91364
Louisville, Tennessee
El Paso
Godbout Electronics
Box 2355
Oakland Airport,
Hayes
P.O.
Box 9884
GA 30319
Atlanta,
(404)231-0574
Heuristic, Inc.
Los Altos,
(408)734-1525
CA
94022
Atlanta,
iCOM
Extensys Corp.
592 Weddell Drive, S-3
Sunnyvale, CA 94086
CA 94614
GA
30306
Division
IBEX
Forethought Products
P.O.
Box 386-A
334
739-3770
CA 94086
MECA
INFO 2000
Micro Data
Box 316
Culver City, C A 90230
3199
Microdesign
8187 Havasu
P.O.
Trinity Place
San Jose,
CA 95124
Circle
BuenaPark,CA 90621
(415)465-1861
CA 94606
(415)465-1861
Oakland,
(703) 536-7373
Box 507
Avenue
Ohio 43554
(419) 737-2352
MicroGRAPHICS
P.O. Box 2189, Station
Champaign, IL 61820
Industrial
Pioneer,
MicroLogic
P.O.
Box 55484
Indianapolis,
IN 46220
Micromation
524 Union Street
San Francisco, CA 94133
(415)398-0289
Lincoln Semiconductor
P.O.
Box 68
Milpitas,
CA 95035
Micronics, Inc.
P.O.
Box 3514
NC 27834
(408) 734-8020
Greenville,
Logistics
Micropolis Corp.
9017 Reseda Blvd.
Box 9970
Marina Del Rey, C A 90291
CA 94710
Northridge,
CA 91324
335
MIKRA-D, Inc.
Box 403
Peripheral Vision
P.O.
P.O.
Hollister, Mass.
01746
Box 6267
Phonics, Inc.
P.O.
MiniTerm Associates
Box 268
Bedford, Mass. 01730
Polymorphic Systems
737 S. Kellogg
MITS
(Altair)
2450 Alamo
S. E.
Albuquerque,
NM
87106
Morrow's Micro-Stuff
Box 6194
Albany,
CA 94706
Galeta,
CA 94086
CA 94608
West Covina,
MRS
P.O.
Box 62275
Sunnyvale,
CA 91792
Processor Technology
Box 1220
Hawthorne,
6200-L
CA 90250
Box 6214
Hollis Street
Emeryville,
CA 94608
Quay Corporation
Box 386
Freehold, N J 07728
P.O.
Hayward,CA 94545
Mountain Hardware
Box 1133
BenLamand,CA 95005
3530
R.H.S. Marketing
Palo Alto,
Station
336
Warrensville Center
Cleveland, Ohio
44122
RO-CHE Systems
7101 Mammoth Avenue
VanNuys,CA 91405
S.
D. Sales
P.O.
Box 28810
Dallas,
Texas 75228
Road
4209 Knoxville
Lakewood,CA 90713
Scientific
Tarbell Electronics
Research Instruments
C
Marcy,NJ 13403
P.O. Drawer
Seals Electronics
Box 11651
Knoxville,
TN
37919
CA 93454
Signal Boardcasting
Smoke
Box 2017
P.O.
Hollywood,
CA 90028
Sylmar,CA 91342
Solid State Music
MIKOS
419 Portofino Drive
San Carlos, CA 94070
Stillman Research Systems (SRS)
P.O.
Box 14036
Phoenix,
AZ
Suntronics
85063
Company
360 Merrimack
Lawrence,
MA
Street
01843
Company
Box 2627
Pomona, C A 91766
Synetic Designs
P.O.
CA
91361
WIZARD
CA 95050
Engineering
Xybek
Box 4925
P.O.
Stanford,
CA
94305
Szerlip Enterprises
TEI
Inc.
7231 FondrenRoad
Houston, Texas 77036
T&H
Engineering
Box 352
Cardiff, CA 92007
P.O.
337
INDEX
A
ACIA
58,107,112
acknowledge
address-bus
analog to digital
analyser
Ascn
asynchronous
8,10,20
191, 197, 204, 207
287, 293
97,147,215,244
13 242
B
band-rate
240, 273
bidirectional
25
bounce
85
breakpoints
buffering
bus-drivers
308
24, 25, 269
48
CAMAC
cassette
dock
338
215,233
85, 121, 123, 140
1
26, 34, 43
component
z,
failure
9,10
control-bus
102
counter
CRC
171
CRT
85,142,151
D
69
daisy -chain
8, 10, 19
data-bus
22
decoders
digital to
analog
191,193,196,206,246
202
direct-comparison
direct
memory
75
access
J
distributor
DMAC
75 185 187
dot-matrix
'
100
drivers
dual-slope
^01
^87, 288
DVM
dynamic
>
RAM
"
23, 3
EBCDIC
245
EPROM
29
error detection
6Q
Lyjy
1
339
floppy-disk
fully
decoded selection
85,154,173,177,180,184,185
21
G
glitch
205
IEEE 488
-
in-circuit
emulation
integration
228
296, 306
201
interface chips
10
interrupts
66
I/O
mapped I/O
46
H
hard-format
hardware
hexadecimal
159,168
8
44
K
keyboard
85,95,96
L
latches
LED
linear selection
340
48
85,98,103
20,32
line printer
LSI
^
7
M
magnetic stripe reader
memory-array
85, 120
268
memory map
20
memory-mapped I/O
45
microcomputer-on-a-chip
microprocessor
MTBF
multiplexer
9,317
282
9,82,83,210,259
N
noise
offset
one-shot
oscilloscope
284, 285
212
82, 83
287,291
P
packaging
pattern testing
85, 113
32
304
341
PIA
50
PIC
PIO
50
plastic software
polling
PPI
priority
probe
318
62, 64, 68
54
64, 70
287, 290
programmable
50
programmed I/O
62
Q
quad-slope
201
queue
260
RAM
23
refresh
40
refresh address
40
refresh controller
40
rollover
88
ROM
RS232C
342
24, 84
215,239,259
S100
215,217
sampling
196, 197
sampling theorem
197
scaling
212
scanning
302
self-diagnostic
serial
93
%"''
56
I/O
signature analysis
3 00
simulation
305
84
soft-fail
1
soft-format
software
8,
59
284
software-priority
69
stack
^3
293, 295
state
static
RAM
stored-response
substrate material
successive approximation
synchronous
system controller
23
303
17, 18, 19
1
97
13,243,246
28
343
teletype
testing
transceivers
85 105
281 300
25, 269
UART
USART
56,58,61,106
58, 60, 260,
270
V
vectored-interrupt
VOM
69
287, 288
Y
yield
344
17, 18
MICROPROCESSOR BOOKS
BOOKS
C200
C201
MICROPROCESSORS, from
chips to systems,
by Rodnay Zaks
C4
par
C207
Rodnay Zaks et
Pierre
systeme,
Le Beux
MD
CASSETTES
51
52
book)
INTRODUCTION TO MICROPROCESSORS
PROGRAMMING MICROPROCESSORS
SEMINAR BOOKS
Bl
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Permit No. 2587
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will
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SYBEX
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SYBEX
SYBEX
INTERFACING
no longer an art, but a set of
techniques and components.
This book will teach you
how to interconnect a
complete system, and
interface it to all the
is
usual peripherals. It
covers hardware and
"*i
js
C6
3>
ft
IEEE 488
Ww
ft
^
-"^
^r
&
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ft
INTERFACING
S
-..
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to
o pn
CD