Low Power Multi GHZ Circuit Techniques in Vlsi: IPASJ International Journal of Electronics & Communication (IIJEC)

IPASJ International Journal of Electronics & Communication (IIJEC)
Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm

Email: editoriijec@ipasj.org
ISSN 2321-5984
A Publisher for Research Motivation........
Volume 3, Issue 3, March 2015
LOW POWER MULTI GHz CIRCUIT

TECHNIQUES IN VLSI
1.
A.Rajesh , 2.Dr.K.Chenna Kesava Reddy , 3.Dr.B.L.Raju

1.
Research Scholar,JNTU,Hyd
2.
Ex-Principal,JNTU College Of Engineering,Jagityal

3.
Principal,ACE Engineering College,Hyd
ABSTRACT
High Performance Integrated Circuits(on Chip) involves large number of transistors integrated in the semiconductor material
operating at GHz frequencies.CMOS Technology Scaling has to overcome three parameters such as power dissipation, process
parameter variations, Circuit Complexity as well as Clock Load. In this paper, Circuit Techniques to control power dissipation
and regain the logic levels. Integrated Circuit consists of a large number of active and passive components. The basic element
considered is a inverter .On chip Signal degradation is analyzed using a nmos switch, resistor, capacitor. In realization, first
discuss the architecture and the implementation issues. Then, the coding process is simulated by Pspice program and verified
by Cadence Tools.
Tools used:- Pspice, Cadence Tools
1.INTRODUCTION
CMOS stands for complementary MOSFET. It consists of both a nmos and pmos device to implement any logic. A
MOSFET is a Voltage Controlled Device with four terminals such as drain,source,gate and bulk. The source terminal
serves as the source of the carriers of electrons or holes. The drain terminal collects the carriers flown from the source
terminal.The carriers flow from the source to the drain terminal through a conducting path called channel. The flow of
carriers in the channel is controlled by applying voltage at a third terminal called gate of the MOSFET.
Fig.1 symbol for nmos and pmos
Fig.2 Cross Sectional View of NMOS,PMOS
2. POWER DISSIPATION IN CMOS CIRCUITS

Power Dissipation of a CMOS Inverter can be divided into two types:I. Dynamic power
II. Static power
The Sources of dynamic power are switching power, short circuit power and Static power dissipation is from leakage
currents.
1.DYNAMIC POWER
1.The switching Power is analyzed as
Pswitch= f c v2
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Where
C is Load Capacitance that is to be charged.
f is the clock frequency with which gate switches
Vdd is the power supply
is the switching activity ratio, how frequently the output switches per clock cycle.
2.The Short Circuit Power is due to the direct path from power supply to ground. when both devices are on.
is the gain factor
T is the input rise and fall time
Vth is the threshold voltage of a MOSFET
Psc= (Vdd-2 Vth)3 T f/12

Generally, it can be kept below 10 % switching power by proper sized static cmos.
2.STATIC POWER :- is due to the Leakage Power
There are several leakage mechanisms that are
a. Subthreshold leakage
b. Gate leakage
c. Reversed junction leakage
Proper operating voltages above threshold voltage, technology (180nm) ,we can neglect the effect of leakage power and
short circuit power on total power dissipation
PROCESS VARIATIONS
Process variations such environment, physical variations impact circuit parameters such as difference in channel
length, width, gate oxide thickness, channel length doping concentrations.
Among all transistor parameters, threshold voltage is an important parameter both for driving strength of transistors.
In this paper, power dissipation and process variation due to threshold voltage is analysed by designing circuit where
mosfet are of different threshold voltages, channel length, width, and doping concentrations.
3.CMOS INVERTER
A CMOS Inverter is the Simplest logic Circuit that uses nmos and pmos transistor.
Fig.3 CMOS realization of Inverter
Fig.4 Equivalent Circuit of CMOS Inverter
Fig.5 Load Capacitance Circuit of CMOS Inverter
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Simulation Results
The Design Specifications are
Channel length= 180nm,Width= 2um,Finger Width=2um,Threshold =800 nm
S/D metal Width=400nm,Source/Drain diffusion area=1.2p
Source/Drain Diffusion periphery=5.2um,Tr=Tf=0ns
Fig.6 CMOS realization of Inverter using Cadence Tools
Fig.7 CMOS realization of Inverter Test using Cadence Tools
Fig.8 Simulation Results of CMOS Inverter using Cadence
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With Tr=Tf=5ns
Fig.9 Simulation Results of CMOS Inverter using Cadence

With threshold =1600nm and width=2.5 L,Source/Drain diffusion area=440f,Source/Drain Diffusion periphery=2.8um
Fig.10 Simulation Results of CMOS Inverter

Design of the basic Inverter modeled using an nmos switch
Fig.11 CMOS realization of Inverter_nmos switch
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Fig.12 Simulation Results of CMOS Inverter

The Signal degradation of voltage is regained using an cascaded inverter at the load.
The Design Specifications are:
1 stage
Channel length= 180nm, Width= 720nm
Finger Width=720nm, Threshold =800 nm,S/D metal Width=400nm
Source/Drain diffusion area=1.2p,Source/Drain Diffusion periphery=5.2um
nmos switch:Channel length= 180nm, Width= 2um,Finger Width=2um, Threshold =400 nm
2 stage:
Channel length= 180nm, Width= 400nm,Finger Width=400nm, Threshold =400 nm
The reasons for choosing different width for the devices are to handle multi threshold values.
Fig.13 CMOS realization of Inverter_nmos switch through Inverter
Fig.14 Simulation Results of CMOS Inverter_nmos switch through Inverter
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Design of the basic Inverter modeled using an capacitive Load
Fig.15 CMOS realization of Inverter_capacitiveload
Fig.16 Simulation Results of CMOS Inverter_Capacitive load
Fig.17 CMOS realization of Inverter_capacitiveload _inverter
Fig.18 Simulation Results of CMOS Inverter_Capacitive load_inverter
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4.RESULTS & CONCLUSION

In this paper, I investigated the performances and com-plexities of the CMOS INVERTER and power dissipation and process
variation due to threshold voltage is analyzed by designing circuit where MOSFET are of different threshold voltages,
channel length, width, and doping concentrations.
The Power dissipation of the CMOS inverter varies from 0.2 mw to 6mw as the load capacitance varies from 1pf to
30pf . this is the case when fanout increases.The small value of capacitance can degrade the signal strength to the order
of 75% and to regain the logic level (Voltage) the load end is connected with another inverter.
On chip Circuit in VLSI experience the same when a signal is distributed to multiple gates. The parasitic effects
(resistance, capacitance) can degrade the signal strength.
The solution is to use cascaded inverter which helps in regain the signal strength and the proper logic values. The
disadvantage with this is cascaded stage introduces a delay of the order of nanosec.
REFERENCES
[1] www.eeherald.com/section/design-guide/Low-Power-VLSI-Design.html
[2] www.ijaet.org/.../18STRATEGIES-METHODOLOGIES-FOR-LOW-PO...
[3] www.ee.ncu.edu.tw/~jfli/vlsi21/lecture/ch04.pdf
[4] users.ece.utexas.edu/~adnan/vlsi-05-backup/lec18LowPower.ppt
[5] www.cpdee.ufmg.br/~frank/lectures/Sill-LowPower2.ppt
[6] www.slideshare.net/vintrainvlsitraining/low-power-vlsi-design
[7] www.cs.utah.edu/.../VLSI/.../Low_Power/Low%20Power%20VLSI.pdf
[8] www.academia.edu/.../POWER_REDUCTION_IN_MODERN_VLSI_CI...
[9] leda.elfak.ni.ac.rs/.../projektovanjeVLSI/.../10%20Low%20Power%20De.
[10] ijcta.com/documents/volumes/vol2issue1/ijcta2011020101.pdf
[11] textofvideo.nptel.iitm.ac.in/106105034/lec1.pdf
[12] www.cmosvlsi.com/lect18.pdf
[13] www.eng.auburn.edu/~agrawvd/TALKS/siri_ms.pdf
[14] www.ijoart.org/.../Designing-of-Low-Power-VLSI-Circuits-using-Non-Cl..
[15] www.ijetae.com/files/Volume2Issue11/IJETAE_1112_15.pdf
[16] ijcaonline.org/journal/number22/pxc387666.pdf
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IPASJ International Journal of Electronics & Communication (IIJEC)

Web Site: http://www.ipasj.org/IIJEC/IIJEC.htm

A Publisher for Research Motivation........

Volume 3, Issue 3, March 2015