432

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 6, NO. 3, SEPTEMBER 1998

On Methods to Match a Test Pattern Generator

to a Circuit-Under-Test
Irith Pomeranz, Senior Member, IEEE, and Sudhakar M. Reddy, Fellow, IEEE

Abstract Autonomous circuits such as linear feedback shift

registers (LFSRs) and cellular automata are used as low-cost
test pattern generators for circuits testable by pseudo-random
patterns. We demonstrate that different LFSRs of the same
degree, started from different initial states, may yield significantly
different fault coverages and test lengths when used as test
pattern generators for a given circuit, especially when the circuit
has faults which are hard to detect by a practical number of
pseudo-random patterns. Methods to tailor an LFSR to a circuitunder-test are proposed, that attempt to select the most effective
LFSR and initial state for the circuit. The first method is based on
a learning process that can be applied directly to certain types of
circuits. The learning process is also used to establish a collection
of (primitive and nonprimitive) LFSRs and initial states, effective
for arbitrary circuits. This collection can then be used as a starting point for a genetic optimization procedure aimed at improving
the selected LFSR and initial state. The use of an LFSR that
can apply complemented as well as uncomplemented test patterns
is shown to significantly improve the fault coverage, at the cost
of a small area overhead. Experimental results demonstrate the
applicability of the proposed approaches to stuck-at faults and
to transition faults.
Index TermsBuilt-in self-test (BIST), built-in test pattern generator, linear feedback shift register, pseudo-random patterns,
weighted random patterns.

I. INTRODUCTION

SEUDORANDOM test pattern generation using autonomous circuits such as linear feedback shift registers
(LFSRs) [1] was proposed as a test application method
[1][4] since it eliminates the need to store deterministic test
patterns and requires low hardware overhead. The suitability
of an LFSR as a test pattern generator for a given circuit
depends on the number of test patterns required to achieve the
desired fault coverage. In many cases, a primitive LFSR that
generates pseudorandom patterns is considered insufficient
as a test pattern generator (a primitive LFSR is one that
can be described by a primitive polynomial [cf. 1, p. 70]).
Current approaches may try an arbitrary primitive LFSR
started from an arbitrary initial state. If the LFSR tried
does not reach the targeted fault coverage with a practical
number of test patterns, the existing approaches try to improve
the fault coverage by using design-for-testability techniques
(e.g., by adding test points to the circuit [1]) or by using
Manuscript received July 29, 1997; revised December 1, 1997. This work
was supported in part by the NSF under Grants MIP-9220549 and MIP9357581. This paper was presented in part at the IEEE 1993 International
Test Conference.
The authors are with the Electrical and Computer Engineering Department,
University of Iowa, Iowa City, IA 52242 USA.
Publisher Item Identifier S 1063-8210(98)05983-6.

other test pattern generators. Several test pattern generators

were proposed in this context, including the use of weighted
random patterns [5][14], the design of a special-purpose
test generator for the circuit-under-test [15][18], and the use
of multiple initial states (seeds) [19], [20] and/or multiple
LFSRs [20]. In [21], a cellular automaton [22] is selected
out of a small predetermined subset of cellular automata such
that a minimal number of initial states have to be loaded
to completely test the circuit. All these techniques increase
the fault coverage and reduce the test length, at the cost
of a significant increase in area compared to the use of a
single LFSR (or cellular automaton) started from a single
initial state. Hardware overhead is associated with the use of
weights, multiple LFSRs, multiple seeds, and in [14], also
with the need to reorder and reroute the inputs of the circuit.
In this work, we explore methods to achieve the desired
(e.g., complete) fault coverage by matching any single LFSR
started from a single initial state to the circuit-under-test,
at zero or small hardware overhead compared to a single
primitive LFSR started from a single initial state. As will
be demonstrated, such matching improves the fault coverage
and/or reduces the test length considerably. The need to
match an LFSR to the circuit-under-test is supported by the
observation that large differences in fault coverage and test
length may exist when different LFSRs and different initial
states are used (each one alone) as test pattern generators for
a given circuit, especially when the circuit has faults that
are random-pattern resistant. We demonstrate this point in
Section III, where it is also shown that LFSRs implementing nonprimitive polynomials may sometimes be preferable
to primitive LFSRs. In view of the significant differences
between different LFSRs and different initial states, it is
important to try and tailor the LFSR and its initial state to the
circuit under consideration before resorting to other methods
that might increase the area overhead involved in test pattern
generation, and/or increase the test application time.
The method proposed is based on establishing a small and
compactly described collection of (primitive and nonprimitive)
LFSRs and initial states, easily adjustable for any number of
circuit inputs. The collection of LFSRs and initial states is
established through a learning process first introduced in [23]
for the generation of deterministic test sets, and reviewed in
Section II. The learning process is applicable to a certain type
of circuits, and we use several such circuits to establish the
collection of test-pattern generators. Given an arbitrary circuit,
all LFSRs and initial states from the collection are simulated
as test pattern generators for the circuit, and the most suitable

10638210/98$10.00 1998 IEEE

POMERANZ AND REDDY: MATCH A TEST PATTERN GENERATOR TO A CIRCUIT-UNDER-TEST

one is selected. Thus, the learning process can be viewed as a

preprocessing step aimed at establishing the collection. Given
a random logic circuit, the learning process is not attempted.
Instead, an LFSR and initial state are selected out of the
collection established through preprocessing. For cases where
incomplete fault coverage is achieved by using LFSRs and
initial states from the collection, we propose several solutions,
as described next.
We propose a genetic optimization procedure that uses the
above collection of LFSRs and initial states as a starting point
to improve the final test pattern generator selected. Although
genetic optimization is known to be a time-consuming process,
its benefits in improving the LFSR and initial state selection
are significant.
In cases where even the genetic optimization procedure does
not result in complete fault coverage, two other techniques are
used. We show that by complementing the patterns produced
by an LFSR and applying the complemented patterns as well
as the uncomplemented ones to the circuit as test patterns,
the fault coverage can be increased beyond what is achievable
if the number of patterns produced by the original LFSR is
doubled. We consider the hardware overhead in producing
complemented patterns, and show an LFSR configuration that
requires only two additional inverters and multiplexers.
Finally, test-point insertion can be used to detect the faults
that remain undetected.
The following hardware overheads are involved in every
one of the methods above, and need to be balanced to achieve
the most suitable solution for the circuit under consideration.
Complementation of the LFSR patterns requires two additional
inverters and multiplexer, thus, the hardware overhead is fixed
and small. We therefore propose that complementation should
be used whenever it is effective in increasing the fault coverage
or reducing the test length. The LFSR selection processes
(selection from a given collection or selection by genetic
optimization) may result in LFSRs that have more XOR gates
than primitive LFSRs. The same benefits of increased fault
coverage and/or reduced test length, that can be achieved
by using the selection process, can sometimes be achieved
by using a primitive LFSR and adding test-points. Thus, the
number of additional XOR gates has to be balanced against
the overhead of adding test-points. We consider observation
points only in this work, since their hardware cost is lower
than that of control points. Observation test-points require
the addition of at least one primary output, or multiplexing
of the existing primary outputs with the test-points [24]. In
addition, there is a routing overhead involved in the use of
test-points. Depending on the circuit, the fault coverage and
test length can be optimized under a limited number of LFSR
XOR gates, and test-points can then be used to increase the
fault coverage or reduce the test length to the required level.
We show the tradeoff between test-points and LFSR XOR
gates where appropriate.
The paper is organized as follows. In Section II we present a
preliminary discussion of the learning process. In Section III
we consider specific circuits to which the learning process
was applied to collect a variety of rules describing effective
LFSRs and initial states. We consider both stuck-at faults

433

Fig. 1. A circuit configuration.

and transition faults in Section III. In Section IV we consider the incorporation of the rules learned into an automatic
procedure for selecting LFSRs and initial states. The use
of complemented as well as uncomplemented LFSR patterns
is considered in Section V. In Section VI we describe the
genetic optimization procedure used to improve the selection
of LFSRs and initial states. Concluding remarks are given in
Section VII.
II. PRELIMINARIES
Throughout this work, we consider the circuit configuration
shown in Fig. 1. An LFSR is connected to the circuit-undertest such that for every primary input of the circuit there is an
LFSR cell driving it. Other configurations were proposed to
reduce the LFSR length and increase the sharing of LFSRs
among various circuits in a system. One such configuration
(STUMPS [1]) uses an LFSR of fixed length (independent
of the number of circuit inputs), driving a shift-register. The
length of the shift-register is equal to the number of primary
inputs in the circuits connected to it, and every circuit input is
driven by a shift-register cell. For simplicity, we concentrate
on the configuration of Fig. 1 and assume that distributed test
generators [25] are used, one for each circuit in a system.
However, the method can be applied to other configurations.
We present results for one such configuration in Section IV-B.
We consider the problem of selecting the most effective
LFSR for a given circuit, where effectiveness is measured by
the fault coverage and the number of patterns to achieve it.
The method proposed is based on collecting effective LFSRs
and initial states through a learning process, first introduced in
[23] for the generation of deterministic test sets. The learning
approach from [23] is applicable to circuits that have a notion
of size associated with them, e.g., operand size, and has the
following steps.
Step 1: Small versions of the given circuit are obtained,
which have a similar structure to the given circuit, but smaller
size. For combinational circuits considered here, circuits with
small numbers of inputs implementing the same function are
obtained. For example, if the large circuit is a 64-bit multiplier,
then 2-bit, 3-bit and 4-bit multipliers may be obtained in this
step. The small circuits can be obtained through synthesis or
by extracting the lower order terms of the given circuit.
Step 2: The problem of interest is solved on the sequence
of small circuits obtained in Step 1. Exhaustive search is used

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 6, NO. 3, SEPTEMBER 1998

(a)

(b)
Fig. 2. LFSR realization.

for this purpose. Exhaustive search is applicable since only

small circuits are considered in this step.
Step 3: The solutions obtained for the small circuits are
studied, and common features are recorded as closed-form
analytic rules. For example, in the test generation problem
considered in [23], if the test patterns {00,11}, {000,111},
and {0000,1111} are included in the test sets of 2-, 3-, and
4-bit versions of the circuit, respectively, then the rules
and
are deduced, where
is the sequence obtained
times.
by repeating the sequence
Step 4: The rules learned are used to produce a solution
for the given circuit.
Next, we introduce the notation used to describe LFSRs
and initial states by analytic rules.
An -cell LFSR is represented by a binary vector denoted
where
if a feedback connection exists
if the
from the last cell of the LFSR to cell , and
connection does not exist [1]. The general realization of a
three-cell LFSR is shown in Fig. 2(a) and the realization of an
LFSR described by the binary vector 110 is shown in Fig. 2(b).
Every -cell LFSR (primitive or not) can be represented by a
. There are
such LFSRs, and
binary vector
initial states.
each one can be started from any one of
We are interested in sequences of LFSRs that can be described by closed-form rules. For example, the rule
(where
stands for
repetitions of the sequence )
corresponds to the LFSRs described by the binary vectors
. The first is the two-cell LFSR
11, 110, 1100, 11000,
, the second is the three-cell LFSR
, and
so on. Such rules allow us to compactly represent sequences
of LFSRs of various sizes. It is interesting to note that the
produces primitive LFSRs for certain values of
rule
(e.g., for
), and nonprimitive LFSRs for other values
, the connection polynomial of the LFSR
of (e.g., for
is divisible by
).
Next, we consider Step 2 of the learning procedure, as
applied to LFSRs, in more detail. We typically start with twoto six-input circuits. For each circuit, an exhaustive search
over all LFSRs and all initial states is performed, e.g., for a
three-input circuit, there are eight LFSRs and eight possible

initial states for each, yielding a total of 64 combinations (in

practice, the all-zero initial state and the LFSR described by
an all-zero vector are not useful, leaving 49 combinations for a
three-input circuit). For every LFSR and initial state, the LFSR
is allowed to go through all states starting from the initial
state considered, until a state visited before is reached. All the
states are applied to the circuit as test patterns and are fault
simulated. If complete fault coverage is achieved, the LFSR
used to generate the patterns, the initial state, and the smallest
number of patterns applied to achieve complete coverage are
recorded. These solutions are then used for the purposes of
learning rules in Step 3. The process of simulating all the
LFSRs and initial states for small versions of the circuit, and
recording the ones that achieve complete fault coverage, is
done automatically.
The list of all effective solutions may be large even for
small circuits. For example, for a six-input circuit, there are
4096 pairs of LFSRs and initial states, which may be too many
to consider for learning if all or most of them yield complete
fault coverage. When this situation is identified, we reconsider
the smaller circuits (typically, the 2- and 3-input circuits) in
order to eliminate some of the less effective (LFSR, initial
state) pairs (i.e., pairs that require large numbers of patterns
to achieve complete fault coverage). For this purpose, we
apply the learning process to the smaller circuits, typically
in order to select a few of the most effective initial states, i.e.,
initial states that achieve complete fault coverage using the
smallest numbers of patterns. The other initial states are then
discarded, thus reducing the number of (LFSR, initial state)
pairs for the smaller circuits. Next, several additional small
circuits (typically, four- to ten-input circuits) are considered
(automatically) under all LFSRs with the restricted set of
initial states selected as above. Again, fault simulation is
carried out for every LFSR and every initial state. The best
solutions recorded are then studied and rules to describe the
LFSRs and initial states corresponding to the best solutions
are noted. More than one rule is typically used to increase the
confidence in the results. Finally, all combinations of rules for
initial states and LFSRs are applied to large (target) circuits,
and the best combination is selected as the final result.
Since we are dealing with LFSRs, if the all-zero state is
reached, the LFSR remains in that state until a new state is
loaded. This implies that in most cases (even with nonprimitive
LFSRs), the all-zero test pattern cannot be applied to the
circuit-under-test. For circuits where the all-zero pattern is
necessary to detect some faults, several alternatives exist. (1)
In [26], it was shown how an LFSR can be modified by adding
a NOR gate to allow the all-zero state to be obtained. (2) It is
possible to use an LFSR that has one additional stage, which
does not drive any circuit input. This stage can be set to 1
when the other stages are set to 0 to apply the all-0 pattern.
The 1 in the additional stage will then take the other stages
out of the all-0 state. (3) The solution we selected is to load
two initial states, the all-zero state and another state, selected
using the method proposed here. We chose this option since
it proved to be the simplest to use. The actual implementation
can follow either one of the methods. To determine whether
the all-zero pattern is necessary, we first try to select an LFSR

POMERANZ AND REDDY: MATCH A TEST PATTERN GENERATOR TO A CIRCUIT-UNDER-TEST

A TRUTH-TABLE

TABLE I
3-BIT PRIORITY UNIT

FOR A

RESULTS

435

FOR

TABLE II
STUCK-AT FAULTS

IN

PRIORITY UNITS

and initial state without using the all-zero state. If it turns out
that no acceptable solution can be found, we add the all-zero
state and repeat the selection process. In all cases considered,
this correctly identified the circuits where the all-zero pattern
is necessary.
III. THE LEARNING PROCESS
In this section, we demonstrate the learning process by
applying it to derive test pattern generators for stuck-at faults
and transition faults in several functional units. Every one of
the units has a size parameter (operand length), that is used
to obtain small versions of the circuit for learning purposes.
The exhaustive generation of test pattern generators for small
circuits is done automatically, whereas the learning of rules to
describe them is done manually.
A. Stuck-at Faults in Priority Units
The first example we consider is the priority unit. An inputs and
outputs.
bit priority unit is a circuit with
The lowest-index input which assumes the value 1 sets its
corresponding output to 1. All other outputs are 0. A
truth table for a 3-bit priority unit is given in Table I for
illustration ( stands for a dont-care). We obtained gate
level implementations of priority units of several sizes.
When we applied the learning process to the priority units,
we found that the all-zero pattern is necessary to detect some
faults. We therefore used two initial states, namely, the allzero state and an additional state that was selected using
the proposed procedure. The selection of the LFSR and the
additional initial state is described next.
Considering all LFSRs and all initial states for two- to sixappears in
input priority units, we found that initial state
all the solutions and yields a small number of patterns. Another
, however, we decided to
candidate initial state was
and look for other options only if
turns out
use
, and
to yield poor results. We fixed the initial state to
proceeded to consider all possible LFSRs for the three- to sixinput priority units. Studying the LFSRs obtained, we derived
the following rules to describe the most effective ones (all
).
with initial state
(describes the LFSRs 101, 1001, 10001,
Rule 1:
);
100001,
(describes the LFSRs 110, 1100, 11000,
Rule 2:
);
110000,
where
and the diRule 3:
vision is integer division, i.e., the result is truncated
(describes the LFSRs 101, 1001, 11011, 110011,
).
1110111,

Note that both the first and the third rule correspond to the
same 3-bit and 4-bit LFSRs but generate different LFSRs of
5 bits or more. The second rule was the best of the three in
terms of test length, however, we retained all of them for the
purpose of comparison.
The results of applying the LFSRs described by the rules
given above to priority units of different sizes are given in
Table II. Every LFSR was allowed to go through at most
50 000 states (including the all-zero state). For every LFSR, we
give the number of patterns required before the fault coverage
reported in Table II was reached. For example, for the 40-bit
priority unit and the first LFSR in Table II, the last pattern
effective in detecting any fault was pattern 21 826, and the
fault coverage achieved was 55.63%. It is interesting to note
the differences between the different results obtained. The
first and third LFSRs sometimes resulted in incomplete fault
coverage. In all cases, the results obtained by the second LFSR
were significantly better than the other results in terms of the
number of test patterns required to completely test the priority
unit. This could have been predicted by observing that the
second rule required the smallest number of tests for the twoto six-input circuits. Table II demonstrates the importance of
selecting an appropriate LFSR, tailored to the circuit-undertest. Note that although the learning process was done for 2to 6-bit circuits, the LFSRs learned are effective for all the
circuits considered. This property is essential to the proposed
method that relies on the existence of such similarities between
different-size versions of the same circuit. Using Rule 2 for
an -bit priority unit, we expect 100% fault coverage to be
tests.
achieved by
To further establish the need for a systematic way of
selecting the best LFSR and initial state, we simulated the
32-input priority unit (which is one of the largest considered)

436

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 6, NO. 3, SEPTEMBER 1998

using all five primitive 32-bit LFSRs from [27] as test pattern
generators. For every one of these five LFSRs, ten different
nonzero seeds were randomly selected, in addition to the allzero state. The all-zero state was included in each case. Each
LFSR was allowed to go through up to 3000 states, applying
3000 test patterns to the circuit-under-test. The best result was
with initial state
obtained for the LFSR
10001110110101100001101011011101, giving 70.45% fault
coverage achieved by the first 326 patterns (the following
2674 patterns applied did not detect any additional fault).
Allowing one of the five primitive LFSRs to produce 100 000
test patterns starting from 10 different randomly selected
initial states, the best fault coverage achieved was 78.54%
with 66 273 patterns. An arbitrarily selected nonprimitive
polynomial from the list in [27] which was used in the same
manner yielded 76.52% fault coverage with 57 632 patterns.
Comparing to the best result in Table II, it can be seen that 95
patterns were sufficient to achieve complete fault coverage
when the LFSR was appropriately selected. In this case,
the LFSRs selected through learning are significantly more
effective than other LFSRs. Furthermore, it should be noted
that the best result obtained from 60 trials using arbitrarily
seeded primitive and nonprimitive LFSRs was considerably
inferior to the best result obtained from three trials using the
LFSRs deduced by the learning process.
For the 32-bit circuit, the number of XOR gates in the LFSR
learned is one. The number of XOR gates in the best primitive
LFSR is four. Thus, the LFSR learned also incurs a lower
hardware overhead than the best primitive LFSR.
B. Stuck-at Faults in Carry-Lookahead Functions
In this section, we consider a circuit similar to that implementing the carry-propagate function of a carry lookahead
, implecircuit. The -input circuit, with inputs
ments the function

where

is even. For example, for

, the function is
.
Of all the LFSRs and initial states obtained by exhaustively
trying all LFSRs and initial states for the circuits with
and , the smallest numbers of patterns were obtained for
. All viable initial states yielded
the LFSRs described by
the same number of patterns in this case, however, the only
one that seemed amenable to generation by a closed-form rule
, that produces initial states 01 for
, 0101
was
, etc., ( is even in this case. In general, we write
for
% , where % is the modulo operator,
this rule as
, 01010 for
, etc.).
to obtain 010 for
We used the above rules to generate test patterns for circuits
with 4 to 32 inputs. For all the circuits, 100% fault coverage
was obtained. The number of patterns required to achieve
.
complete coverage for the -input circuit was
For comparison, we used five primitive LFSRs of degree
16 from the list in [27], each with ten different seeds, to
generate tests for the 16-input circuit. Up to 10 000 patterns
were applied to each circuit. The highest fault coverage

achieved was 93.55%, and it was achieved after 9890 patterns.

In this case, the results of learning (100% fault coverage
using 17 patterns) are significantly better than those achieved
by arbitrarily selected primitive LFSRs. We also used a
nonprimitive LFSR arbitrarily selected from the list in [27]
for a similar experiment with ten randomly selected initial
states. The highest fault coverage achieved was 91.94% after
8721 patterns.
Since the LFSR learned,
, requires 15 XOR gates,
whereas the best primitive LFSR requires only seven XOR
gates, we checked how many test-points are required to
achieve complete fault coverage when the primitive LFSR is
used. A single test-point was required to achieve complete
fault coverage when the primitive LFSR was used. Thus, the
overhead of eight additional XOR gates has to be balanced
against one test-point and a longer test sequence.
C. Transition Faults in Priority Units
In this section, we consider the priority units of Section IIIA under transition faults. Transition faults require two-pattern
tests. A primitive LFSR to which the all-zero state is added is
guaranteed to generate all single patterns, and it is therefore
guaranteed to achieve complete coverage of stuck-at faults.
However, it is not guaranteed to generate all two-pattern tests.
Therefore, it may not always be possible to achieve complete
coverage of transition faults. Our goal is therefore to maximize
the fault coverage.
To select an LFSR and initial state for priority units, we
first generated all the combinations of LFSR and initial state
for the four-, five-, and six-input priority units, and recorded
the pairs that yielded the maximum fault coverage. In all
cases, the all-zero initial state was used as well. The best
fault coverage and smallest test length was achieved by the
LFSRs 1100, 11000 and 110000, started from initial states
1011, 10111, and 101111, respectively. We therefore selected
with initial state
. We applied
the LFSR
this combination to priority units of various sizes (up to 100
inputs). The results obtained are summarized by the following
formulae applicable to an -bit priority unit.
.
1) The total number of transition faults is
2) The number of transition faults left undetected is
.
3) The fault coverage is therefore
FC
4) FC
% as
.
.
5) The number of tests is
For comparison, we used five primitive LFSRs of degree 32
and a nonprimitive LFSR of degree 32 arbitrarily selected from
the list in [27] for the 32-bit priority unit. Each LFSR was used
with ten different seeds, in addition to the all-zero initial state.
Up to 10 000 patterns were applied to each circuit. The highest
fault coverage achieved was 57.70%, and it was achieved after
4832 patterns. In this case, the results of learning (93.32%
fault coverage using 125 patterns) are significantly better than
those achieved by arbitrarily selected LFSRs. In addition, the

POMERANZ AND REDDY: MATCH A TEST PATTERN GENERATOR TO A CIRCUIT-UNDER-TEST

number of XOR gates in the LFSR learned is one, whereas

the number of XOR gates in the best primitive LFSR is 12.

437

TABLE III
RULES FOR GENERATING LFSRs AND INITIAL STATES.
(a) RULES FOR LFSRs. (b) RULES FOR INITIAL STATES

D. Transition Faults in Carry-Look-Ahead Functions

We consider the carry-look-ahead functions of Section IIIB under transition faults. As for the priority unit, we used
the all-zero initial state in addition to a selected initial state.
For the four-input circuit, the LFSR 1111 with initial state
1101 detected all 14 faults. For the six-input circuit, the
LFSR 111111 with initial state 110101 detected all 22 faults.
and applied it, with all
We concentrated on the LFSR
initial states, to the eight-input circuit. The most suitable initial
state was 11010101 that detected all 30 faults. We, therefore,
with initial state
.
selected the LFSR
From the results of applying these rules to larger carrylook-ahead circuits (up to 30 inputs), we can predict the total
, the number of faults left undetected
,
number of faults
for an -input circuit as follows:
and the number of tests

For comparison, we used five primitive LFSRs of degree

16 and a nonprimitive LFSR of degree 16 arbitrarily selected
from the list in [27] for the 16-bit carry-look-ahead circuit.
Each LFSR was used with ten different seeds, in addition to
the all-zero initial state. Up to 10 000 patterns were applied to
each circuit. The highest fault coverage achieved was 74.19%,
and it was achieved after 8888 patterns. The results of learning
(100% fault coverage using 18 patterns) are significantly better
than those achieved by arbitrarily selected primitive LFSRs.
The number of XOR gates in the LFSR learned for the 16bit circuit is 15. The number of XOR gates in the best primitive
LFSR is nine. We therefore inserted test-points to achieve the
maximum fault coverage using the primitive LFSR. Seven testpoints were required to achieve complete fault coverage using
the primitive LFSR.

(a)

(b)
TABLE IV
ADDITIONAL RULES FOR GENERATING LFSRs AND INITIAL
STATES. (a) RULES FOR LFSRs. (b) RULES FOR INITIAL STATES

(a)

E. Summary
In summary, it can be seen that learning based on binary
LFSR connection patterns and initial states is very effective
for matching LFSR-based test pattern generators to circuits
that have size parameters. The learned LFSRs and initial
states are considerably more effective than arbitrarily selected
ones. In the next sections we propose methods to match test
pattern generators to circuits that do not have recognizable
size parameters.
IV. SELECTING AN LFSR AND AN INITIAL
STATE FOR A RANDOM LOGIC CIRCUIT
In this section, we consider the application of the rules
collected in the previous section and in additional experiments
to random logic circuits. The circuits considered are in general
neither related to the example circuits studied in the previous
section, nor have recognizable size parameters. We compare
for these circuits the following test pattern generators. 1) The
best LFSR of an appropriate size selected out of the collection
established in experiments similar to the ones of Section III.

(b)

2) The best among arbitrarily selected primitive LFSRs with

randomly selected initial states. The experiments show that
LFSRs out of the collection are more effective than randomly
selected primitive ones. We consider stuck-at faults in this
section.
A. Single Circuits
We incorporated the rules shown in Table III, which were
learned in Section III and in [28] for stuck-at faults, into a
program. To increase the effectiveness of the program, we
augmented the rules of Table III by additional rules, shown
in Table IV. The rules of Table IV were all discerned for
some of the small circuits considered in Section III and other
circuits considered in [28]. Tables III(a) and IV(a) give the
rules for generating the LFSRs and Tables III(b) and IV(b)

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RESULTS

FOR

TABLE V
BERKELEY PLAs (INCOMPLETE COVERAGE)

give the rules for generating the initial states. The program
implementing these rules proceeds as follows. Given a circuit,
the program tries every pair of (LFSR, initial state) as a test
pattern generator for the circuit, and reports the fault coverage
achieved and the number of patterns required to achieve it.
The best test pattern generator is then selected. If desired,
the program can also provide a list of undetected faults. This
list can be used for test-point insertion. The run time of this
be the number
program can be determined as follows. Let
of (LFSR, initial state) pairs tried. Let the TPGs be allowed
to go through states, producing test patterns. Suppose that
the time to fault simulate the circuit under test patterns is
. Then the total run time is approximately
.
Next, we report the results of experiments on multilevel
implementations of Berkeley PLAs [29], the combinational
which is
logic of ISCAS-89 benchmark circuits [30],
an ISCAS-85 benchmark circuit [31] and other ISCAS-85
benchmark circuits, and circuits from [32]. All the circuits
considered have faults that need large numbers of random
patterns to be detected.
For Berkeley PLA multilevel circuits, we tried all combinations of LFSRs and initial states given in Table III and
allowed up to 10 000 test patterns. We then added the rules
of Table IV, and repeated the experiment. We also used a
primitive LFSR from [1] with ten randomly selected initial
states. The best results obtained by both methods are reported
in Table V, as follows. For every one of the methods, we
give the best result in terms of fault coverage, followed by
the smallest number of patterns to achieve this fault coverage.
In parentheses we give the results obtained when the rules of
Table IV are added to the rules of Table III. It can be seen
that in most cases, the fault coverage obtained by the LFSRs
from Table III (or Tables III and IV) is higher than the fault
coverage achieved by primitive LFSRs. Note especially the
case of rckl, where a primitive LFSR resulted in 49.86% fault
coverage and the collection of Table III resulted in 97.28%
fault coverage. We repeated the experiment where primitive
LFSRs are used, this time applying 100 000 random patterns
to rckl. The highest fault coverage achieved was 71.66%, still
lower than what can be achieved with the LFSRs of Table III
, where the
with 991 patterns. Note also the case of
additional rules of Table IV resulted in a test pattern generator
that achieves complete fault coverage. The number of XOR
gates is lower in most cases when the LFSRs learned are
used. For all the circuits considered, an improvement in test set
size and/or fault coverage is achieved without increasing the

RESULTS

FOR

TABLE VI
ADDITIONAL BENCHMARK CIRCUITS

number of XOR gates. Thus, an LFSR better than a primitive

one can be selected at the cost of a one-time investment in
computation time.
We also applied the rules of Table III to ISCAS-85 benchwhich is considered below, to
mark circuits excluding
the combinational logic of ISCAS-89 benchmark circuits, and
to circuits from [32] that have random pattern resistant faults.
For comparison, we used a primitive LFSR from [1] with 10
randomly selected initial states. We allowed up to 10 000 test
patterns in both experiments. The best results obtained by both
methods are reported in Table VI.
, an ISCASNext, we applied the rules of Table III to
85 benchmark circuit known to have faults that cannot be
detected by practical numbers of random patterns. We used
an LFSR from [1] started from two randomly selected initial
states and allowed up to 100 000 patterns to be generated
in each case. The best fault coverage achieved was 85.73%
with 94 732 patterns (the other initial state resulted in 85.40%
fault coverage after 85 580 patterns). We then used the rules
of Table III, and allowed up to 10 000 patterns in each case.
The highest fault coverage achieved was 89.41% after 8608
patterns (note that only 10 000 patterns were applied). We selected the combination of LFSR and initial state from Table III
that resulted in the highest fault coverage, and allowed it to
generate 100 000 patterns. The highest fault coverage achieved
was 89.95% with 86 826 patterns. A difference of over 4%
in the fault coverage between the method proposed here and
arbitrarily selected LFSRs can have a measurable effect on
the hardware overhead required to achieve complete fault
coverage for this circuit. If hardware overhead is not allowed,
then at the cost of additional computation time it is possible
to select a better LFSR than a primitive one.
The results of this section and the previous one show the
importance of matching an LFSR and initial state to the circuitunder-test. Moreover, by performing the learning process for
a small number of functional units, we could find a collection
of LFSRs and initial states that was superior to arbitrarily
selected primitive LFSRs and initial states in most of the
cases considered. Additional learning is expected to increase
the effectiveness of the method even further. In the following
sections, we consider methods to further improve the LFSR
and initial state selection.
B. Pairs of Circuits
Next, we show the effectiveness of the LFSR collection
in another experiment, where the same test-pattern generator

POMERANZ AND REDDY: MATCH A TEST PATTERN GENERATOR TO A CIRCUIT-UNDER-TEST

NUMBERS

OF

TABLE VII
LFSRs FOR PAIRS

Fig. 3. Circuit structure for the experiment.

is used to generate tests for two different circuits. The circuit

configuration is shown in Fig. 3. This configuration potentially
reduces the area overhead compared to distributed BIST by
allowing test-pattern generators to be shared among various
circuits. The problem in this case is to select the test-pattern
generator which is most effective for the combination of two
circuits. The test-pattern generators we consider are made up
of one or more LFSRs. The number of LFSRs is determined
as the smallest number that allows complete fault coverage to
be achieved for both circuits. In the worst case, the number of
LFSRs required for two circuits is the sum of the numbers of
LFSRs required for the individual circuits. However, since the
same LFSR may be useful for different circuits, the number of
LFSRs may be significantly reduced. Our goal is to determine
this reduction.
The test-pattern generator selection procedure consists of
repeatedly selecting the best LFSR and initial state from
Table III. Each (LFSR, initial state) pair is allowed to run
patterns,
until the fault coverage does not improve for
is the number of primary inputs, but not more
where
than 100 000 patterns. The best pair is the one that detects the
maximum number of yet-undetected faults. If the test-pattern
generator drives two circuits, then the yet-undetected faults in
both circuits are considered. The selection process is repeated
until complete fault coverage is achieved for all the circuits
connected to the test-pattern generator.
We considered circuits with approximately equal numbers of
inputs, between 27 and 45, among Berkeley PLAs considered
above and the combinational logic of ISCAS-89 benchmark
circuits. In addition, we considered three functional units

OF

439

CIRCUITS

including a 32-bit priority unit (called prior), a 32-bit carrylookahead function (called cla), and a 32-bit circuit consisting
of a 32-input AND gate and a 32-input OR gate connected in
parallel (called andor). All the circuits considered are random
pattern resistant in that a primitive LFSR from [1] applying
100 000 pseudorandom patterns starting from each one of
five randomly selected initial states does not achieve 100%
coverage of detectable faults for any initial state.
We first applied the test-pattern generator selection procedure to each circuit separately. The purpose of this experiment
was to find out how many test-pattern generators from the list
of Table III are required for each circuit. Next, we considered
pairs of circuits driven from the same source (cf. Fig. 3).
When the number of inputs of the two circuits considered
was not equal, we assumed that the lower-index inputs of the
two circuits are driven by the same LFSR cells. The results
are reported in Table VII. Next to each circuit name, we give
the number of (LFSR, initial state) pairs required to achieve
complete fault coverage for the circuit. For each pair of circuits
considered, we give in Table VII the number of (LFSR, initial
state) pairs required to achieve complete fault coverage. The
number is followed by if the number of pairs for the two
circuits is smaller than the sum of the numbers of pairs for the
two circuits separately; it is followed by if the number of
pairs for the two circuits is equal to the sum of the numbers
of pairs for the two circuits separately. It can be seen that in
many of the cases considered, the number of pairs required
is smaller than the sum of the number of pairs for Circuit 1
,
and Circuit 2. Moreover, in some cases, like rckl and
the number of pairs required for the interconnection is smaller
than the number of pairs required for one of the circuits alone
(rckl in this case). This can happen when the other circuit has
a larger number of inputs, and therefore requires the use of
pairs of larger size which can sometimes be more effective for
the smaller circuit, or when the number of patterns generated
for the interconnection is larger than for each circuit alone.
C. Discussion
The experimental evidence above suggests that the rules of
Tables III and IV produce LFSRs that are effective as test
pattern generators for arbitrary circuits. These rules should
therefore be tried before resorting to other methods having

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WEIGHTS

FOR THE

LFSRs

TABLE VIII
TABLES III

OF

higher hardware overheads. However, there is no known

theoretical argument to explain why the rules of Tables III
and IV produce effective LFSRs. In an attempt to offer an
explanation, we checked whether the LFSRs of Tables III and
IV operate as weighted-random pattern generators. Weighted
random pattern generators are known to be more effective
than pure random ones for some circuits. For this purpose,
we considered the LFSRs of Tables III(a) and IV(a) under
several initial states from Tables III(b) and IV(b). For each
LFSR and initial state, we allowed the LFSR to generate
10 000 patterns. We define the weight associated with Cell
of the LFSR as the number of patterns in which Cell
produces the value one, divided by the total number of patterns
10 000. The results under initial state 8 of Table III are shown
in Table VIII. Similar results were obtained for other initial
states. Each row of Table VIII corresponds to a different LFSR
length from 15 to 32 followed by 233 (which is the number
). The entries in the table are the minimum
of inputs of
and maximum weights obtained for all the LFSR cells. It can
be seen that for different numbers of inputs, the same LFSR
may produce different weights. In most cases, the weights are
uniform across the various cells. In other cases, the weights
, the best LFSR
vary from one input to the next. For
selected in Section IV-A was LFSR number 5 with initial state
8. It can be seen from Table VIII that for this LFSR and initial
state, the weights vary between 0.28 and 0.52.
V. THE USE

OF

COMPLEMENTED PATTERNS

To increase the effectiveness of a given LFSR and initial

state as a test pattern generator, we consider in this section a
scheme where each pattern produced by the LFSR is applied
to the circuit-under-test both in its uncomplemented and in its
complemented form. We first present experimental evidence
of the effectiveness of this scheme. We then consider the
hardware overhead involved.

AND

IV (INITIAL STATE 8)

RESULTS

FOR

TABLE IX
BERKELEY PLAs WITH COMPLEMENTED PATTERNS

To show the effectiveness of using complemented patterns,

we repeated the experiments of Section IV-A, this time using
both uncomplemented and complemented patterns. For Berkeley PLA circuits, we applied a total of 10 000 patterns, 5000 of
them uncomplemented and 5000 of them complemented. The
results for the circuits considered in Table V are shown in
Table IX. In contrast to Table V where only uncomplemented
patterns were used, complete fault coverage is achieved by
the LFSRs based on learning when complemented patterns
are used for four of the five circuits. Comparing the data
in Tables V and IX, it can be noted that for pure random
patterns, complementing the patterns does not improve the
fault coverage significantly, and in most cases application of
additional uncomplemented patterns is preferred over applying the same patterns in complemented form. This can be
explained as followed. Pure random patterns have equal probabilities of containing a 0 or a 1 in a given position. By
complementing a random pattern, the probabilities of obtaining
0s and 1s remain the same. Thus, complemented and
uncomplemented patterns have the same characteristics, and
once the fault coverage using uncomplemented patterns has
saturated, the use of complemented patterns cannot improve
it significantly. In contrast, many of the learned LFSRs
do not produce pure random patterns. Thus, complemented

POMERANZ AND REDDY: MATCH A TEST PATTERN GENERATOR TO A CIRCUIT-UNDER-TEST

441

(a)

(b)

(c)
Fig. 4. An LFSR producing complemented patterns.

patterns have different characteristics than uncomplemented

ones. Once the fault coverage of the uncomplemented patterns
has saturated, the use of complemented patterns can increase
it further.
We also used the LFSRs and initial states of Table III to
. We then applied each one
produce 50 000 patterns for
of the patterns produced uncomplemented and complemented,
for a total of 100 000 patterns. The highest fault coverage
achieved was 94.03%, compared to a fault coverage of 89.95%
when 100 000 patterns were used without the provision for
applying complemented test patterns. The primitive LFSR
from [1], when used in a similar experiment with two randomly
determined initial states, resulted in 85.95% fault coverage,
compared to 85.73% when complemented patterns are not
used.
Due to the effectiveness of applying complemented patterns
produced by an LFSR, we use this scheme in the following
sections. The hardware involved is considered next.
A straightforward way of obtaining complemented patterns
flip-flops
is to use the complemented outputs of the LFSR
to drive the circuit-under-test. To select between uncomplemented and complemented patterns, multiplexers need to be
placed between the LFSR and the inputs of the circuit-undertest. The multiplexers would be driven by both outputs of
flip-flops, and a select input would determine
the LFSR
which one drives the corresponding circuit input. The main
disadvantage of this scheme is that extra logic (multiplexers)

needs to be placed on the signal path in the circuit, thus

increasing its delay. We propose an alternate scheme where
only two inverters and two multiplexers are required, and
they are placed between the LSFR cells similar to the BILBO
configuration. Thus, they do not affect the circuit delay during
normal operation. By setting a control signal, the LSFR can
be configured in one of two ways, shown in Fig. 4. Fig. 4(a)
shows the configuration for uncomplemented patterns, which
is the same as the one shown in Fig. 2. Fig. 4(b) shows the
concept behind the configuration for complemented patterns.
In Fig. 4(b), the LFSR has to be loaded with the complemented
initial state, and it stores the complemented patterns. To ensure
that the next state of the LSFR is the complement of the
next state in the uncomplemented case, the inputs of the
XOR gates are complemented by placing additional inverters.
This yields the XOR input values in the uncomplemented
case, and the XOR gates compute the same values as in the
uncomplemented case. The outputs of the XOR gates are then
complemented to provide the complemented result to the next
LFSR cell. Thus, two inverters are required around every XOR
gate. In addition, the output of the last LFSR stage and the
input to the first stage are complemented. The configuration
of Fig. 4(b) can be simplified by using the property that
. This allows us to use two inverters, as
shown in Fig. 4(c). Two multiplexers are required to determine
whether the complemented or uncomplemented patterns are
applied.

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 6, NO. 3, SEPTEMBER 1998

TABLE X
RESULTS FOR STUCK-AT FAULTS IN c2670 (233
INPUTS, 2747 FAULTS, 117 REDUNDANT FAULTS)

VI. IMPROVING THE SELECTION

PROCESS BY GENETIC OPTIMIZATION
In this section, we consider the selection of an LFSR and
an initial state for a random logic circuit by starting from an
initial collection of (LFSR, initial state) pairs and applying a
genetic optimization procedure [33] to improve them. Genetic
optimization has been shown to be effective for various design
automation problems, and is expected to improve the selected
LFSRs as well.
The details of the genetic optimization procedure are
briefly described next. We use the standard representation
of bit-vectors for LFSRs and initial states, and the onepoint crossover operator. To perform crossover between two
(LFSR, initial state) pairs, we perform crossover between
the two LFSRs and between the two initial states separately.
Crossover between two LFSRs (or two initial states) and
is performed by randomly selecting a position (the crossover
up to
point), and copying into a new vector the part of
position , and the part of
from position . The quality
of a pair (its fitness function value) is determined based on
the number of faults detected by the test patterns it produces,
and the number of test patterns required to achieve this fault
coverage. The higher the number of faults detected, the better
the pair. In addition, for the same number of detected faults,
a pair is considered better if it requires fewer test patterns
to detect the faults. We used 20 (LFSR, initial state) pairs in
each iteration of the genetic optimization procedure, and a
mutation rate equal to one over twice the number of primary
inputs. Next, we report the results obtained by performing
genetic optimization.
. We use the
We first consider stuck-at faults in
LFSRs and initial states of Table III as a starting point,
and apply genetic optimization to generate new pairs with
increased fault coverage and reduced numbers of tests. The
results are shown in Table X. In Table X, stands for the
iteration index. After the iteration index, we give the number
of faults detected, the fault coverage and the fault efficiency
(fault efficiency is computed as the number of faults detected,
divided by the number of detectable faults). In the last column,
we give the number of tests until the final fault coverage was
are the results using the LFSRs
achieved. The results for
and initial states of Table III unmodified. Table X includes the
results of several experiments, as follows.
Experiment 1: We used 50 iterations of the genetic optimization procedure with 20 pairs of (LFSR, initial state) in
each iteration. The number of test patterns used was 10 000,

applied as follows. 5000 different patterns are generated. They

are applied as they are, then they are complemented and
applied again in their complemented form. The fault coverage
achieved after 20 iterations is 94.61% with a fault efficiency
of 98.82%. After 50 iterations, the fault coverage is 95.49%
with a fault efficiency of 99.73%.
Experiment 2: We restarted Experiment 1 with the best
solution obtained after 50 iterations. After 44 additional iterations, the fault coverage achieved was 95.56% with a fault
efficiency of 99.81%.
The final LFSR and initial state obtained after Experiment
2 for
leave five detectable faults uncovered. Testpoint insertion to detect these faults required two test-points.
We also applied the test-point insertion procedure to
with the primitive LFSR and initial state that yielded 85.73%
in Section IV (100 000 uncomplemented patterns) and with
the primitive LFSR and initial state that yielded 85.95% in
Section V (50 000 uncomplemented and 50 000 complemented
patterns). For both pairs, three faults were never activated,
and therefore, could not be detected after test-point insertion
(we only considered observation points in this work). Three
test-points were inserted to detect the remaining faults.
We also applied genetic optimization to the test-pattern
generators for transition faults. The initial set of pairs is
selected as follows. Five rules to create an LFSR are included.
Three of them were learned for the examples of Section III
and other examples, namely,
;
1)
;
2)
.
3)
The fourth rule describes a shift register, which turned out to
be useful in some cases.
.
4)
The fifth LFSR is a primitive LFSR from [1] that varies
with the number of circuit inputs.
The initial states used are the following. They were also
learned during the experiments of Section IV and other experiments as follows:
;
1)
% ;
2)
% ;
3)
.
4)
The initial set of solutions included every pair of LFSR and
initial state from the above set (for a total of 20 pairs). Each
pair of (LFSR, initial state) was allowed to produce up to 5000
patterns, which were then applied both uncomplemented and
complemented. The fault coverage for rckl was improved from
, the fault coverage
86.24% to 92.75% in 3 iterations. For
was improved from 94.58% to 98.28% after 10 iterations.
VII. CONCLUDING REMARKS
We demonstrated that different (primitive or nonprimitive)
LFSRs may yield different fault coverages and test lengths
when used as test pattern generators. Thus, before resorting
to weighted random patterns or other methods with higher
hardware overhead than pure random pattern generation, the

POMERANZ AND REDDY: MATCH A TEST PATTERN GENERATOR TO A CIRCUIT-UNDER-TEST

possibility of tailoring an LFSR to the circuit-under-test should

be explored. We first proposed a learning method to select an
LFSR and an initial state to form a test pattern generator for a
given circuit. The learning method is applicable to circuits that
have a size parameter. Under this method, an exhaustive search
over all LFSRs and all initial states is first performed for small
circuits. Based on the most effective LFSRs for the small
circuits, rules are derived that allow the generation of suitable
LFSRs for larger circuits. The method was demonstrated on
several types of circuits. The collection of rules resulting from
the learning process was then applied to random logic circuits.
The collection was shown to result in test pattern generators
that are effective in achieving high fault coverage for random
logic circuits as well. We argued that the collection of LFSRs
and initial states is effective for random logic circuits since
it includes LFSRs that produce weighted-random patterns.
LFSRs that produce both complemented and uncomplemented
test patterns were shown to increase the fault coverage at the
cost of a low hardware overhead. The collection was then
used as a starting point for a genetic optimization process that
improves the LFSR and initial state selected. Finally, test-point
insertion was used where appropriate to achieve complete
fault coverage when a single LFSR and initial state could not
achieve such fault coverage.

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Irith Pomeranz (M89SM96) received the B.Sc.

degree (summa cum laude) in computer engineering
and the D.Sc. degree from the Department of Electrical Engineering at the TechnionIsrael Institute
of Technology, Haifa, Israel, in 1985 and 1989,
respectively.
From 1989 to 1990, she was a Lecturer in the
Department of Computer Science at the Technion.
In 1990, she joined the Department of Electrical and
Computer Engineering at the University of Iowa,
Iowa City, where she is currently a Professor. Her
research interests are testing of VLSI circuits, design for testability, synthesis
and design verification.
Dr. Pomeranz is a recipient of the NSF Young Investigator Award in 1993,
and of the University of Iowa Faculty Scholar Award in 1997. From 1995 to
1997, she served as an Associate Editor of the ACM Transactions on Design
Automation, and as a Guest Editor of the IEEE TRANSACTIONS ON COMPUTERS,
Special Issue on Dependability of Computing Systems, January 1998.

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 6, NO. 3, SEPTEMBER 1998

Sudhakar M. Reddy (M68SM84F87) received the undergraduate degree in electrical

and communication engineeing from Osmania
University, the M.S. degree from Indian Institute
of Science, India, and the Ph.D. degree in electrical
engineering from the University of Iowa, Iowa City.
Since 1972, he has been active in the areas
of testable designs and test generation for logic
circuits. Since 1968, he has been a member of
the Faculty of the Department of Electrical and
Computer Engineering, University of Iowa, where
he is currently the Department Chairman. In 1990, he was made a University
of Iowa Foundation Distinguished Professor.
Dr. Reddy is a member of Tau Beta Pi, Eta Kappa Nu, and Sigma Xi. He has
been an Associate Editor and twice a Guest Editor of the IEEE TRANSACTIONS
ON COMPUTERS. He is an Associate Editor of the IEEE TRANSACTIONS ON
COMPUTER-AIDED DESIGN.