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Content
1. Introduction to digital system design (Mar. 11) (by Ying-Shieh Kung)
Introduction to FPGA
Introduction to VHDL
Case study in controller and filter design using VHDL
2. ModelSim/Simulink co-simulation (Mar. 18) (by Nguyen Phan Thanh )
Introduction to ModelSim Simulation
Introduction to ModelSim/Simulink co-simulation
Case study
3. FPGA implementation (Mar. 25) (by Risfendra)
Refer from:
Prof. Ying-Shieh Kung, Teaching Material, 2014.
Volnei A. Pedroni, Circuit Design and Simulation with VHDL,
Second Edition, The MIT Press, 2010.
3
1. Open a project
(project file)
testbench file
original VHDL code
3. Compile
Counter.vhd
library ieee;
use ieee.std_logic_1164.all;
use Ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-----------------------------------------ENTITY counter IS
PORT(
clk, count_ena
: IN
BIT;
clear, load, direction
: IN
BIT;
p
: IN
INTEGER RANGE 0 TO
255;
max_min
: OUT BIT;
qd
: OUT INTEGER RANGE 0 TO
255);
END counter;
-----------------------------------------ARCHITECTURE a OF counter IS
BEGIN
PROCESS (clk, clear, load)
VARIABLE cnt
: INTEGER RANGE 0 TO 255;
BEGIN
IF (clear = '0') THEN
-- Asynchrnous clear
cnt := 0;
ELSIF (load = '1' and clear = '1') THEN -- Asynchronous
load
cnt := p;
ELSE
IF (clk'EVENT AND clk = '1') THEN
IF (count_ena = '1' and direction = '0') THEN
cnt := cnt - 1;
ELSIF (count_ena = '1' and direction = '1') THEN
cnt := cnt + 1;
END IF;
END IF;
END IF;
qd <= cnt;
Counter_tb.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
----------------------------------ENTITY counter_tb IS
END counter_tb;
----------------------------------------ARCHITECTURE testbench of counter_tb IS
----- counter declaration --------------COMPONENT counter
PORT ( clk, count_ena
: IN
BIT;
clear, load, direction
: IN
BIT;
p
: IN
INTEGER RANGE 0 TO 255;
max_min
: OUT BIT;
qd
: OUT INTEGER RANGE 0 TO 255);
END COMPONENT;
BEGIN
----- counter_1 instantiation --------------Counter_1: counter PORT MAP (clk, counter_ena,
clear, load, direction, P, max_min, qd);
----- Stimuli generation -------------clk <= NOT clk AFTER 40ns;
clear <= '1' AFTER 0ns;
counter_ena <= '1' AFTER 0ns;
load <= '0' AFTER 0ns;
direction <= '1' AFTER 0ns;
P <= 20 AFTER 0ns;
END testbench;
4. Simulation
Compilation result
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5. Add waveform
Choose Sim tab
Right click counter_tb => Add => Add to Wave
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6. Running
Simulation results
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7. End Simulation
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B. Introduction to
ModelSim/Simulink Co-simulation
For ModelSim 5.7d
Matlab 8.0
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ModelSim
y=f(x)
Co-simulate ModelSim/Simulink
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>> configuremodelsim
(Step 1)
(Step 2)
ModelSim SE 5.7d
(Step 3)
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>> configuremodelsim
Identify the ModelSim installation to be configured for MATLAB and Simulink
Do you want configuremodelsim to locate installed ModelSim executables [ y ] / n ? y
Select a ModelSim installation to be configured:
[1] C:\Modeltech_5.7d\win32
[0] None
ModelSim SE 5.7d
(Open ModelSim)
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2. ModelSim
2.1. Create new project
- File => New => Project
- Type counter (any project name)
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(Step 1)
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2.6. Simulation
-
# Reading C:/Modeltech_5.7d/tcl/vsim/pref.tcl
# do {D:/Softwares/MATLAB/R2008a/bin/tp2eb1637e_fa87_4651_9eb1_209b9189e1d8}
# Loading project counter
# Compile of 220model.vhd was successful.
# Compile of 220pack.vhd was successful.
# Compile of counter.vhd was successful.
# 3 compiles, 0 failed with no errors.
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3. Matlab
3.1. Create new model
- At main window, type Simulink
- At Simulink Library Browser, choose EDA Simulator Link MQ
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Display 1
clear
1
qd
Convert
clear
Constant 5
load
qd
0
Convert
load
Display 3
Constant 1
direction
1
Convert
direction
Convert
count _ena
Constant 2
count _ena
max _min
max _min
Constant 3
bin 0
Display 6
20
HDL Cosimulation
int 8
Constant 4
HDL Cosimulation
Display 2
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ModelSim/Simulink Co-simulation
Case study
- Sum of Product (SoP)
- Filter Design
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0.2
Convert
x1
bin 0000 1100 0010 0111
0.3
fixdt(1,16,0)
Convert
x2
-0.1
Convert
x3
0.5
Convert
a1
0.15
Convert
a2
0.5
Convert
a3
0.094940185546875
-K Gain 1
Output
0: unsigned
1: signed
Q format (Q0)
5.9814453125015
x1
Subtract
x2
x3
fcn
e-005
error
0.095
a1
Display 1
a2
function y = fcn(x1,x2,x3,a1,a2,a3)
y=a1*x1+a2*x2+a3*x3
a3
Embedded
MATLAB Function
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Convert
x1
bin 0000 1100 0010 0111
0.3
-0.1
Convert
Convert
x2
0.094940185546875
x3
y
0.5
Convert
a1
0.15
Convert
a2
0.5
Convert
a3
-K Gain 1
Output
Sum of Product
5.9814453125015
x1
Subtract
error
x2
x3
fcn
e-005
0.095
a1
Display 1
a2
a3
Embedded
MATLAB Function
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