ANALOG CIRCUITS

1 .

( GATE 2013)

2.

(GATE 2013)

3. A low pass filter with a cutoff frequency as 30 Hz is cascadeded with a high pass filter
With a cutoff frequency of 20Hz. The resultant system of filters coil function as
(GATE-2011)
Sol:- (A)
A pass filter
(B) An all-stop filter
(C)
A band stop filter
(D) A Band pass filter

Ans: Vi

LPF

Vo

HPF

fc=30Hz

Vi

fc = 20hz

HPF

HPF

20Hz

30Hz

Vo

The Cutoff freq of LPF is greater than that of HPF Band pas filter

20

30

Ans: (D)

4. For the circuit shown below, the correct transfer characteristics is

R
R

+12V
+

Vi
R

-12V
R

-12V
+

V0
-12V

(GATE-2011)

(A)

(B)

Vo
+12V

+12V

Vo

-6

-6

+6

+6

Vi

Vi

-12V

-12V

Vo

+12V

(C)

(D)

6V

-6V

Vi

+12V

- 6V

Vi

6V

-12V

-12V

+
Sol:- The first Stage of the given CKt represents subtractor. As Vi
V01 = -Vi Then

-12V
Vi

Vo

+
V=12V

R
VUTP 12
6V
2R

R
VLPT = -6V
R

than its output is

As
10V
+6V

When Vi <6V Vo= +12 V

Vi >6V Vo= -12 V
When Vi >-6V Vo= -12 V
Vi <-6V Vo= +12 V

6V
-10V
+12V

-12V

The transfer characteristic curve is

Vo
12V

Vi

-6V

6V

-12V
Ans: [ C ]
5. The transistor is used in the circuit shown below has a of 30 and ICBO is negligible.
If
the forward voltage drop of diode is 0.7V. Then the current through collector will
be
(GATE-2011)
(A) 168 mA
(B) 108 mA
(C) 20.54 mA
(D) 5.36 mA
15K

1K D

2.2K

VBE=0.7V
VBE(Sat)=0.2V

Vz=5 V
V
-12V
Sol:- Assume that the transistor operated in active region then.
Apply KVL to base emitter loop.

5-103IB-0.7-0.7+12=0
IB=15.6mA
IC=0.468Amp
Apply KVL to Collector emitter loop
0-2.2 103IC VCE+12=0
VCE = 2200IC-12
=1017.6Volts
As O<VCE<VCC Not Satisfying this Condition. Transistor Operating in Saturation
region;
V+ (Sat)=0.2V
Apply KVL, 0-2.2IC-0.2+12=0
IC=5.36mA
Ans : (D)
6. A clipper Circuit is shown below

(GATE-2011)

1k

Vi

D
10V
5V

Assuming forward voltage drops of the diodes to be 0.7V, the input-output transfer
characteristics of the circuit is
15K

1K

2.2K

VBE=0.7V

VBE(Sat)=0.2V
Vz=5
V
-12V
(A)

Vo

(B)

10V
4.3V

4.3V
4.3V
(C)

Vo

Vo

Vi
(D)

Vo

4.3V
10V

10V
5.7V
-0.7V
0.7V 5.7V

-5.7V
10V
-5.7V

Vi

Sol:- During positive half cycle of the i/p

For Vi 5.7V <, D-off and Zener not operated in breakdown region
Therefore Vo=Vi
For Vi>5.7V, D-ON, as it is on, Vo=5.7V
Zener never operated in break down region (Ies it always off state)
During negative half cycle of i/p
D-is reverse baised and Zener diode gets forward aided only Vi 0.7V
Then Vo = 0.7V
SOLUTION:
When Vi > 0.7V, D-off
Zener- off
Then Vo = Vi
(C)

Vo

5.7V
-0.7V
0.7V 5.7V

7. As shown in the figure, a negative feedback system has an amplifier of gain 100 with
10% tolerance in the forward path and an attenuator of value 9/100 in the feedback path.
The overall system gain is approximately.
(GATE-2010)
+
10

1
%
(a)
10010%
(b) 10 2%

(c) 10 5%
(d) 10 10 %
9/100
Solution:

Ans: (a)

dA
10 %, 9 / 100 , A 100
A
dA f
1
dA

Af
1 A A
1

9
1
10%
100
1%

Af

A
1 A

10

8. Given that the op-amp is ideal, the O/P voltage V0 is

(a) 4V
(b) 6V
(c) 7.5 V
(d) 12.12 V
GATE-2010
2R

Solution: Given that Non inv Op-amp circuit

Apply KCL at a
I If
O Va Va V0

V0 3Va 3(2)
R
2R
V0 6V
Ans : (b)

IR
f
I

a
b

V0

2V

Va=Vb=2V

V
V
9. Assuming that the diodes are ideal in the given circuit, the voltage V0 is
(GATE-2010)
(a) 4V
(b) 5V
D2

D1

(c) 7.5V
(d) 12.12V

Solution: The diodes,

D1 F.B(ON ) &
D 2 R.B(off )

10
I
0.5mA
20 10 3
V0 10 10 3 I

10K
V0

I
10V

10K

V0 5V

Ans: (b)
10. The transistor circuit shown uses a Si transistor with VBE 0.7 V, I C I E and a DC
current gain of 100. The value of V0 is
(GATE-2010)
(a) 4.65 V
(b) 5V
(c) 6.3V
(d) 7.23V

Solution: Apply KVL from 10V to Ground through BE terminals

10 10 4 I B VBE 100 I E 0
10 0.7 10 4 I B 100 I C

10 4

IC
100 I C

9 .3
46.5mA
200
V0 100 I C

9.3 100 I C 100 I C I C

V0 4.65Volts

Ans: (a)
11. The nature of feedback in the op-amp circuit shown is
(A) Current-current feedback

(GATE-2009)

(B) Voltage-Voltage feedback

(C) Current- Voltage feedback
(D) Voltage-Current feedback

Sol:- The equivalent circuit of the given amplifier is

R0
+
Vi
+
+ AV
i
Ri

1K

V0

2K

The feedback network samples the o/p voltage and given to the inverterting terminal of
the op-amp is shunt mixing (or) voltage mixing
The feedback is voltage-shunt (or) voltage-voltage
ANS : (b)

12. The following CKT has a voltage source Vs as shown in the graph. The current through
the circuit is also shown
(GATE-2009)

The element connected between a and b could be

Sol:- During the positive cycle, D-gets F.B then V0=Vi

During negative cycle D gets R.B then V0=0
Ans:- (A)
13. The following circuit has R=10k , C=10 F. The input voltage is a sinusoid at 50HZ
with an RMS values of 10V. Under ideal conditions, the current IS from the source is
(A) 10 mA leading by 90o
(GATE-2009)
(B) 20 mA leading by 90o

(C) 20 mA lagging by 90o

(D) 10 mA lagging by 90o

Vb=Va=VS
Sol:- Apply KCL at b
V0 0 Vo V0

0
1/ CS
R
V0.SCR+VbV0=0
Vo
Vb

1 SCR

Apply KCL at a
Va V0 Vb Vb Vb SCR

R
R
V .SCR
IS b
jC Vb jC VS
R

IS =

Is lags behind the applied voltage

|Is| = | C| |Vs|
= 2 f C | Vs |
6

= 2 50 10 10 10

90o

VS

= 10 10
= 10mA lagging by 900
Ans:- (d)

IS

14. An ideal op-amp circuit and its input waveform are shown in the figures. The o/p w/f of
this circuit will be
(GATE-2009)
+6V

Sol:- Given that Vsat=6V, Vsat = 3V

Where V0 = +6V, the potential at non-inverting terminal is,
R2 1
6 2V
VUTP = + Vsat
R1 R 2 3
At instantaneous value of Vi = 2V, V0 = +6V
If VUTP > Vi V0 = +6V
VUTP < Vi V0 = 3V
When V0 = 3V, the potential at noninverting terminal is VLTP = 3(1/3) = 1V
At t < t4, Vo = 3V
i.e., VLTP < Vi Vo = 3V
When VLTP > Vi Vo = +6V
Ans : (d)

15. The equivalent circuits of a diode, during forward and reverse biased conditions are
shown in figure.
(GATE-2008)
10k
0.7V Rf

If such diodes are used in the clipper circuit of figure given above, the output voltage (Vo)
of the circuit will be

Sol:- Diode branch and 10k resistor are connected in parallel and voltage across them must
be same. So that the value of o/p voltage from potential divider network is
10 Vi
Vo = Vi
Vo 5 sin wt

10 10 2
Therefore voltage across diode must always less than O V VD O i.e., D-Reverse biased
for the given i/p. Vo = 5 sinwt
Ans: (a)
16. Two perfectly matched silicon transistors are connected as shown in the figure. Assuming
the of the transistors to be very high and forward voltage drop to be 0.7V, the value of
current I is
(GATE-2008)
(A) 0 mA
D
(B) 3.6 mA
(C) 4.3 mA
(D) 5.7 mA

Sol:- This is a current mirror circuit, since is very large,

IC1 = IC2 = IC = IE1 = IE2 = IE
& IB1 = IB2 = IB

The potential at base of the transistor

VB 0.7+5=0 VB= 4.3V
D is Forward biased
Current passing through diode is
0 VB
4.3mA
I=
1k
Ans: (C)
17. In the voltage doubler circuit shown in figure, the switch S is closed at t =0. Assuming
diodes D1 & D2 to be ideal, load resistance to be infinite and initial capacitor voltages to
be zero, the steady state voltage across capacitors C1 & C2 will be
(GATE-2008)
(A) VC1 = 10V, VC2 = 5V
(B) VC1 = 10V, CC2 = 5V
(C) VC1 = 5V, VC2 = 10V
(D) VC1 = 5V, VC2 = 10V
Sol:- At t=0, S-Closed and During the +ve cycle of i/p,
D1 Forward biased
D2 Reverse biased
C, Charges towards the more value
and C, will charge upto +5V
VC1 5V

C1
+
+

Vi

During the Ve half cycle of i/p voltage

D1off
D2ON
VC1
Apply KOL
+
Vi + VC2 + VC1 =0
VC2 = Vi VC1
+
C
2
Vi
= 5 5

= 10V
C2 will charge upto 10V
Ans: (d)

18. The block diagram of two types of half wave rectifiers are shown in figure. The transfer
characteristics of the rectifiers are also shown within the block
(GATE-2008)

It is desired to mark full wave rectifier using two halfwave rectifiers. The resultant circuit
will be

Sol:- From the transfer characteristic of the rectifier P is

Vo = Vi for Vi >0
V0
Vo = 0
for Vi <0
P
From the transfer characteristic of the rectifier Q is
Vo = 0
for Vi >0
V0
Vo = Vi for Vi <0

The Full Wave rectifier o/p is

So the HWR P must be connected to
inverting and Q must be connected to
non- inverting terminal of the op-amp.

V0

Ans: (b)
19.A general filter circuit is shown in figure

(GATE-2008)

(I) If R1=R2=RA and R3=R4=RB, the circuit acts as a

(a) All pass filter
(b) Band pass
(c) High pass filter
(d) Low pass
(II) The output of the filter in above is given to the circuit shown in figure
The gain VS frequency characteristic of the 0/p (Vo) will be

Sol:- (i)
Vi

R1
II a
1

I Z

R3
R4
I2

Vd0
Vb Va

Assume Z = R2// 1/Sc

R 1 / SC
R2
= 2

R 2 1 / SC 1 SCR 2
RA
V0
Z=
1 SCR A

Apply KCL at b
I1=I2
Vi Vb Vb
Vi

Vb
R3
R4
2

Apply KCL at a, I = If
Vi Va Va Vo

RA
z

z
z
Vi

V0 Va 1
R
R
A

1
1
= Vb 1
Vi

1 SCR A
1 SCR A

2 SCR A

Vi

1 SCR A
1 SCR A
Vi
SCR A
1
1
=
1 SCR A
2

Vi
2

SCR A

1 SCR A

Vi
S
Vo =

2 S 1/ R A C
High pass filter
Ans: (c)

(II) Vo1

Vi
S

As input to LPF
2 S 1 / R A C

Vi
2

then Vo = Vi1 SC
RA 1

2 SC

= Vi 1
2

SCR
A

Vi
S
2

=
2 S 1 / R A C R C S 2

A
R A C

R AC
Vi
S

=
S 2

2 S 1
R A C
R A C

Transfer function of BPF

Ans: (d)

20.The common emitter forward current gain of the transistor shown is F 100 . The
transistor
(GATE-2007)
(a) Saturation region
(b) Cut-off region
(c) Reverse active region
(d) Forward active region
Ans: (d)
Sol: Apply KVL from 10V to Ground through B-E terminals
10 103 I E 0.7 270 103 I B 0
103 1 I B 270 103 I B 9.3
9.3
IB
25.06 A
270 101 103
I C 2.506 mA
I E 2.5318 mA
Apply KVL from 10V to ground through C-E terminals
10 10 3 I E VCE 10 3 I C 0
VCE 10 10 3 I C I E 0

10 103 5.0378 10 3
= 4.962 volts
21.The three terminal linear voltage regulator is connected to a 10 load resistor as shown
dissipated in the transistor?
(GATE-2007)
(a) 0.6 W

(b) 4.2 W (c) 2.4 W

(d) 5.4 W

Sol:
VE 0.7 6.6 0
VE
=0.59 Amp
10
VE 0

VE = 5.9 Volts then I L

Apply KVL, Vin VCE

VCE 10 5.9 4.1 Volt
V V
6 .6 5 .9
I1 x 3 E
0.7 mA
10
10 3
IL IE I1 I E I L I1
= 0.59 0.7 103

Vin

IE

IC
IB
x

E
IL

0.7V
+
I1 1K
6.6V

10

= 0.5893 Amp
Assume that I E Ic 0.5893
Therefore the power dissipated in the transistor is
PD VCE IC
= 4.1 0.5893
= 2.416 W
Ans: (c)
22. The circuit shown in figure is

(GATE-2007)

rV
R 1 // R 2
r // R 2
(b) A voltage source with voltage
V
R1
r // R 2 V
(c) A current source with current
.
R1 R 2 r
R2
V
(d) A current source with current
.
R1 R 2 r

(a) A voltage source with voltage

Sol:
Vd 0
V V 0
V V
Assume that V V1

R2
Therefore V V1
V1 V
R1 R 2
V
R2
V
i 1
.
r
R1 R 2 r
Current entering into the op-amp is zero
V R2

I L i
r R 1 R 2
This is voltage to current converter.
Ans: (d)

R
V

V
1

R
2

Then

+
I

V0 L r
1
i

23. The input signal Vin shown in the figure is a 1 kHz square wave voltage that alternates
between +7V and -7V with a 50% duty cycle. Both transistors have the same current
gain, which is large. The circuit delivers power to the load resistor R L . What is the
efficiency of this circuit for the given input? Choose the closest answer. (GATE-2007)
(a) 46%
(b) 55%
(c) 63%
(d) 92%

Sol: The given circuit is class-B amplifier whose efficiency,

Vp

4 Vcc

Vp Peak voltage

7

4 10
Vcc Supply voltage
= 54.98%
55%

Ans: (b)
24. The switch S is the circuit of the figure is initially closed. It is opened at time t = 0. You
may neglect the zener diode forward voltage drops. What is the behaviour of VOUT for
t>0
(GATE-2007)

(a) It makes a transition from 5V to +5V at t 12.98 sec .

(b) It makes a transition from 5V to +5V at t 2.57 sec .
(c) It makes a transition from +5V to -5V at t =12.98 sec
(d) It makes a transition from +5V to 5V at t=2.57 sec
Sol: Initially VC 0
When the switch S is opened, the capacitor charges towards the max value of 20V and
(1)
is given by Vc 201 e t
This is at inv. terminal of the op-amp. But the voltage at Non-inv. Terminal is
100 10
Vx V0
V0
110 11
When o/p changes from -5V to 5V, the capacitor changes and

+10V

20 1 e

10
5
11

+5
4.5V

t
5
5 17
e 1

22
22 22
t
22
RC
e
17
t
22
ln
103 0.01 10 6

17
22
= 10 sec
t ln
17
5
10 0.2578 29
=2.578 sec
Ans: (B)

1 e

4.5V
5
10V

25. IC 555 in the adjacent figure is configured as an Astable multivibrator. It is enabled to

oscillator at t = 0 by applying a high input to pin 4. The pin description is 1and 8
supply; 2-vigger; 4-reset; 6-threshold; 7-discharge. The wave form appearing across the
capacitor starting from t = 0 observed on the storage CRO is
(GATE-2007)
RA

RB

Sol: Let C is initially relaxed then,

When the C charges, D-ON and charging time (ON) is
10 k C
TH 0.69 R A C
R A R B 10 k
C discharges through R B & C & D R.B
TL 0.69 R BC
T TH TL 0.69 R A R B C
D = 50%
charging Time = Discharging time
Ans: (b)

26. What are the states of the three ideal diodes of the circuit shown in figure? (GATE-2006)
(a) D1 - ON, D2 - OFF, D 3 - OFF
(b) D1 - OFF, D2 - ON, D 3 - OFF
(c) D1 - ON,

D2 - OFF D 3 - ON

(d) D1 - OFF, D2 - ON, D 3 - ON

1K

Sol: From the given Ckt, we can analyse that the diodes
1K
D - ON
1

D2 - ON &

D2
10V

1k

5A

D1

D 3 - OFF then

But no current flows through D2 because current always select the low resistance path
(through short ckt path D1 ) Therefore D2 also OFF
Ans: (a)
27. For given sinusoidal input voltage, the voltage waveform at point P of the clamper circuit
shown in figure will be

(GATE-2006)

-0.7V

Sol:

Vi

RL

During the ve half cycle of input, Diode D will be forward biased and its equivalent
circuit is
C
Vi

P
0.7V

V0

The op-amp has high open loop gain so it goes into the saturation and Vp 0.7 V
During the +ve cycle of input , D-R.B and no Feedback to the op-amp then VP= 12V

Vi

+12V
Vp

+
12V

RL

Ans : (d)

28. Assuming the diodes D1 and D2 of the circuit shown in the figure to be ideal ones, the
transfer characteristics of the circuit coil be

(GATE-2006)

Sol: When Vi =0, D1 -OFF and D2 also OFF

+
Vi

D2 - Reverse biased

D2

10V

5V

RL=

+
2

Vi

10V

V0

Current passing through 2 resistor is 0.

V0 10 V

For Vi 10 V,

V0 10 Volts

To become D1 -ON, Vi 10 V D1 - ON and D2 -OFF

V0
+

+
2

Vi

10V

V0

10V

Vi

10V
Ans: (a)

29. Consider the circuit shown in figure. If the of the transistor is 30 and I CBO is 20 nA and
the input voltage is 5V then the transistor would be operating in
(GATE-2006)
(a) Saturation region
(b) Active region
(a) Break down region
(a) Cut-off region

Sol: Assume that the transistor in the active region. To calculate base current
12V

15K

2.2 K

x
+ 0.7

Vth

Vth
5V

Rth

100K
12V

 5 12
x
3
115 10
R th

15 100
115

R th 13.043 k

Vth 100 10 3 x 12 0

17
Vth 12 100

115

= 2.783 volts
IB

Vth 0.7
0.1597 mA
R th

Ic I B = 4.79 mA

Then apply KVL in C-E loop

12-2.2(4.79)- VCE =0
VCE 1.46 Volts J C R.B

So 0.2v VCE 12 v
J E F.B

Transistor operated in Active region

30. A relaxation oscillator is made using op-amp as shown in figure. The supply Voltage of
the op-amp are 12 the voltage waveform at point p will be

(GATE-2006)

Sol: Given circuit is Astable multivibrator whose output is square wave and waveform
across capacitor is exponential waveform. There fore potential across C and P are
same.
When o/p voltage is + 12V, the C changes towards maximum value through R 1 . And
max voltage is given by
10
Vp V0 D1 ON
20

= + 6v
When o/p voltage is -12V, C discharges towards -12V through R 2 . To calculate this,
consider the circuit at non inverting terminal. At this
10
D2 ON then VP V0 10V
12

12V
+6V
10V
12V

Ans: (c)

31. Assume that D1 and D2 in figure are ideal diodes the value of current I s is (GATE-2005)
(a) 0 mA

(b) 0.5 mA

1mA

(c) 1 mA

(d) 2 mA

2K
2
2V

2K

Solution: The current always selects the low resistance path. D1 -ON and D2 -OFF.
The I directed from N type to P-type ( D2 -R.B) As D2 -R.B replaced by O.C

I=0

Ans: (A)

32. Assume that N-channel MOSFET shown in figure is ideal and its threshold voltage is 1V,
the voltage Vab between nodes a and bis

(GATE-2005)
a

Vab

b
(a) 5V

(b) 2V

(c) 1V

(d) 0V

VG 2V
Solution: VGS 2V

VS 0V
Vth 1V
V DS (sat ) V GS V th 1V

Due to 10V source VDS VDS (sat ) N-channel MOSFET operated in saturation, high
current flows through drain and source so that it acts as a SHORT CIRCUIT,
Vab = 0V

Ans: (d)

33. The common Emitter amplifier shown in the figure is biased using a 1mA ideal current
source. The approximate base current value is
(GATE-2005)
(a) 0 A
(b) 10 A
(c) 100 A
(d) 1000 A
Solution: Given that IE = 1 mA
IC

I E 0.99 mA
1

IB

IC
9.909 A

I B 10 A

Ans: (b)

34. Consider the inverting amplifier using an ideal operational amplifier shown in figure.
The designer wishes to realize the i/p resistance seen by the small signal source to be as
large as possible, while keeping the voltage gain between -10 and -25. The upper limit
on R F is 1M . The Value of R 1 should be
(GATE-2005)
(a) Infinity
(b) 1M
(c) 100 k
(d) 40 k

Solution: Gain of the inverting Amp is A

RF
given that R F = 1M , A -10 & -25
R1

10 6
105 =100 k when A=-10
then R 1
10
10 6
R1
40 k when A=-25
25
The designer wishes the input resistance should be as large as possible
R1 =100 k

Ans: (c)
35. The typical frequency response of a two stage direct coupled voltage amplifier is as
shown in figure

(GATE-2005)

Sol: The direct coupled (or) DC coupled amplifier provides a gain at low frequency and for a
two-stage direct coupled voltage amplifier provides a gain at zero frequency
Ans: (b)
36. In the given figure, if the input is a sinusoidal signal, the output-will appear as shown
(GATE-2005)

Sol: The op-amp is in the open-circuited mode i.e. no feedback is given. The op-amp has
high open loop gain and is forced to operate in saturation region, for the given input
waveform of the op-amp
V0 A OL O Vi

During the positive half cycle of input Vi 0 the op-amp saturated to V0 V

During the negative half cycle of i/p Vi 0 the op-amp saturated to V0 V
Ans: (c)

37. Assume that the threshold voltage of the N-channel MOSFET shown in figure is 0.75 V
the output characteristics of the MOSFET are also shown

(GATE-2005)

VGS=4V
VGS=3V
VGS=2V
VGS=1V

(i) The Transconductance of the MOSFET is

(a) 0.75 mS

(b) 1 mS

(c) 2 mS

(d) 10 mS

ID
Sol: g m

VGS VDS cons tan t

2 1 10 3
2 1

1mS

g m 1 mS

(ii) The voltage gain of the amplifier is

(a) +5

(b) -7.5

(c) +10

(d) -10

Sol: The small signal model of the given amp is

G
Vi

Id

+
gmVgs

Vgs

rd

S
Current through 10k I L I d g m Vgs

= 10 4 I d
104 g mVgs
V0 10 4 10 3 Vi

V0
A V 10
Vi

Ans: (d)

10K
IL

V0 10 10 3 I L

+
V0

38. The current through the zener diode in the given circuit is
2.2 K
(a) 33 mA

(GATE-2004)
+

(b) 3.3 mA

3.5V

RL

10V

(c) 2 mA

(d) 0 mA

VZ = 3.3V
RZ = 100

Solution: Given that V0 3.5V

Vz 3.3V

Then zener offers R z 0.1 k of dynamic resistance.

So V z I z R z 3.5
3.5 3.3
2 mA
I z
Rz

Ans: (c)
39. Two perfectly matched Si transistors are connected as shown in figure. The value of the
current I is
(GATE-2004)
3V
(a) 0 mA

1 k

(b) 4.3 mA
=1000

=1000

(c) 2.3 mA
(d) 7.3 mA

5V

Fig.

Solution:
This is a current mirror circuit I C I C & I B I B I B
1

I R I C 2I B

2I C

I R I C 1 2

= IC

Apply KVL from ground to -5V

IC1

IR
4.3 x 10 3

4.2914 mA
1 2
1.002

I C I 4.3 mA

Ans : (c)

I
I

0 10 3 I R 0.7 5 0
I R 4.3 mA

IC

3V

IR
1 k

IB1
Fig.

IB2
5V

=1000

40. The feedback used in the circuit shown figure can be described as

(GATE-2004)
VCC

(a) Shunt Series feedback

RF

(b) Shunt-Shunt feedback

RC C =
V0

(c) Series-Shunt feedback

RL
(d) Series-Series feedback

RS

RB

RC

Ce

Fig.
Solution: Ans : (b)
As one terminal of feedback element connected to o/p voltage, so it is voltage
sampling (or) shunt sampling and another terminal of feedback element connect
connected to base of the transistor, it is shunt mixing hence it is Shunt-Shunt feedback
amplifier
41. A bipolar junction transistor (BJT) is used as a power control switch by biasing it in the
cutoff region (OFF) or in the saturation region (ONstate). In the ON state, for the BJT
(a) both Base-Emitter and Base-collector junction are reverse biased (GATE-2004)
(b) The B-E junction is R.B and Base-collector junction F.B
(c) The B-E junction is F.B and Base-collector junction R.B
(d) both B-E & B-C junctions are F.B
Solution:
JE

JC

R.B

R.B cutoff (OFF)

R.B

F.B Inverse Active Attenuator

F.B

R.B Active Amplifier

F.B

F.B Saturation ON

Ans : (d)
42. Assuming that the diodes are ideal in figure the current in the diode D1 is (GATE-2004)
1K

(a) 8 mA
(b) 5 mA

D1

5V

D2
8V

(c) 0 mA
(d) 3 mA

1K

Fig.

Sol: From the Ckt D2 must be in Forward bias where D1 -first replace by O.C
V 5 V 8
Apply Nodal analysis at 1 3 1 3 0
1K V1 1K
10
10
V1 5 V1 8 0
2V1 3
5V
V1 1.5 V
D1 is Reverse biased
Fig.

8V

I D1 0

Ans: (c)
43. The transconductance g m of the transistor shown in figure is 10 mS. The value of input
VCC (GATE-2004)

resistance R in is
(a) 10 k

10K

(b) 8.3 k

V0
C=
= 50
1K
C=

VS C =

(c) 5 k
(d) 2.5 k

Sol:

RC

10K

Given that gm =10 mS

gm r 50 r

50
5 k
10 x 10 3

RB

VS

gmV

R in R B // 2.5 k

Rin

Ans: (d)

RB = R1//R2 = 5K

44. The input resistance R IN Vx I x of the circuit in the figure is

10K

(a) 100 k
(b) 100 k

(GATE-2004)

100K

(c) 1 M
(d) 1 M

V0

V0

+
Vx
Ix

1M

Fig.

RC

Solution: The gain of the op-amp Ckt is

V0 100
1

Vx
10

V0
11
Vx
Vx

V0
11

Apply KCL at Non inverting terminal,

Ix

Vx V0 Vx 11Vx

10 6
10 6

Ix

Vx x 10
V
x 100 k
6
10
Ix

R in 100 k
Ans: (b)

45. In the Schmitt trigger circuit shown in figure, if VCE (sat) = 0.1V, the output logic low
level (VOL) is
(GATE-2004)
(a) 1.25V
(b) 1.35 V
V0

(c) 2.5V

Vi=0

Q1

Q2

(d) 5.0 V
Solution: When Vi 0,
Q1 (cutoff) off and Q 2 ON (sat )
VCE (sat) = 0.1V
Then Apply KVL from 5V to Ground through transistor Q 2 C-E terminals
5 I C x 200 V0 and
5 I C x 200 VCE (sat ) 1.25 x10 3 x 10 3 0

V0 0.1 1.25 0
V0 =1.35 volts

Ans: (b)

46. In the active filter circuit shown in figure if Q =1, a pair of poles will be realized with
equal to
(GATE-2004)
(a) 10000 rad/sec
(b) 100 rad/sec
(c) 10 rad/sec
(d) 1 rad/sec

R2

Solution: The transfer function of the bridged T-network is

1
1 1
1

S2 S

C1 C 2 R 1 C1C 2 R 1R 2
T(S) =
1
1
1
1

S2 S

C1R 1 C1R 2 C 2 R 1 C1C 2 R 1R 2

The pole polynomial of the active filter circuit will be equal to the numerator
polynomial of the bridged T-network
S2 S.

1
0
1 1
1
.
02 S2 S
Q
C1 C2 R1 C1C2 R 2 R1
0

Then

1
and
C1C 2 R 1R 2

CC R R
Q 1 2 1 2
R1

1
1

C1 C 2

Given that Q 1, C1 C 2 1 nF and R 1 = 200 k

10 9 x 10 9 x 200 x 103 R 2 1
1
1

9 9
3
Q
200 x 10
10
10
1
1
Q

R 2 x 2 x10 13
2 x109
5
2 x 10

R 2 x 4.472 x103 1

R 2 223 .606

R 2 50 k
0

1
1

9
9
C1C 2 R1R 2
10 x 10 x 200 x 103 x 50 x 103

0 10,000 rad / sec

Ans: (a)
47. In the circuit of figure shown, assume that the transistor has h fe = 99 and VBE 0.7V .
The value of collector current I C of the transistor is approximately (GATE-2003)
3.3 K

(a) [3.3/3.3] mA
(b) [3.3/(3.3+0.33)] mA

33K

IC

(c) [3.3/33] mA
(d) [3.3/(33+33)] mA

12V
4V

3.3 K
Fig.

Solution:
12V
3.3 K

Apply KVL to Base-emitter loop

4 33x10 3 I B 0.7 3.3x10 3 I E 0

33K
IB

3.3 33 x103 I B 3.3 x 103 (1 )I B

IB

Ic

IC
3.3 K

4V

3.3
3 .3
IC IB
x 99
3
33 330 x 10
33 330 x 103

Fig.

3 .3
mA
33 330

99
3 .3
mA
3.33 0.33

Ans: B
R
48. For the circuit shown in figure with an ideal op-amp,

R
the maximum phase shift of the output Vo with reference V
tointhe input vin is
+
(GATE-2003)

(a) 0 0

(b) 90 0

Fig.

(c) 90 0
(d) 180 0
Sol: Apply KCL at b

Vi Vb
Vb .SC
R

Vi Vb Vb .SCR

Vi
Vb
1 SCR

Apply KCL at a, I I f

R
Vin

I
I1

If

a
b

V0

+
C

I2

Vi Va Va V0

V0 2Va Vi
R
R

= 2Vb Vi
1 SCR
= Vi
1 SCR
V0 1 jCR

Vi 1 jCR

Fig.

V0

 V0
1
2 tan CR
V
i

For 90 0 90 0 ,

180 0

Ans: (D)
49. For the n-channel enhancement MOSFET shown in figure, the threshold voltage
Vth = 2V. The drain current I D of the MOSFET is 4 mA when the drain resistance is
1k . If the value of R D is increased to 4k , the drain current I D will become
(a) 2.8 mA
(GATE-2003)
10V
RD
ID
(b) 2.0 mA
(c) 1.4 mA
(d) 1.0 mA
Sol: Given that Vth 2V ,
VD VG , VS 0

Fig.

10V
RD
ID
VD

VDS VGS

We know I D 4 mA, R D 1 k
10 I D R D VD 0

Fig.

VD 10 4 6V
VD 6 V VGS

then I D k VGS VGS( th )

4

= k x 6 2

1
mA v 2
4

But when R D changed to 4 k then

VGS VDS 10 4 I D

Then

ID kVGS VGS t n

ID

1
10 I D 22
4
1
8 4I D 2
4

I D 42 I D

ID m mA

I D 4 I 2D 4 4I D

I 2D 4.25 I D 4 0

ID

4.25

4.25 16
2

4.25 1.436
2

ID

= 2.843 mA (or) 1.407 mA

I D 2.84 (or ) 1.407 mA

For N-channel E-MOSFET VGS Vth

VGS 10 4( 2.84)

& VGS 10 4(1.407 )

= -1.372 volts

= 4.372 volts

I D =1.407 mA

Ans: (C)

1K

50. Assuming the operational amplifier to be ideal the gain

V0 Vi for the circuit shown in
figure

1K

1K
(GATE-2003)

1K
Vi

(a) -1

V0

(b) 20
(c) -100

Fig.

(d) -120
Solution:
Apply KVL at a
I I1

Vi
Vx

3
10
10 x 103

Vx 10Vi

1K x 1K
I3
I1
1K
I2

Apply KVL at b
I1 I 2 I3

Vx
V
V V0
x3 x
3
10 x 10
10 10 x 103
Vx 10 Vx Vx V0
V0 12 Vx 120 Vi

Gain

Ans: (d)

V0
120
Vi

1K
Vi

a
I
b

V0

+
Fig.

51. A voltage signal 10 sin t is applied to the circuit with ideal diodes as shown in figure.
The max and minimum values of the output waveform of the circuit are respectively
(GATE-2003)
10 K
(a) +10V and 10V
+
D2
D1
(b) +4V and 4V
V0
Vi
4V
4V
10 K
(c) +7V and 4V

(d) +4V and 7V

Fig.

Solution: For positive half cycle

(i) (When Vi 4V ) D2 ON, D1 = off then

10 K
+

(ii) When Vi 4V , D1 & D2 -OFF V0 Vi

(iii) For negative half cycle, D1 -ON, & D2 -OFF

Vi

4V
10 K

Vi - 10I+4-10I = 0

V0=4V

V 4
I= i
mA
20

Fig.

When Vi = -10V (max.value)

10 K

6
I=
mA
20

V0 4 10 I 0

4V

Vi

V0 10I 4
6
= 10
4
20

V0

4V
10 K

Fig.

= -3-4 V0 7 V
Ans: (d)
52. The circuit of fig shows a 555 timer IC connected as an Astable multivibrator. The value
of capacitor C is 10 nF. The value of the resistors R A and R B for a frequency of
10 kHz and a duty cycle of 0.75 for the output waveform are
(GATE-2003)
Vvcc
(a) R A = 3.62 k , R B = 3.62 k
(b) R A = 3.62k , R B = 7.25 k

RA
Th

(c) R A = 7.25 k , R B = 3.62 k

RB

(d) R A =7.25 k , R B = 7.25 k

Tr

Fig.

Vout
555

Solution:
Given that f = 10 kHz, D = 0.75, C = 10 nF
The frequency of Oscillations from 555 Astable timer is f
R A 2R B

1
0.69(R A 2R B )C

1
1

4
0.69 fC 0.69 x 10 x 10 x 10 9

R A +2 R B =14.492 k

R RB
0.75
and D A
R A 2R B

R A + R B = 0.75 ( R A +2 R B )

= 10.869 k
R B = ( R A +2 R B ) ( R A + R B )

= 14.492-10869
= 3.623 k
R A = 10.869-3.623 = 7.246 k
Ans: (c)

53. In the circuit shown, the current gain '' of the ideal transistor is 10. The operating point
of the transistor VCE , I C is
(a) (40V, 4A)

(b) (0 V, 4A)

(c) (40V, 5A)

(d) (15V, 4A)

Solution:

10 (GATE-2003)
0.5A

IC
40V

15V

Given that I B =0.5 amp

Fig.

Assume transistor in Active, I C I B =5 Amp

then VCE =40-10 x 5 = -10v
As VCE is negative, Q operated is saturation
VCE =0 V then 40-10 Ic VCE 0
I c =4 amp

Ans: (b)
54. The cutin voltage of both zener diode Dz and D shown in Figure is 0.7 V, while
breakdown voltage of the zener is 3.3 V and reverse break down of D is 50 V. The other
parameters can be assumed to be the same as those of an ideal diode. The values of the
peak output voltage (V0) are
(GATE-2002)

(a) 3.3 V in the positive half cycle and 1.4 V in the negative half cycle.
(b) 4 V in the positive half cycle and 5 V in the negative half cycle.
(c) 3.3 V in the both positive and negative half cycle.
(d) 4 V in the both positive and negative half cycle.
1k

I1k
V0

10sin t
= 314rad/sec

Sol: During the positive half cycle, when Vi > 4 V zener replaced by Vz (ON) & D replaced
by 0.7 V
1K
+
33V

Vi

V0 = 4V
1K

0.7

During the negative half cycle

Zener diode becomes forward biased and PN junction diode becomes reverse biased,
then
1K
V
+
V0 i
2
5 Sin t
Vi
V0
1K
Vomax = 5V

Ans: (B)
55. The forward resistance of the diode shown in figure is 5 and the remaining parameters
are same as those of ideal diode. The DC component of the source current is
(GATE-2002)
Vm
Vm
Vm
2 Vm
(a)
(b)
(c)
(d)
50
50
100 2
50 2
D
Vi
Vi Vm Sin t
314 rad / sec
Sol: During positive half cycle
D F.B replaced by 5
5
Vi

45

Vi

45
I

Vi
50
V
i( t ) m sin t
50

V V
DC component is Idc = m m
50 50

During negative half cycle, D R.B replaced by O.C
I=0
Ans: (a)
i( t )

56. The output voltage (V0) of the Schmitt trigger shown in figure swings between + 15V and
15V. Assume that the operational amplifier is ideal. The output will change from +15V
to 15V when the instantaneous value of the input sine wave is
(GATE-2002)
(a) 5 V in the positive slope only

Vi
+

100

(b) 5 V in the negative slope only

(c) 5 V in the positive and negative slopes

10k

Vi= 10sint

3k

(d) 3 V in the positive and negative slopes

2V

Sol: When V0 = + 15 V,
The potential at non inverting terminal is UTP,
R2

VUTP = Vref (V0 Vref )

R

R
2
1
3
VUTP = 2 15 2
When VUTP > Vi V0 = + 15 V
13
= 5V.
VUTP < Vi V0 = 15 V
When V0 = 15 V, the potential at non inverting terminal is LTP
3
10 V
VLTP = Vref + ( V0 Vref)
5V
13
1.923V
t
3
10V
= 2 17
13
+15V
VLTP = 1.923 V
The output will change from + 15 V to 15 OV when the instantaneous value of the
15V
input sine wave is 5 V in the positive slope only.
Ans: (a)

57. In the single phase diode bridge rectifier shown in figure, the load resistor is R = 50 .
The source voltage is V = 200 sin t, where = 2 x 50 rad/sec. The power dissipated in
the load resistor R is
(GATE-2002)
3200 W
(a)

(b) 400 W

(c)

400 W

(d) 800 W

A
D4

D1

Sol: The given circuit can be redrawn as

During the positive half cycle of the i/p then
D1 & D3 ON, S.C
D2 & D4 Off O.C

D2

D3
B

i( t )

v( t ) 200 sin t

R
50
= 4 sin t. Amp

R
V(t)

i(t)

During the negative half cycle of the input, D1 & D3 off O.C
D2 & D4 ON S.C
V(t)

v( t )
4 sin t
R
Full Wave Rectifier power dissipated in the load resistor R is
v( t ) i ( t )
P
x
2
2
200
4

x
2
2
i(t)
P = 400 W
Ans: (b)
i( t )

58. For the circuit shown in Figure, IE = 1 mA, = 99 and VBE = 0.7 V determine
15V

(a) Current through R1 and RC

RF

(b) The output voltage V0

V0
IC

(c) The value of RF

Sol: Given that IE = 1 mA

I 0.99 mA
I C
1
IB

(GATE-2002)
RC=1K

IB

17K

R1

IC
10 A

1K

15V
RF

Potential at Base is
VB VBE IE x 103 = 0
VB = 0.7 + I = 1.7 Volts

1K(IC+I)
V0
IC

B
VB
I1
R1
17K

IB
IE
1K IE

VB
100 A
17 K
Then I = I1 + IB
= 110 A

Then I1 =

(a) Current passing then through R1 is 100 A

Current passing through RC is IC + I
= 0.99 mA + 110 A
= 1.1 mA
3
(b) The O/P voltage V0 = 15 10 (IC + I)
= 15 103(1.1 x 103)
= 13.9 Volts
V VB 13.9 1.7
110 .91 K
(c) R F 0

6
I

110 x 10
Vy
59. Determine the transfer function for the RC network shown in figure (1). The
Vx
network is used as a feedback ckt in an oscillator ckt shown in figure (2) to generate
sinusoidal oscillations. Assuming that the operational amplifier is ideal, determine the value
of RF for generating these oscillations. Also determine the oscillation frequency if R = 10 K
and C = 100 PF
(GATE-2002)
C

R
C

VX

Figure 1
Sol:
VX

R VY
1/SC
R

I1

C
C I2
1/SC

R V0

Figure 2

Apply KVL to loop (1)

1
1

Vx(S) = I1(S) R
I2(S).
-------- (1)

SC
SC

Apply KVL to loop (2)

2
1

I1 (S)
0
I 2 (S) R
SC
SC

1
2 SCR
I1 (S) .
I 2 (S)
SC
SC
I1(S) = I2(S) [2 + SCR]
--------------------- (2)

Substitute equation (2) in (1) then

1
1 SCR
Vx (S) I 2 (S) (2 SCR )
I 2 (S).
SC
SC

I 2 (S)
(1 SCR ) (2 SCR ) 1
SC
Vy (S)

(2 3 SCR S2 C 2 R 2 1
SCR
VY (S)
SCR
2 2 2
Vx (s)
S C R 3 SCR 1

Vy (S)
Vx (S)

But Vy(S) = I2(S).R

I2(S) =

VY (S)
R

1
1

SCR 3 SCR

If this is connected as feedback in the op amp ckt then

V
Then feedback factor f
V0
1

1
SCR 3
SCR
1

3 j CR

CR

V0
Vf

To get the undamped oscillations the imaginary part of the feedback factor is zero.
1
CR
0
CR
1
1
2 2 2
C R
RC
The frequency of oscillations is given by
1
f0
2 RC
1
=
3
2 x 10 x 10 x 100 x 10 12
= 159.12 KHz
1
3
To get sustained oscillation | AB| =1
1
A= 3

R
A 1 F3 3
10

Then

RF
2
10 3
RF = 2 K

60. The circuit shown in figure uses an ideal op-amp working with +5V and 5V power
supplies. The output voltage Vo is equal to
(GATE-2000)
1K

(a) +5V
(b) 5V
(c) +1V
(d) 1V

+5
V

V0

1mA

Va=0

5
V

Ans : (d)

Sol:
Apply KCL at inverting terminal
V V
10 3 a 3 0 Va Vo 1
10
V0 1 Volt
61. The type of the power amplifier which exhibits crossover distortion in its output is
(GATE-2000)
(a) class A
(b) Class B
(c) Class AB
(d) Class C
Sol:
Ans : (b)
100

62. The feedback factor for the circuit shown in fig. is

9
9
(a)
(b)
100
10
(c)

1
9

(d)

(GATE-2000)
V0

VS

1
10

1K

90
10

Ans : (d)

Sol :
The feed back network is
Vf I 10
V
0 10
100
Vf
1

V0
10

Vf
90
10

V0

V
VT

63. A diode whose terminal characteristics are related as i D IS e , where IS is the reverse
saturation current and VT is thermal voltage (=25 mV) is biased at iD= 2 mA. Its dynamic
resistance is _______
(GATE-2000)
(a) 25
(b) 12.5
(c) 50
(d) 100
Ans : (b)
Sol :
Change in voltage across diode
dv

Change in Current through diode

dI D
Diff. eq w.r.t V
R ac

DI D
1
I
IS .e VT .
D
dV
VT
VT
R ac

VT
25 10 3

12.5
ID
2 10 3

64. In the circuit of figure, the value of the base current IB will be
(a) 0 A

5V (GATE-2000)
5K

(b) 18.2 A
(c) 26.7 A

=80

IB 0.7V

(d) 40 A

6.3K
RE

Ans : (b)

10V
Sol : Apply KVL in the base loop
0 0.7 I E R E 10 0
9 .3
I E R E 9.3 I E
6.3 10 3
I E 1.4762 mA
I
I B E 18.22 A
1

65. A current amplifier has an input resistance of 10, an o/p resistance of 10K and a
Current gain of 1000. It is feed by a current source having a source resistance of 10K
and its output connected to a 10 load resistance. Find the voltage gain and the power
gain
(GATE-2000)
Sol:
+
IS

RS

Ri

Vi

Ii
AI Ii

R0=10K

RL

V0

10

IL

 R0

I L A I I i
R0 RL
10 4

1000 Ii 4
10 10
I L 999 I i Rs

R S 10 K

R L 10
A I 1000

Voltage gain

V0
VS

Ri

Vs
IL
I
I
L i
IS
I i IS

IL R L
Ii (R S R i )

A IS

999 10
(10 4 10)

RS

Ii IS
RS Ri
Ii R S

IS R S R i

= 0.998
Power gain = Current gain Voltage gain

Ii

RS

A IS A I
RS Ri

= 999 0.998
= 997
10000
10 3

10010
= 999

66. The mobility of an electron in a conductor expressed in terms of

(a) Cm 2 / V sec
(b) Cm / V sec
2
(c) Cm / V
(d) Cm 2 / sec

(GATE-1999)

Ans : (a)
67. The enhancement type n-channel MOSFET is represented by the symbol
(GATE-1999)
(a)

(b)

(c)

(d)

Ans : (a)
68. As temperature is increased, the voltage across a diode carrying a constant current.
(a) Increases
(b) Decreases
(GATE-1999)
(c) Remains Constant
(d) May increase or decrease depending upon the doping levels in the junction
Ans : (b)
Sol : When temperature increases the current passing through the diode increases. But to
maintain the carrying current as constant, voltage across the diode must be decreased.

69. One of the applications of current mirror is

(GATE-1998)

(a) Output current limiting

(b) Obtaining a very high current gain
(c) Current feedback
(d) Temperature Stabilized biasing
Ans : (d)
70. Match the following
Circuit

(GATE-1998)
Functions

VCC

(A)

Vi

Vo

(P) High-pass filter

(B)

Vi

(Q) Amplifier
Vo

(C)

Vi

Vo

(R) Comparator

(S) Low-Pass Filter

Ans : (A) Comparator
(B) LPF
(C) HPF (2nd order)
(A) (R ), (B) (S), (C) (P)

71. A NPN Si transistor is meant for low-current audio amplification. Match its following
characteristics against their values.
(GATE-1998)
Characteristics
(A). VEB max
(B) VCB max
(C) VCE max

Sol :

Values
(P) 0.7 V
(Q) 0.2 V
(R) 6 V
(S) 50 V

AP
BR
CQ

72. A major advantage of active filters is that they can be realized without using
(GATE-1997)
(a) OP-amps
(b) Inductors
(c) Resistors
(d) Capacitors
Ans : (b)

73. The circuit shown in figure acts as a _________ and for given inputs, its output voltage is
___________ V
(GATE-1997)
1 K
1K
1V

2V

Sol: The given circuit is

Since Vd 0
Vb Va 0

1K

1 K
1K

I3

1V
I1

1K
2V
I2

a
b

 Vb Va 0
Apply KCL at a
1 Va 2 Va
V V

a 3 0
3
3
10
10
10
V0 3Va 3
Va 0

V0 3V

The O/P voltage is sum of inputs and phase shift between them is 180o.
The ckt is inverting summing amplifier.
74. The depletion region (or) space charge region (or) transition region in a semiconductor
p n junction diode has
(GATE-1996)
(a) Electrons and holes

(b) positive ions and electrons

(c) positive and negative ions

(d) negative ions and holes

(d) no ions, electrons or holes

Sol: Due to concentration gradient exist either P or N side, diffusion of majority carriers takes
place due to this recombination of e - hole takes place on both sides of the junction.
Therefore depletion region formed. In their region there is no exist of mobility of charge
carriers ( e & hole) and exist only immobile ions (positive & Negative)
Ans: (c)
75. A non inverting op amp amplifier is shown in figure. The o/p voltage is (GATE-1996)
3
(a)
sin 100t
2
2R
R
(b) 3 sin 100t

(c) 2 sin 100t

R
(d) None of these
+
2
2+sin100t

Sol:

Apply KCL at b I1 + I2 = 0
2 Vb 2 sin 100 t Vb

0
R
R

2R

sin 100t = 2 Vb
Vb =

1
sin 100t
2

a
R I

Apply KCL at a
2 + sin 100t R

I = If
0 Va Va V0

V0 3 Va
R
2R

V0 =
Ans: (a)

If

3
sin 100t
2

I1 b
I2

V0

76. In the transistor amplifier shown in figure, the ratio of small signal voltage gain when the
emitter resistor is bypassed by the capacitor Ce to when it is not bypassed. (Assuming of
simplified approximate h parameter model for transistor) is
(GATE-1996)
VCC
(a) 1
RC
R
1
Vo
(b) hfe
C1
Vi
Cc
(1 h fe ) Re
(c)
h ie
R2
Re
(1 h fe ) Re
Ce
(d) 1
h ie
Ans: The small signal model with Re & Ce

h fe R C

h ie

hie
Vi

Ratio =

hfe R C
h ie (1 hfe) R e

AV
A 1V

IC

IL
Vo

RC

Zi
hie

V
I .R
AV 0 C C
Vi
Vi

But Vi = [h ie + (1 + hfe) Re] Ib

hfe Ib

Ib

RB

The small signal model with Re only

AV =

V I R
Voltage gain = 0 L C
Vi I b Z i

RB

Vi

Ib

hfeIb
E

IL

IC

RC

1+ (hfe ) Ib

hfe R C

h ie
h ie (1 h fe) R e
(1 hfe) R e

1
hfe R C
h ie
h ie
h ie (1 hfe) R e

Ans: (d)
77. Let the magnitude of the gain in the inverting op amp amplifier circuit shown be x with
switch S1 open. When the switch is closed, the magnitude of gain becomes.
(GATE-1996)
(a) x/2
S1
(b) x
(c) 2 x
R
R
(d) 2 x
R
Vi

V
o

Vo

Sol: (i) when switch is open gain =

V0
x 2
Vi

2R
R

Vi

Vo

(ii) When switch is closed

V0
1
Vi

1
A = (2)
2

Vi

Vo

x
2

Ans: (a)
78. The common mode voltage of a unity gain (voltage follower) op amp buffer in terms of
its output voltage V0 is ___________
(GATE-1995)
Sol:

V
a

+
b
For a voltage follower, Va = Vb (or) V0 = Vi
Vi

i/p
1
The common mode voltage = (Va+ Vb)
2
1
= (2 V0)
2
= V0 or Vi

Vo

79. In the transistor circuit shown in figure. Collector to ground voltage is +20V. Which of
the following is the probable cause of error?
(GATE-1994)
(a) Collector Emitter terminals shorted
20 V
(b) Emitter to ground connection open
(c) 10 K resistor open
10 k
(d) Collector base terminals shorted
+ 10 V 47 K

Sol: Given that collector to ground voltage is 20 V i.e, collector to ground is nothing but
collector to emitter voltage = 20 V. So no current passing through 10 K. So collector
directly connected to 20 V supply.
From their we conclude that IE = IC = 0, IB = 0.
Emitter to ground is open circuited.
Ans: (b)
80. A practical R.C sinusoidal oscillator is built using a positive feedback amplifier with a
closed loop gain slightly less than unity. (TRUE/FALSE)
(GATE-1994)
Sol: A sinusoidal oscillator is built using a positive feedback amplifier and its closed loop
gain is slightly greater than unity.
Ans: (FALSE)
81. An analog comparator is a high gain amplifier whose output is always either in positive or
in negative saturation. (TRUE/FALSE)
(GATE-1994)
Sol: An analog comparator is the open loop application of op amp whose gain is very high.
In open loop mode the op amp is forced to operate in either positive or negative
saturation.
Ans: (TRUE)
82. Given figure shows a two stage small signal transistor feedback amplifier. Match the
defective component (listed on the left hand side below) with its probable effect on the
circuit (listed on the right hand side)
(GATE-1994)
VC
RC
RS C1

VS

R1

C2

R1

Re1

C5

Vo

TR2

TR1
R2

RC

R2

Re2

C3
C4

e11

RF

List I
A. Capacitor C1is open
B. Capacitor C3 is open
C. Capacitor C4 is open

List II
P. All dc voltages normal V0 increases marginally
Q. Collector of TR2 at VCC, V0 = 0
R. All dc voltages normal gain of 2nd stage decrease V0
decrease
S. All dc voltage normal V0 = 0
T. All dc voltages normal, overall gain of the amplifier
Increases, V0 increase
U. No change

D. RC2 is shorted

Sol:

If capacitor C1 is open, no i/p is connected to the circuit then V0 = 0 and the DC

voltages are unaffected.
AS
If C3 is open, the gain of the 2nd stage decreases and hence V0 decrease
BR
If C4 is open No negative feedback. So that overall gain of the amp. Increase and V0
increase
CT
If R2 is shorted collector is at VCC and AC voltage V0 becomes zero.
DQ

Ans: A S, B R, C T and D Q.
83. Given figure, shows a non inverting op amp summer with V1 = 2 V and V2 = 1V the
output voltage V0 = ___________.
(GATE-1994)
Sol: Since Vd 0

2R

Vb Va
R

Apply KCL at b
2 Vb 1 Vb Vb

R
R
R

1 = 3 Vb Vb = 1/3 Volts

2V
1V

a
R

Apply KCL at a
o Va Va V0

R
2R

2 Va = Va V0 V0 = 3 Va
= 3 Vb
1
= 3
3

= 1 Volts.
-

V0 = 1 Volts

V0