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Design Methodology:
HDL Constructs:
Learning
Simulation:
, costs
Styles of description:
Advancements
Cycle, timing,
Specific Objectives
1.
Outline
Combinational Logic - Concurrent Statements
2.
3
3.
Boolean Equations
With--SelectWith
Select-When, WhenWhen-Else
Component Instantiations
If--ThenIf
Then-Else, Case
Case--When
FIFO Example
3
Combinational Logic
L o gic
In
L o gic
Out
C ir c u i t
C i r c u it
State
( a ) C o m b i n a ti o n a l
O u t p u t = f( I n )
Combinational Logic
Outputs are functions of current
inputs only
No memory
Example: gates, multiplexers,
multiplexers,
decoders,, ALUs
decoders
( b ) S e q u en tial
Dataflow
O u t p u t = f (I n , P r e v io u s I n )
Sequential Logic
O t t are ffunctions
ti
off currentt and
d
Outputs
past inputs
Uses memory (flip(flip-flops, RAM, ROM)
Example: state machines,
machines, counters,
counters,
shift registers
registers,, FIFOs
style
Concurrent Statements
Boolean Equations
Logical
g
and Relational Operators
p
Dynamic
Domino
np--CMOS
np
With
With-SelectSelect-When
When,
,
When
When-Else
Component Instantiations
Boolean Equations
Use in both concurrent and sequential signal assignments <=
Use in sequential variable assignments :=
Cumbersome for array
y operations
p
Often good for simplesimple-toto-complex scalar operations
Examples:
Combinational Logic
Logical Operators
With--Select
With
Select--When Statement
Concurrent statement
arrays
Examples:
Syntax:
WITH selector_expression
selector expression
out_signal <=
value1
value2
...
value9
SELECT
WHEN choice1
choice1,
,
WHEN choice2
choice2,
,
WHEN choice9
choice9;
;
With--Select
With
Select--When Statement
With--Select
With
Select--When Statement
Selector expression
-- 2-toto-1 multiplexer
WITH addsub SELECT
opcode <= add WHEN 0,
sub WHEN 1;
Choices
Values
Combinational Logic
Synthesis result
10
12
When--Else Statement
When
When--Else Statement
When
Conditions
Boolean expressions
S t off conditions
Set
diti
NOT necessarily
il mutually
t ll exclusive
l i or allll inclusive
i l i
Syntax:
Synthesis results
value9;
value9
;
13
When--Else Statement
When
opcode <=
out <=
-- 4-to
to-2 priority encoder
outcode <= 11
11
WHEN in3 =
=1
1
10
10
WHEN in2 =
=1
1
01
01
WHEN in1 =
=1
1
00
00
WHEN in0 =
=1
1
00
00;
;
Can
C appear on right
i ht side
id off signal
i
l assignment
i
t
Concatenation
ELSE
ELSE
ELSE
ELSE
15
Combinational Logic
14
16
Example: IF a = 0-0--
THEN
Format: std_match
std match (name
(name, bitstring)
IF a_bit = 1 THEN
-- syntax error
-- syntax error
-- syntax
y
error
18
Component Instantiations
Sequential statements:
Syntax:
instance_label: component_name PORT MAP
(ordered_list_of_signals);
ordered_list_of_signals);
IF--THENIF
THEN-ELSE
CASE--WHEN
CASE
Combinational Logic
but signals must be used for all process inputs and outputs
20
IF--THEN
IF
THEN--ELSE Statement
IF--THEN
IF
THEN--ELSE Statement
-- optional
PROCESS (xbus
xbus)
)
BEGIN
IF xbus = XF THEN
-- optional section
doitnow <= 1;
-- optional section
END PROCESS;
include
or
21
22
IF--THEN
IF
THEN--ELSE Statement
CASE--WHEN Statement
CASE
Logically equivalent to concurrent selected signal assignment
(WITH--SELECT
(WITH
SELECT--WHEN)
Syntax:
label:
CASE selector_expression IS
WHEN choice1 => statements1
statements1;
;
WHEN choice2 => statements2
statements2;
;
WHEN choice3 => statements3
statements3;
;
WHEN OTHERS => statements4
statements4;
;
END CASE;
-- optional
-- optional
Result:
foo = x . a + x . y . b + x . y . z . c + x . y . z . d
23
Combinational Logic
-- output of a set
set-only latch
END IF;
Forms a multiplexer
multiplexer--based logic structure
24
Summary
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
With--SelectWith
Select-When (like Case), WhenWhen-Else (like IfIf-Then)
Component Instantiations
ENTITY dff IS
PORT (d,
(d, clk : IN std_logic;
q : OUT std_logic);
END dff;
ARCHITECTURE behavior OF dff IS
BEGIN
PROCESS (clk)
clk)
-- sensitive ONLY to clk
BEGIN
-- rising clk edge
IF (clkEVENT
(clkEVENT AND clk = 1
1)
) THEN q <= d
d;
;
ELSE q <= q
q;
;
-- NOT needed (implied)
END IF;
END PROCESS;
END behavior;
If--ThenIf
Then-Else (like WhenWhen-Else), CaseCase-When (like With
With--Select)
26
FIFO
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY register8 IS
PORT (d : IN std_logic_vector (0 TO 7); -- 8 bit reg.
clk : IN std_logic;
q : OUT std_logic_vector (0 TO 7));
END register8;
Combinational Logic
rdinc and wrinc increment either rdptr or wrptr to the next word
rdptrclr and wrptrclr reset either rdptr or wrptr to the first word
FIFO
FIFO
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.std_arith.all;
ENTITY fifo8x9
fif 8 9 IS PORT(
clk, rst:
rst:
rd, wr, rdinc, wrinc:
wrinc:
rdptrclr, wrptrclr:
wrptrclr:
data_in:
data_in
:
IN
data_out:
data_out
:
OUT
END fifo8x9;
8x9 FIFO
0
1
2
3
4
5
6
7
IN std_logic;
IN std_logic;
IN std_logic;
std_logic_vector(8 DOWNTO 0);
std_logic_vector(8 DOWNTO 0));
ARCHITECTURE archfifo8x9
hfif 8 9 OF fifo8x9
fif 8 9 IS
TYPE fifo
fifo_array
_array IS ARRAY(7 DOWNTO 0) OF
std_logic_vector(8 DOWNTO 0);
SIGNAL fifo
fifo:
:
fifo_array;
SIGNAL wrptr, rdptr
rdptr:
: std_logic_vector(2 DOWNTO 0);
SIGNAL en
en:
:
std_logic_vector(7 DOWNTO 0);
SIGNAL dmuxout
dmuxout:
:
std_logic_vector(8 DOWNTO 0);
29
FIFO
FIFO
READ COUNT
-- read pointer
read_count:
read_count
: PROCESS (rst, clk
clk)
)
BEGIN
IF rst = '
'1
1' THEN
Reset
rdptr <= (OTHERS => '
'0
0');
ELSIF (clk'event and clk='
clk='1
1') THEN
IF rdptrclr = '
'1
1' THEN
Pointer clear
rdptr <= (OTHERS => '
'0
0');
ELSIF rdinc = '
'1
1' THEN
Pointer increment
rdptr
d t <=
< rdptr
d t + 1
1;
;
END IF;
IF;
END IF;
END PROCESS;
30
WRITE COUNT
-- write pointer
write_count:
write_count
: PROCESS (rst, clk)
clk)
BEGIN
IF rst = '
'1
1' THEN
Reset
wrptr <= (OTHERS => '
'0
0');
ELSIF (clk'event and clk
clk='
='1
1') THEN
IF wrptrclr = '
'1
1' THEN
Pointer clear
wrptr <= (OTHERS => '
'0
0');
ELSIF wrinc = '
'1
1' THEN
wrptr <= wrptr + 1;
1;
Pointer
P i t increment
i
t
END IF;
END IF;
END PROCESS;
31
Combinational Logic
REGISTER ARRAY
BEGIN
-- fifo register array:
reg_array: PROCESS (rst, clk)
clk)
BEGIN
RESET
IF rst
t = '1
'1' THEN
FOR i IN 7 DOWNTO 0 LOOP
fifo(i) <= (OTHERS => '
'0
0');
END LOOP;
ELSIF (clk'event
(clk'event and clk = '
'1
1') THEN
IF wr = '
'1
1' THEN
FOR i IN 7 DOWNTO 0 LOOP
WRITE
IF en(i) = '
'1
1' THEN
fifo(i) <= data_in
data in;
data_in;
in;
ELSE
fifo(i) <= fifo(i)
fifo(i);
;
END IF;
END LOOP;
END IF;
END IF;
END PROCESS;
32
FIFO
FIFO
OUTPUT
REGISTER SELECTOR
p
SELECT
WITH rdptr
dmuxout <=
,
"00000001" WHEN "000",
en <=
fifo(0) WHEN "000",
"01000000"
01000000 WHEN "110"
110 ,
33
FIFO
34
rd
TRI--STATE OUTPUT
TRI
9
data_in(8:0)
fifo(0) 9
D Q
En
> R
wr
-- three
three-state control of outputs
en(0)
three_state:
three_state
: PROCESS (rd,
rd, dmuxout
dmuxout)
)
wrptr(2:0)
BEGIN
IF rd = '
'1
1' THEN
wrptrclr
wrinc
..
.
..
.
counter
Clr Q
3
En
>R
data_out(8:0)
fifo(7)
D Q
9
En
> R
counter
rdptrclr
rdinc
END PROCESS;
END archfifo8x9;
Clr Q
En
>R
rdptr(2:0)
rst
clk
35
Combinational Logic
9
dmuxout
ELSE
END IF;
..
.
36