4706 DS00 R BCM4706 Advance Data Sheet NDA Clear

Advance Data Sheet
BCM4706
Communications Processor with Network
Acceleration Hardware
GE N ER A L DE S CR I P TI O N
F E A T U RE S
The Broadcom BCM4706 processor is a

communications device targeted for wireless access
points and routers.
Advanced MIPS32 74K Core

- 32 KB I-cache, 32 KB D-cache
- BCM4706 CPU runs at 600 MHz/1200 DMIPs
On-chip SoC RAM provides low latency read/
write access to improve system performance
Advanced Gigabit Ethernet MAC
MII/RGMII/SGMII interface
Supports external GbE switch (such as
BCM53115/BCM53125)
Supports external 10/100 switch (such as
BCM5325E)
One USB 2.0 host port
16-bit/32-bit DDR2 300 MHz memory interface
Supports serial or parallel Flash
Dual PCI Express interface compliant with PCI
Express base specification revision 1.1
UART/MDIO/SPI/JTAG interface, up to 16 GPIOs
I8S audio/TDM voice interfaces
BCM4706 package: 23 mm 23 mm, 484-pin
PBGA
At the center of the device is a high-performance

600 MHz MIPS32 74K core with a 32 KB four-way
set associative instruction cache, a 32 KB four-way
set associative data cache, and a 64-entry translation
lookaside buffer (TLB). Enhanced CPU memory
subsystem architecture provides increased system
performance. The device uses state-of-the-art, low
power, and low leakage 65 nm LP technology.
The BCM4706 integrates several peripheral
interfaces including Gigabit Ethernet MACs, USB 2.0,
PCI Express, serial and parallel Flash, DDR memory,
and audio/voice TDM subsystem. Various common I/
O controllers are also integrated. These I/O
controllers include JTAG, UART, MDIO, GPIO, and SPI.
RGMII
or MII
2.5 Gbps
MIPS32 Core
(600 MHz)
DDR2
Memory Controller
2.5 Gbps
SerDes
EJTAG
I-Cache
32 KB
D-Cache
32 KB
SGMII/
SerDes
480 Mbps
SerDes
SerDes
USB Phy
PCle
1x1
PCle
1x1
USB 2.0
Host
GMAC
GMAC
Parser/FP
Parser/FP
DMA
DMA
CPU Local Bus

SoC-RAM
(512 KB)
System Bus
System Bus
TDM
Peripheral Interface
GPIO
Serial
Flash
Parallel
Flash
8b/16b
SPI
I2C
UART
/I2C
UART
I8S/TDM
2 VOIP Channels
or
8 Audio Channels
Figure 1: Functional Block Diagram

4706-DS00-R
5300 California Avenue Irvine, CA 92617 Phone: 949-926-5000 Fax: 949-926-5203
4/12/2011 DXKOG
June 02, 2010
Revision History
Revision
Date
Change Description
4706-DS00-R
06/02/10
Initial release
Broadcom Corporation
5300 California Avenue
Irvine, CA 92617
2010 by Broadcom Corporation
All rights reserved
Printed in the U.S.A.
Broadcom, the pulse logo, Connecting everything, and the Connecting everything logo are among the
trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/
or the EU. Any other trademarks or trade names mentioned are the property of their respective owners.
This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed,
intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations,
pollution control, hazardous substances management, or other high risk application. BROADCOM PROVIDES
THIS DATA SHEET "AS-IS", WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES,
EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT.
4/12/2011 DXKOG
BCM4706 Advance Data Sheet
Table of Contents
Table of Contents
Section 1: Functional Description ...................................................................................... 9
Overview.........................................................................................................................................................9
MIPS Core .......................................................................................................................................................9
Reset ...............................................................................................................................................................9
Crystal Oscillator and Clock Generator..........................................................................................................9
DDR2 SDRAM Interface ................................................................................................................................10
USB 2.0 Host Controllers ..............................................................................................................................10
PCI Express Interface ....................................................................................................................................10
Transaction Layer Interface ...................................................................................................................11
Data Link Layer.......................................................................................................................................11
Physical Layer.........................................................................................................................................12
Logical Subblock.....................................................................................................................................12
Scrambler/Descrambler.........................................................................................................................12
8B/10B Encoder/Decoder ......................................................................................................................12
Elastic FIFO.............................................................................................................................................12
Electrical Subblock .................................................................................................................................13
Configuration Space...............................................................................................................................13
10/100/1000 Ethernet MAC Controller .......................................................................................................13
Flash Interface ..............................................................................................................................................13
SPI/UART/GPIO Interface.............................................................................................................................14
I8S/TDM Interface ........................................................................................................................................14
Section 2: Hardware Signal Descriptions.......................................................................... 15

BCM4706 Pin Tables .....................................................................................................................................21
BCM4706 Ballmap ........................................................................................................................................27
Section 3: Electrical Characteristics.................................................................................. 28

Absolute Maximum Ratings .........................................................................................................................28
Recommended Operating Conditions and DC Characteristics....................................................................29
Core and I/O Power Sequencing Requirements ..........................................................................................30
DDR2 SDRAM Memory Interface DC Characteristics ..................................................................................31
USB Host Interface DC Characteristics .........................................................................................................31
PCIe DC Characteristics.................................................................................................................................33
1G SGMII/SerDes Port Signals......................................................................................................................33
Standard 3.3V Signals...................................................................................................................................34
Standard 2.5V Signals...................................................................................................................................34
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Table of Contents
XTAL Oscillator Interface..............................................................................................................................34
Section 4: Timing Characteristics ..................................................................................... 35

Reset and Clock Timing ................................................................................................................................35
Parallel Flash Timing.....................................................................................................................................36
Parallel Flash READ Timing.....................................................................................................................36
Parallel Flash WRITE Timing...................................................................................................................37
Serial Flash Timing (ST Micro-compatible Device) ......................................................................................38
DDR2 SDRAM AC Timing Characteristics .....................................................................................................39
USB Host Interface AC Timing Characteristics .............................................................................................40
PCIe Interface Timing ...................................................................................................................................41
PCIe_REFCLKP/N Timing ........................................................................................................................41
MII Interface Timing .....................................................................................................................................43
MII Input Timing.....................................................................................................................................43
MII Output Timing..................................................................................................................................44
RGMII Interface Timing ................................................................................................................................45
RGMII Output Timing (Normal Mode) ...................................................................................................45
RGMII Output Timing (Delayed Mode) ..................................................................................................46
RGMII Input Timing (Normal Mode) ......................................................................................................47
RGMII Input Timing (Delayed Mode) .....................................................................................................48
SGMII/SerDes Serial Interface......................................................................................................................49
Serial Interface Output Timing...............................................................................................................49
Serial Interface Input Timing..................................................................................................................50
I8S/TDM Audio/Video AC Specification ......................................................................................................51
JTAG Interface ..............................................................................................................................................52
MDC/MDIO Master Interface ......................................................................................................................53
SPI Master Interface .....................................................................................................................................54
Timing Parameters for CPHA=0 .............................................................................................................54
Timing Parameters for CPHA=1 .............................................................................................................55
Section 5: Thermal Specifications .................................................................................... 56

BCM4706.......................................................................................................................................................56
BCM4706 Thermal Specifications Without External Heatsink at 70C ..................................................56
BCM4706 Thermal Specifications with External Heatsink at 70C.........................................................57
BCM4706 Thermal Specifications Without External Heatsink at 85C ..................................................58
BCM4706 Thermal Specifications with External Heatsink at 85C.........................................................59
Section 6: Mechanical Information.................................................................................. 60

BCM4706.......................................................................................................................................................60
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Table of Contents
Section 7: Ordering Information ...................................................................................... 61
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List of Figures
List of Figures
Figure 1: Functional Block Diagram....................................................................................................................1
Figure 2: PCI Express Layer Model ...................................................................................................................11
Figure 3: BCM4706 BallmapTop View...........................................................................................................27
Figure 4: Power Supply Sequencing .................................................................................................................30
Figure 5: Reset and Clock Timing......................................................................................................................35
Figure 6: Parallel Flash READ Timing Diagram..................................................................................................36
Figure 7: Parallel Flash WRITE Timing Diagram ................................................................................................37
Figure 8: Serial Flash Timing Diagram ..............................................................................................................38
Figure 9: PCIe_REFCLKP/N Timing ....................................................................................................................41
Figure 10: PCIe[1:0]_RDP/N Timing..................................................................................................................41
Figure 11: PCIe[1:0]_TDP/N Timing..................................................................................................................42
Figure 12: MII Input Timing ..............................................................................................................................43
Figure 13: MII Output Timing ...........................................................................................................................44
Figure 14: RGMII Output Timing (Normal Mode).............................................................................................45
Figure 15: RGMII Output Timing (Delayed Mode)............................................................................................46
Figure 16: RGMII Input Timing (Normal Mode)................................................................................................47
Figure 17: RGMII Input Timing (Delayed Mode)...............................................................................................48
Figure 18: Serial Interface Output Timing ........................................................................................................49
Figure 19: Serial Interface Input Timing ...........................................................................................................50
Figure 20: IXS Transmitter Timing ....................................................................................................................51
Figure 21: IXS Receiver Timing .........................................................................................................................51
Figure 22: JTAG Interface .................................................................................................................................52
Figure 23: MDC/MDIO Master Interface..........................................................................................................53
Figure 24: SPI Master Interface: Timing Parameters for CPHA=0 ....................................................................54
Figure 25: SPI Master Interface: Timing Parameters for CPHA=1 ....................................................................55
Figure 26: BCM4706 Mechanical Information .................................................................................................60
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List of Tables
List of Tables
Table 1: Hardware Signals ................................................................................................................................15
Table 2: BCM4706 Sorted by Pin Location .......................................................................................................21
Table 3: BCM4706 Sorted by Signal Name .......................................................................................................24
Table 4: Absolute Maximum Ratings................................................................................................................28
Table 5: Recommended Operating Conditions ................................................................................................29
Table 6: Total Power and Supply Current.........................................................................................................29
Table 7: DC Characteristics for DDR2 SDRAM Interface...................................................................................31
Table 8: USB Host Interface DC Characteristics................................................................................................31
Table 9: USB 1.1 Electrical and Timing Parameters..........................................................................................32
Table 10: PCIe DC Characteristics.....................................................................................................................33
Table 11: 1G SGMII/SerDes Port Signals ..........................................................................................................33
Table 12: Standard 3.3V Signals .......................................................................................................................34
Table 13: Standard 2.5V Signals .......................................................................................................................34
Table 14: XTAL Oscillator Interface ..................................................................................................................34
Table 15: Reset and Clock Timing.....................................................................................................................35
Table 16: Parallel Flash READ Timing ...............................................................................................................36
Table 17: Parallel Flash WRITE Timing..............................................................................................................37
Table 18: Serial Flash Timing ............................................................................................................................38
Table 19: AC Characteristics for DDR SDRAM Interface ...................................................................................39
Table 20: USB 2.0 Host Interfaces Timing Parameters .....................................................................................40
Table 21: USB 1.1 Timing Parameters ..............................................................................................................40
Table 22: PCIe_REFCLKP/N Timing ...................................................................................................................41
Table 23: PCIe[1:0]_RDP/N Timing...................................................................................................................42
Table 24: PCIe[1:0]_TDP/N Timing ...................................................................................................................42
Table 25: MII Input Timing ...............................................................................................................................43
Table 26: MII Output Timing ............................................................................................................................44
Table 27: RGMII Output Timing (Normal Mode) ..............................................................................................45
Table 28: RGMII Output Timing (Delayed Mode).............................................................................................46
Table 29: RGMII Input Timing (Normal Mode) .................................................................................................47
Table 30: RGMII Input Timing (Delayed Mode)................................................................................................48
Table 31: Serial Interface Output Timing .........................................................................................................49
Table 32: Serial Interface Input Timing ............................................................................................................50
Table 33: IXS Receiver Timing...........................................................................................................................51
Table 34: JTAG Interface...................................................................................................................................52
Table 35: MDC/MDIO Master Interface ...........................................................................................................53
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List of Tables
Table 36: SPI Master Interface .........................................................................................................................54

Table 37: Timing Parameters for CPHA=1 ........................................................................................................55
Table 38: Package for 2s2p Board,
TA = 70C, P = 2.7W from Simulation ..............................................................................................56
Table 39: BCM4706 Thermal Specifications Without External Heatsink at 70C .............................................56
Table 40: Package with 30x30x25 mm External Heat Sink on 2s2p Board,
Table 41: BCM4706 Thermal Specifications with 30x30x25 mm External Heatsink at 70C............................57
TA = 85 C, P = 2.7 W from Simulation ............................................................................................58
Table 43: BCM4706 Thermal Specifications Without External Heatsink at 85C .............................................58
Table 45: BCM4706 Thermal Specifications with 30x30x25 mm External Heatsink at 85C............................59
Table 46: Ordering Information .......................................................................................................................61
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Functional Description
Section 1: Functional Description

Overview
The Broadcom BCM4706 is a family of processors optimized for power and cost without compromising
performance. Integrating a high-performance 600 MHz MIPS32 74KTM core with a 32 KB four-way set
associative instruction cache, a 32 KB four-way set associative data cache, and a 64-entry TLB, the BCM4706
offers significant performance improvements in both transfer rates and CPU utilization.
Flexible support for a variety of system bus interfaces is provided including Gigabit Ethernet MACs, an audio/
voice TDM unit, a USB 2.0 host port, PCI Express (X1 lane), 16-bit/32-bit DDR2 300 MHz memory control, serial
Flash port, and 16-bit parallel Flash port. There are 16 GPIOs on the BCM4706 processor. All inputs can be used
to generate processor interrupts.
MIPS Core
The chip integrates an advanced 600 MHz MIPS32 74K core with a 32 KB four-way set associative I-cache and
a 32 KB four-way set associative D-Cache. The MIPS32 74K core has an integrated 32 32-bit single-cycle
multiply/accumulate block running at CPU core speed, providing additional signal or media processing
capabilities. The integrated MMU with a 64-entry TLB block is included, allowing support for common
multithreaded real-time operating systems (RTOS) such as the standard Linux distribution.
Reset
A power-on or hard reset is initiated by an active low reset pulse on the RESET_N Schmitt-triggered input pin.
The reset signal has a minimum required low pulse duration to guarantee that a sufficiently long reset is applied
to all internal circuits, including integrated PHYs (see Table 15: Reset and Clock Timing, on page 35). The
initialization process loads all pin configurable modes, resets all internal processes, and puts the device in the
idle state. During initialization, the clock source input signal must be active, and the 3.3V power supply to the
device must be stable.
Crystal Oscillator and Clock Generator

A typical BCM4706-based platform requires only a single crystal to clock the entire device. Several internal PLLs
are driven by the oscillator and generate the various clocks, including the clock for the 10/100/1000 MAC core
and the MIPS32 74K, DDR2 SDRAM, PCIe, UART, and USB 2.0 host controllers.
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DDR2 SDRAM Interface
DDR2 SDRAM Interface

The integrated DDR2 controller has on-chip serial termination resistors on the address, data and control
signals, except DDR clocks. The differential clock pair needs external serial termination resistors. Additionally,
VREF pin must be set to half of the DDR_OVDD_1P8 voltage. This can be accomplished by using two equal value
resistors to divide the DDR_OVDD_1P8 voltage.
USB 2.0 Host Controllers

The BCM4706 integrates a USB 2.0 host controller that supports high-speed USB 2.0 ports. It is also backward
compatible with full-speed and low-speed USB 1.1 devices. Each host port has a dedicated overcurrent input
to notify the OS or driver to take appropriate action. Individual port power control is also available.
PCI Express Interface

The PCI Express (PCIe) core on the BCM4706 is a high performance serial I/O interconnect that is protocol
compliant and electrically compatible with the PCI Express Base Specification v1.1. This core contains all the
necessary blocks, including logical and electrical functional subblocks, to perform PCIe functionality and
maintain high-speed links using existing PCI system configuration software implementations without
modification.
The PCIe core is organized in logical layers: Transaction Layer, Data Link Layer, and Physical Layer, as shown in
Figure 2. A configuration or link management block is provided for enumerating the PCIe configuration space
and supporting generation and reception of System Management Messages by communicating with PCIe
layers.
Each layer is partitioned into dedicated transmit and receive units that allow point-to-point communication
between the host and BCM4706 device. The transmit side processes outbound packets while the receive side
processes inbound packets. Packets are formed and generated in the Transaction and Data Link Layer for
transmission onto the high-speed links and onto the receiving device. A header is added at the beginning to
indicate the packet type and any other optional fields.
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HW/SW Interface
HW/SW Interface
Transaction
Layer
Transaction
Layer
Data Link
Layer
Data Link
Layer
Physical Layer
Physical Layer
Logical Subblock
Logical Subblock
Electrical Subblock
Electrical Subblock
TX
TX
RX
RX
Figure 2: PCI Express Layer Model
Transaction Layer Interface

The PCIe core employs a packet-based protocol to transfer data between the host and BCM4706 device,
delivering new levels of performance and features. The upper layer of the PCIe is the Transaction Layer, which
is primarily responsible for assembly and disassembly of transaction layer packets (TLPs). TLP structure
contains header, data payload, and end-to-end CRC (ECRC) fields, which are used to communicate transactions,
such as read and write requests and other events.
A pipelined full split-transaction protocol is implemented in this layer to maximize efficient communication
between devices with credit-based flow control of TLP, which eliminates wasted link bandwidth due to retries.
Data Link Layer

The data link layer serves as an intermediate stage between the transaction layer and the physical layer. Its
primary responsibility is to provide a reliable, efficient mechanism for the exchange of TLPs between two
directly connected components on the link. Services provided by the data link layer include data exchange,
initialization, error detection and correction, and retry services.
Data link layer packets (DLLPs) are generated and consumed by the data link layer. DLLPs are the mechanism
used to transfer link management information between data link layers of the two directly connected
components on the link, including TLP acknowledgement, power management, and flow control.
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Physical Layer
The physical layer of the PCIe provides a handshake mechanism between the data link layer and the high-speed
signaling used for Link data interchange. This layer is divided into the logical and electrical functional subblocks.
Both subblocks have dedicated transmit and receive units that allow for point-to-point communication
between the host and PCIe device. The transmit section prepares outgoing information passed from the data
link layer for transmission, and the receiver section identifies and prepares received information before passing
it to the data link layer. This process involves link initialization, configuration, scrambler, and data conversion
into a specific format.
Logical Subblock
The logical subblocks primary functions are to prepare outgoing data from the data link layer for transmission
and identify received data before passing it to the data link layer.
Scrambler/Descrambler
This PCIe PHY component generates a pseudo-random sequence for scrambling of data bytes and the idle
sequence. On the transmit side, scrambling is applied to characters prior to the 8b/10b encoding. On the
receive side, descrambling is applied to characters after 8b/10b decoding. Scrambling may be disabled in
polling and recovery for testing and debugging purposes.
8B/10B Encoder/Decoder
The PCIe core on the BCM4706 uses an 8b/10b encoder/decoder scheme to provide DC balancing, clock
synchronization and data recovery, and error detection. The transmission code is specified in ANSI X3.2301994, clause 11 and in IEEE 802.3z, 36.2.4.
Using this scheme, 8-bit data characters are treated as 3 bits and 5 bits mapped onto a 4-bit code group and a
6-bit code group, respectively. The control bit in conjunction with the data character is used to identify when
to encode one of the twelve Special Symbols included in the 8b/10b transmission code. These code groups are
concatenated to form a 10-bit Symbol, which is then transmitted serially. Special Symbols are used for link
management, frame TLPs, and DLLPs, allowing these packets to be quickly identified and easily distinguished.
Elastic FIFO
An elastic FIFO is implemented in the receiver side to compensate for the differences between the transmit
clock domain and the receive clock domain, with worst case clock frequency specified at 600 ppm tolerance.
As a result, the transmit and receive clocks can shift one clock every 1666 clocks. In addition, the FIFO
adaptively adjusts the elastic level based on the relative frequency difference of the write and read clock. This
technique reduces the elastic FIFO size and the average receiver latency by half.
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10/100/1000 Ethernet MAC Controller
Electrical Subblock
The high-speed signals utilize the common mode logic (CML) signaling interface with on-chip termination and
deemphasis for best in class signal integrity. A deemphasis technique is employed to reduce the effects of
intersymbol interference (ISI) due to the interconnect by optimizing voltage and timing margins for worst case
channel loss. This results in a maximally open eye at the detection point, thereby allowing the receiver to
receive data with an acceptable bit-error rate (BER).
To further minimize ISI, multiple bits of the same polarity that are output in succession are deemphasized.
Subsequent same bits are reduced by a factor of 3.5 dB in power. This amount is specified by PCIe to allow for
maximum interoperability while minimizing the complexity of controlling the deemphasis values. The highspeed interface requires AC coupling on the transmit side to eliminate the DC common mode voltage from the
receiver. The range of AC capacitance allowed is 75 nF to 200 nF.
Configuration Space
The PCIe function in the BCM4706 implements the configuration space as defined in the PCI Express Base
Specification v1.1.
10/100/1000 Ethernet MAC Controller

The BCM4706 integrates a high performance yet flexible Ethernet MAC controller. GMAC port 0 of the
BCM4706 supports the following interfaces through strap pin settings:
RGMII: 10/100/1000 Mbps mode
MII: 10/100 Mbps mode
The BCM4706 supports a second GMAC with SGMII interface in 10/100/1000 Mbps mode. These interfaces can
work with a wide variety of Ethernet PHYs and switches.
In RGMII mode, the bus signals operate at 2.5V, with the exception that the MDIO and MDC pins operate at
3.3V. All the Ethernet MAC controller output pins have built-in series termination so external termination
resistors are not required.
Flash Interface
An on-chip, 16-bit external bus interface (EBI) provides the following connectivity options:
16-bit NOR or NAND flash memory. BCM4706 supports up to 256 MB.
Serial Flash (ST-compatible four-pin SPI interface)
The BCM4706 has two Flash chip select pins so it can support up to two Flash devices in any of the
combinations in the following list:
One parallel Flash
One serial Flash
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SPI/UART/GPIO Interface
Two parallel Flash

Two serial Flash
One serial Flash + one parallel Flash (either the serial Flash or parallel Flash can be the boot device)
One serial Flash + NAND Flash (serial Flash must be the boot device to set up the on-chip NAND Flash
controller before it is accessed)
The BCM4706 has 16-bit parallel Flash data pins and supports either an 8-bit or 16-bit parallel Flash through
strap-pin settings when the parallel Flash is the boot device. However, byte-mode configuration should not be
used when 16-bit parallel Flash is used. When the BCM4706 is used in a configuration with two parallel Flash
devices, mixing of 8-bit and 16-bit parallel Flash memory is not supported.
SPI/UART/GPIO Interface
The BCM4706 supports one dedicated two-wire UART interface (UART_TX and UART_RX pins). It can support
one additional UART interface by sharing GPIO pins. The BCM4706 also supports one SPI master. The pin
sharing is enabled by software with the following configuration:
GPIO[3:0] and GPIO[9:8] can be configured as the SPI master interface.
GPIO[7:6] can be configured as the UART interface.
There are 16 3.3V GPIO pins on the BCM4706. These pins can be used to connect to various external devices.
Upon power-up and reset, these pins become tristated. Subsequently, they can be programmed to be either
input or output pins via the GPIO control register.
I8S/TDM Interface
The BCM4706 integrates a Voice/Audio TDM subsystem core that provides support for up to two full-duplex
voice channel conversations or up to eight audio channels for stereo or multichannel music/sound acquisition
or playback applications. The BCM4706 supports various flavors of TDM interface operations to work with
external A/D or D/A devices. The following list contains the possible channel combinations:
Audio/voice output only: one three-wire I8S/TDM interface
Audio/voice input only: one three-wire I8S/TDM interface
Full-duplex audio/voice: two three-wire I8S/TDM interfaces or one four-wire TDM interface
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Hardware Signal Descriptions
Section 2: Hardware Signal Descriptions

The section describes the BCM4706 hardware signals and uses the following conventions:
I = Input signal
O = Output signal
I/O = Bidirectional signal
IPD = Input Signal with internal pull-down
IPU = Input Signal with internal pull-up
Table 1: Hardware Signals
Pin Names
I/O
Pin Description
DDR SDRAM Interface

DDR_SDRAM_ADDR[14:0]
DDR_SDRAM_BA[2:0]
DDR_SDRAM_CAS
DDR_SDRAM_CKE
DDR_SDRAM_CS_N
DDR_SDRAM_ODT
DDR_SDRAM_RAS
DDR_SDRAM_REF
O
O
O
O
O
O
O
I
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
0.9V
DDR_SDRAM_WE
DDR_SDRAM_ZQ
O
I/O
1.8V
DDR_SDRAM_CK0P/N
DDR_SDRAM_CK2P/N
DDR_SDRAM_DM[3:0]
DDR_SDRAM_DQSP[3:0]
DDR_SDRAM_DQSN[3:0]
DDR_SDRAM_DQ[31:0]
O
O
O
I/O
I/O
I/O
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
DDR2 address bus

DDR2 bank address
DDR2 column address select
DDR2 clock enable
DDR2 chip select
DDR2 on-die termination
DDR2 row address select
0.9V (DDR_OVDD_1P8 divided by two) DDR2 reference
voltage
DDR2 write enable
Output impedance calibration. This pin should be attached to
a 240 resister to VSS for impedance calibration.
DDR2 differential clock pair for byte lane 1 and 0
DDR2 differential clock pair for byte lane 3 and 2
DDR2 data mask
DDR2 differential pair data strobe for byte lane 3 to 0
DDR2 differential pair data strobe for byte lane 3 to 0
DDR2 data bus
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Table 1: Hardware Signals (Cont.)

Pin Names
I/O
Pin Description
Parallel Flash Interface/Strap Pins

Note: Strap pin values are latched during reset, after reset the pin behaves as a Flash address pin.
FLASH_ADDR[26:0]
IPD/O 3.3V
When connecting to NAND Flash:
FLASH_ADDR0: NAND Flash CLE (command latch enable)
output.
FLASH_ADDR1: NAND Flash ALE (address latch enable)
output.
FLASH_ADDR2: NAND Flash WP# (write protect) output
(active low).
FLASH_ADDR21: NAND Flash R/B# (ready/not busy) input
with internal pullup.
FLASH_ADDR[4:20], [22:25]: Unused.
FLASH_ADDR6/
IPD/O 3.3V
MIPS EJTAG mode enable:
MIPS_EJTAG_MODE
0: General JTAG interface
1: MIPS EJTAG interface (connect to ICE)
FLASH_ADDR8/
IPD/O 3.3V
Ethernet interface voltage level select:
GMAC_VSEL
Set this pin low to configure port 0 GMAC interface to
operate in 2.5V RGMII.
Set this pin high for 3.3V MII.
FLASH_ADDR12/PCIe_DIS IPD/O 3.3V
PCIe port 1 disable:
0: PCIe port 1 is enabled.
1: PCIe port 1 is disabled for power saving.
FLASH_ADDR16/
IPD/O 3.3V
PCIe SerDes reference clock select:
PCIe_REFCLKSEL
0: Use internal PLL to generate 100 MHz clock.
1: Use the external 100 MHz differential clock source,
through PCIe_REFCLKP/N pins.
FLASH_ADDR17/
IPD/O 3.3V
Boot Flash type, depending on SFLASH_BOOT setting, this pin
BOOT_FLASH_TYPE
specifies the parallel Flash or serial Flash boot device type:
If (SFLASH_BOOT == 0):
0: 8-bit parallel Flash
1: 16-bit parallel Flash
If (SFLASH_BOOT == 1):
0: ST-compatible serial Flash
1: Atmel serial Flash
FLASH_ADDR18/
IPD/O 3.3V
Specifies using parallel Flash or serial Flash as the boot device:
SFLASH_BOOT
0: Boot device is a parallel Flash
1: Boot device is a serial Flash
FLASH_ADDR19/
IPD/O 3.3V
MIPS endian setting:
MIPS_ENDIAN
0: Little endian
1: Big endian
BROADCOM
June 02, 2010 4706-DS00-R
Page 16
4/12/2011 DXKOG

Pin Names
I/O
FLASH_ADDR22/
TX_DELAY_MODE
IPD/O 3.3V
FLASH_ADDR23/
RX_DELAY_MODE
IPD/O 3.3V
FLASH_ADDR[25:24]/
GMAC_MODE
IPD/O 3.3V
FLASH_CS0_N
3.3V
FLASH_CS1_N
3.3V
FLASH_DATA[15:0]
I/O
3.3V
FLASH_OE_N
3.3V
FLASH_WE_N
3.3V
Pin Description
GMAC port 0 transmit interface 2 ns delay mode:
0: No delay
1: Enable 2 ns delay
GMAC port 0 receive interface 2 ns delay mode:
0: No delay
1: Enable 2 ns delay
GMAC port 0 interface mode:
2'b01: MII mode
2'b1x: RGMII mode
Chip select for the boot Flash (active low). Can be connected
to serial or parallel Flash
Chip select for second Flash (active low). Can be connected to
serial, parallel, or NAND Flash
Parallel/NAND Flash data bus. External pull downs are
required when unused.
Output enable (active low). NAND Flash RE# (read enable)
output (active low)
Write enable (active low). NAND Flash WE# (write enable)
output (active low)
Ethernet Interface (RGMII/MII)

Port 0
Note: RGMII10/100/1000 Mbps; MII10/100 Mbps only
GMAC_COL
IPD
2.5V/3.3V Collision detect
GMAC_CRS
IPD
2.5V/3.3V Carrier sense
GMAC_RXCLK
IPD/O 2.5V/3.3V Receive clock
GMAC_RXD[3:0]
IPD
2.5V/3.3V Receive data
GMAC_RXDV
IPD
2.5V/3.3V Receive data valid
GMAC_RXER
IPD
2.5V/3.3V Receive error
GMAC_TXCLK
IPD/O 2.5V/3.3V Transmit clock
GMAC_TXD[3:0]
O
2.5V/3.3V Transmit data
GMAC_TXEN
O
2.5V/3.3V Transmit enable
GMAC_TXER
O
2.5V/3.3V Transmit error
Port 1
Note: SGMII10/100/1000 Mbps
SGMII_TXDP
O
1.2V
SGMII SerDes transmit data
SGMII_TXDN
O
1.2V
SGMII SerDes transmit data
SGMII_RXDP
I
1.2V
SGMII SerDes receive data
SGMII_RXDN
I
1.2V
SGMII SerDes receive data
BROADCOM
June 02, 2010 4706-DS00-R
Page 17
4/12/2011 DXKOG

Pin Names
I/O
Pin Description
GPIO/SPI/UART Interfaces (internal PU/PD of GPIOs is user-configurable through register setting)

GPIO0/SPI_SCLK
I/O
3.3V
GPIO bit 0 or SPI master clock output
GPIO1/SPI_SS0
I/O
3.3V
GPIO bit 1 or first SPI master select output
GPIO2/SPI_MOSI
I/O
3.3V
GPIO bit 2 or SPI master data output
GPIO3/SPI_MISO
I/O
3.3V
GPIO bit 3 or SPI master data input
GPIO4
I/O
3.3V
GPIO bit 4
GPIO5/
I/O
3.3V
GPIO bit 5
GPIO6/UART_RX2
I/O
3.3V
GPIO bit 6 or 2nd UART receive data input
GPIO7/UART_TX2
I/O
3.3V
GPIO bit 7 or 2nd UART transmit data output
GPIO8/SPI_SS1
I/O
3.3V
GPIO bit 8 or second SPI select
GPIO9/SPI_SS2
I/O
3.3V
GPIO bit 9 or third SPI select
GPIO10/FLASH_CS2_N
I/O
3.3V
GPIO bit 10 or additional chip select
GPIO11/FLASH_CS3_N
I/O
3.3V
GPIO bit 11 or additional chip select
GPIO[12:15]
I/O
3.3V
GPIO bits 12 to 15
JTAG Interface
JTCK
IPU
3.3V
JTAG clock
JTDI
IPU
3.3V
JTAG data input
JTDO
O
3.3V
JTAG data output
JTMS
IPU
3.3V
JTAG mode select
JTRST
IPU
3.3V
JTAG reset (active low)
MIIM Interface
MDC
O
3.3V
Management clock
MDIO
IPD/O 3.3V
Management data
PCIe Interface
PCIe0_RDN
I
1.2V
Negative leg of the differential pair receive serial data on PCIe
port 0
PCIe0_RDP
I
1.2V
Positive leg of the differential pair receive serial data on PCIe
port 0
PCIe0_TDN
O
1.2V
Negative leg of the differential pair transmit serial data on PCIe
port 0
PCIe0_TDP
O
1.2V
Positive leg of the differential pair transmit serial data on PCIe
port 0
PCIe0_RST_N
O
1.2V
PCIe port 0 reset (active low)
PCIe1_RDN
I
1.2V
Negative leg of the differential pair receive serial data on PCIe
port 1
PCIe1_RDP
I
1.2V
Positive leg of the differential pair receive serial data on PCIe
port 1
PCIe1_TDN
O
1.2V
Negative leg of the differential pair transmit serial data on PCIe
port 1
BROADCOM
June 02, 2010 4706-DS00-R
Page 18
4/12/2011 DXKOG

Pin Names
I/O
Pin Description
PCIe1_TDP
1.2V
PCIe1_RST_N
PCIe_REFCLKOUTP/N
PCIe_REFCLKP/N
O
O
I
1.2V
1.2V
1.2V
Positive leg of the differential pair transmit serial data on PCIe

port 1
PCIe port 1 reset (active low)
100 MHz reference clock output differential pair
100 MHz reference clock input differential pair
This is used when FLASH_ADDR16/PCIe_REFCLKSEL pin is
enabled.
O
O
IPU
3.3V
3.3V
3.3V
Clock output for serial Flash

Data output signal driving serial Flash
Data input from serial Flash
IPU/O
IPU/O
IPU/O
IPU/O
IPU/O
IPU/O
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
TDM channel 0 bit clock

TDM channel 0 serial data input/output
TDM channel 0 word select
TDM channel 1 bit clock
TDM channel 1 serial data input/output
TDM channel 1 word select
IPU
O
3.3V
3.3V
UART receive data

UART transmit data
I/O
I/O
1.2V
1.2V
USB differential pair data

USB resistance reference. This pin should be connected to an
external 4.02 k resistor in parallel with a 100 pF capacitor to
ground.
USB over-current-detect input pin
Serial Flash Interface

SFlash_CLK
SFlash_SO
SFlash_SI
I8S/TDM Interface
TDM0_BITCLK
TDM0_SDIO
TDM0_WS
TDM1_BITCLK
TDM1_SDIO
TDM1_WS
UART Interface
UART_RX
UART_TX
USB Interface
USB_DATA_N/P
USB_RREF
USB_OCD
Miscellaneous Interface
RESET_N
XTALI
XTALO
OSC_XTAL_SEL
IPU
3.3V
IPU
I
O
IPD
3.3V
3.3V
3.3V
3.3V
NC
Chip reset, active low, Schmitt-triggered

25 MHz crystal/oscillator input
Crystal output
25 MHz oscillator/crystal input clock select, 0V: selects crystal,
3.3V: selects oscillator
No connect
BROADCOM
June 02, 2010 4706-DS00-R
Page 19
4/12/2011 DXKOG

Pin Names
I/O
Power
CORE_DVDD_1P2
CORE_PLLAVDD_1P2
MISC1_PLLAVDD_1P2
MISC2_PLLAVDD_1P2
DDR_OVDD_1P8
INT_OVDD_33
1.2V
1.2V
1.2V
1.2V
1.8V
3.3V
GMAC_OVDD_25_33
PCIe_PLLVDD_1P2
PCIe_SDVDD_1P2
SGMII_PLLAVDD_1P2
SGMII_VDD_1P2
USB_DVDD_1P2
USB_PLLAVDD_1P2
USB_AVDD_2P5
USB_AVDD_3P3
XTAL_PLLAVDD_3P3
Ground
DVSS
PCIe_PLLVSS
PCIe_SDVSS
CORE_PLLAVSS
MISC1_PLLAVSS
MISC2_PLLAVSS
SGMII_PLLAVSS
SGMII_VSS
USB_AVSS
Pin Description
1.2V digital core power

1.2V core PLL analog power
1.2V miscellaneous PLL analog power
1.2V miscellaneous PLL analog power
1.8V DDR2 and 1.8V I/O power
3.3V interface I/O power, including Flash, I8S/TDM, GPIO,
MDC, UART, JTAG interfaces, and global clock/reset pins
2.5V/3.3V GMAC port 0 power supply, tied to 2.5V for RGMII, 3.3V for MII
1.2V
1.2V PCIe SerDes PLL analog power
1.2V
1.2V PCIe SerDes TX/RX analog power
1.2V
1.2V SGMII SerDes PLL power
1.2V
1.2V SGMII SerDes TX/RX analog power
1.2V
1.2V USB PHY PLL digital power
1.2V
1.2V USB PHY PLL analog power
2.5V
2.5V USB PHY analog power
3.3V
3.3V USB PHY analog power
3.3V
3.3V analog power for XTALI/O
0V
0V
0V
0V
0V
0V
0V
0V
0V
Ground
PCIe SerDes PLL analog ground
PCIe SerDes analog TX/RX ground
Core PLL analog ground
Miscellaneous PLL analog ground
Miscellaneous PLL analog ground
SGMII SerDes PLL ground
SGMII SerDes TX/RX ground
USB PHY ground
BROADCOM
June 02, 2010 4706-DS00-R
Page 20
4/12/2011 DXKOG
BCM4706 Pin Tables
BCM4706 Pin Tables

Table 2: BCM4706 Sorted by Pin Location
Ball Signal
Ball Signal
Ball Signal
Ball Signal
A1
DDR_OVDD_1P8
B16
FLASH_ADDR5
D10
FLASH_DATA1
F1
DDR_SDRAM_DQ24
A2
DDR_SDRAM_DQ30
B17
DVSS
D11
DDR_SDRAM_DQ25
A3
DDR_SDRAM_DQ31
FLASH_WE_N
FLASH_ADDR23/
RX_DELAY_MODE
F2
B18
F3
DDR_SDRAM_DM3
A4
JTRST
B19
UART_TX
D12
FLASH_ADDR20
F4
DVSS
A5
JTMS
B20
MDIO
D13
FLASH_ADDR15
F5
INT_OVDD_33
A6
SFlash_SO
B21
GPIO13
D14
F6
DVSS
A7
FLASH_DATA15
B22
GPIO12
FLASH_ADDR12/
PCIe_DIS
F7
INT_OVDD_33
A8
FLASH_DATA11
C1
DDR_SDRAM_DQSP3
F8
DVSS
A9
FLASH_DATA7
C2
DDR_SDRAM_DQSN3
F9
INT_OVDD_33
A10
FLASH_DATA3
C3
DDR_OVDD_1P8
A11
FLASH_ADDR26
C4
DVSS
A12
FLASH_ADDR22/
TX_DELAY_MODE
C5
JTCK
C6
DVSS
FLASH_ADDR18/
SFLASH_BOOT
C7
FLASH_DATA14
C8
DVSS
C9
FLASH_DATA6
C10
DVSS
C11
FLASH_ADDR25/
GMAC_MODE
A13
A14
FLASH_ADDR14
A15
FLASH_ADDR10
A16
FLASH_ADDR6/
MIPS_EJTAG_MODE
A17
FLASH_ADDR2
A18
FLASH_OE_N
A19
UART_RX
A20
MDC
D15
FLASH_ADDR7
D16
FLASH_ADDR4
D17
NC
D18
INT_OVDD_33
D19
RESET_N
D20
USB_OCD
D21
GPIO9/SPI_SS2
D22
INT_OVDD_33
E1
DDR_SDRAM_DQ22
E2
DDR_SDRAM_DQ23
E3
DDR_SDRAM_DQ27
E4
NC
DVSS
E5
JTDI
FLASH_ADDR17/
BOOT_FLASH_TYPE
E6
SFlash_SI
E7
FLASH_DATA13
C14
DVSS
E8
FLASH_DATA8
C12
C13
A21
GPIO15
C15
FLASH_ADDR9
E9
FLASH_DATA5
A22
GPIO14
C16
DVSS
E10
FLASH_DATA0
E11
FLASH_ADDR24/
GMAC_MODE
B1
DDR_SDRAM_DQ26
C17
FLASH_ADDR1
B2
DVSS
C18
FLASH_CS0_N
B3
DVSS
C19
INT_OVDD_33
B4
DVSS
C20
DVSS
INT_OVDD_33
F16
DVSS
F17
INT_OVDD_33
F18
DVSS
F19
GPIO5
F20
GPIO8/SPI_SS1
F21
GPIO7/UART_TX2
F22
GPIO2/SPI_MOSI
G1
DDR_OVDD_1P8
G2
DVSS
G3
DDR_OVDD_1P8
G4
DVSS
DVSS
DVSS
DVSS
G8
DVSS
G9
CORE_DVDD_1P2
G10
DVSS
CORE_DVDD_1P2
GPIO10/FLASH_CS2_N
E14
FLASH_ADDR11
E15
FLASH_ADDR8/
GMAC_VSEL
DVSS
DVSS
F15
G7
C22
D2
F14
G6
FLASH_CS1_N
FLASH_DATA10
INT_OVDD_33
FLASH_ADDR16/
PCIe_REFCLKSEL
B6
B8
DVSS
F13
E13
GPIO11/FLASH_CS3_N
DDR_SDRAM_DQ28
F12
FLASH_ADDR19/
MIPS_ENDIAN
C21
D1
INT_OVDD_33
E12
DVSS
DVSS
DVSS
F11
G5
B5
B7
F10
B9
DVSS
D3
DDR_SDRAM_DQ29
E16
FLASH_ADDR3
G11
B10
FLASH_DATA2
D4
DVSS
E17
FLASH_ADDR0
G12
DVSS
CORE_DVDD_1P2
B11
DVSS
D5
JTDO
E18
DVSS
G13
B12
FLASH_ADDR21
D6
SFlash_CLK
E19
INT_OVDD_33
G14
DVSS
DVSS
B13
DVSS
D7
FLASH_DATA12
E20
OSC_XTAL_SEL
G15
B14
FLASH_ADDR13
D8
FLASH_DATA9
E21
DVSS
G16
DVSS
D9
FLASH_DATA4
E22
GPIO6/UART_RX2
G17
DVSS
B15
DVSS
BROADCOM
June 02, 2010 4706-DS00-R
Page 21
4/12/2011 DXKOG
BCM4706 Pin Tables
Ball Signal
Ball Signal
Ball Signal
Ball Signal
G18
INT_OVDD_33
J17
DVSS
L16
DVSS
N15
DVSS
G19
GPIO4
J18
DVSS
L17
DVSS
N16
DVSS
G20
GPIO3/SPI_MISO
J19
NC
L18
PCIe_REFCLKN
N17
PCIe_SDVSS
G21
GPIO1/SPI_SS0
J20
TDM1_SDIO
L19
PCIe0_RDP
N18
PCIe_SDVSS
G22
GPIO0/SPI_SCLK
J21
TDM0_SDIO
L20
PCIe0_RDN
N19
PCIe0_TDP
H1
DDR_SDRAM_DQSP2
J22
TDM0_BITCLK
L21
PCIe_SDVDD_1P2
N20
PCIe0_TDN
H2
DDR_SDRAM_DQSN2
K1
DDR_SDRAM_DQ20
L22
PCIe1_RST_N
N21
PCIe_REFCLKOUTN
H3
DVSS
K2
DDR_SDRAM_DQ16
M1
DDR_SDRAM_DQ14
N22
PCIe_REFCLKOUTP
H4
DDR_SDRAM_DQ21
K3
DVSS
M2
DDR_SDRAM_DQ15
P1
DDR_SDRAM_DQ12
H5
DVSS
K4
DDR_SDRAM_DQ17
M3
DDR_OVDD_1P8
P2
DDR_SDRAM_DQ9
H6
DVSS
K5
DVSS
M4
DVSS
P3
DDR_OVDD_1P8
H7
DVSS
K6
DVSS
M5
DVSS
P4
DDR_SDRAM_DQ8
H8
DDR_OVDD_1P8
K7
DVSS
M6
DVSS
P5
DVSS
H9
DVSS
K8
DVSS
M7
DVSS
P6
DVSS
H10
CORE_DVDD_1P2
K9
DVSS
M8
DDR_OVDD_1P8
P7
DVSS
H11
DVSS
K10
DVSS
M9
DVSS
P8
DVSS
H12
CORE_DVDD_1P2
K11
DVSS
M10 DVSS
P9
DVSS
H13
DVSS
K12
DVSS
M11 DVSS
P10
DVSS
H14
CORE_DVDD_1P2
K13
DVSS
M12 DVSS
P11
DVSS
H15
DVSS
K14
CORE_DVDD_1P2
M13 DVSS
P12
DVSS
H16
DVSS
K15
DVSS
M14 CORE_DVDD_1P2
P13
DVSS
H17
DVSS
K16
PCIe_SDVSS
M15 DVSS
P14
CORE_DVDD_1P2
H18
NC
K17
DVSS
M16 DVSS
P15
DVSS
H19
NC
K18
PCIe_PLLVSS
M17 PCIe_SDVDD_1P2
P16
DVSS
H20
NC
K19
PCIe_SDVDD_1P2
M18 PCIe_REFCLKP
P17
DVSS
H21
TDM1_WS
K20
PCIe_SDVSS
M19 PCIe_SDVDD_1P2
P18
DVSS
H22
TDM0_WS
K21
PCIe0_RST_N
M20 PCIe_SDVSS
P19
PCIe_SDVDD_1P2
J1
DDR_SDRAM_CK2P
K22
TDM1_BITCLK
M21 PCIe1_RDP
P20
PCIe_PLLVDD_1P2
J2
DDR_SDRAM_CK2N
L1
DDR_SDRAM_DQ19
M22 PCIe1_RDN
P21
PCIe1_TDP
J3
DDR_OVDD_1P8
L2
DDR_SDRAM_DQ18
N1
DDR_SDRAM_DQSP1
P22
PCIe1_TDN
J4
DVSS
L3
DVSS
N2
DDR_SDRAM_DQSN1
R1
DDR_SDRAM_DQ11
J5
DVSS
L4
DDR_SDRAM_DM2
N3
DVSS
R2
DDR_SDRAM_DQ10
J6
DVSS
L5
DVSS
N4
DDR_SDRAM_DQ13
R3
DVSS
J7
CORE_DVDD_1P2
L6
DVSS
N5
DVSS
R4
DDR_SDRAM_DM1
J8
DVSS
L7
CORE_DVDD_1P2
N6
DVSS
R5
DVSS
J9
DVSS
L8
DVSS
N7
DVSS
R6
DVSS
J10
DVSS
L9
CORE_DVDD_1P2
N8
CORE_DVDD_1P2
R7
DVSS
J11
DVSS
L10
DVSS
N9
DVSS
R8
CORE_DVDD_1P2
J12
DVSS
L11
DVSS
N10
DVSS
R9
DVSS
J13
DVSS
L12
DVSS
N11
DVSS
R10
DDR_OVDD_1P8
J14
DVSS
L13
DVSS
N12
DVSS
R11
CORE_DVDD_1P2
J15
DVSS
L14
DVSS
N13
DVSS
R12
DVSS
J16
DVSS
L15
DVSS
N14
DVSS
R13
DVSS
BROADCOM
June 02, 2010 4706-DS00-R
Page 22
4/12/2011 DXKOG
BCM4706 Pin Tables
Ball Signal
Ball Signal
Ball Signal
Ball Signal
R14
DVSS
U13
SGMII_PLLAVDD_1P2
W12 SGMII_PLLAVDD_1P2
AA11 XTAL_PLLAVDD_3P3
R15
DVSS
U14
SGMII_VDD_1P2
W13 SGMII_VDD_1P2
AA12 XTALO
R16
DVSS
U15
DVSS
W14 SGMII_VDD_1P2
AA13 SGMII_VDD_1P2
R17
DVSS
U16
DVSS
W15 SGMII_VDD_1P2
AA14 SGMII_TXDN
R18
DVSS
U17
GMAC_OVDD_25_33
W16 GMAC_TXD1
AA15 SGMII_VDD_1P2
R19
DVSS
U18
DVSS
W17 GMAC_TXCLK
AA16 SGMII_RXDP
R20
USB_AVDD_2P5
U19
USB_AVDD_3P3
W18 GMAC_COL
AA17 SGMII_VDD_1P2
R21
PCIe_SDVDD_1P2
U20
USB_AVSS
W19 GMAC_RXDV
AA18 GMAC_TXER
R22
PCIe_SDVSS
U21
NC
W20 MISC1_PLLAVSS
AA19 GMAC_RXD3
T1
DVSS
U22
USB_DATA_N
W21 MISC2_PLLAVDD_1P2
AA20 GMAC_RXD2
T2
DVSS
V1
DDR_OVDD_1P8
W22 NC
AA21 CORE_PLLAVDD_1P2
T3
DVSS
V2
DVSS
Y1
DDR_SDRAM_DQ7
AA22 NC
T4
DVSS
V3
DVSS
Y2
DDR_SDRAM_DQ3
AB1
DDR_SDRAM_CK0P
T5
DVSS
V4
DDR_SDRAM_CKE
Y3
DDR_SDRAM_DQ0
AB2
DDR_SDRAM_CK0N
T6
DVSS
V5
DDR_SDRAM_RAS
Y4
DDR_OVDD_1P8
AB3
DDR_SDRAM_ODT
T7
DVSS
V6
DDR_OVDD_1P8
Y5
DVSS
AB4
DDR_SDRAM_WE
T8
DVSS
V7
DVSS
Y6
DDR_SDRAM_BA1
AB5
DDR_SDRAM_BA0
T9
CORE_DVDD_1P2
V8
DVSS
Y7
DDR_SDRAM_ADDR0
AB6
DDR_SDRAM_ADDR2
T10
DVSS
V9
DVSS
Y8
DDR_SDRAM_ADDR4
AB7
DDR_SDRAM_ADDR5
T11
DVSS
V10
DDR_OVDD_1P8
Y9
DDR_SDRAM_ADDR6
AB8
DDR_SDRAM_ADDR8
T12
DVSS
V11
NC
Y10
DDR_SDRAM_ADDR10
AB9
DDR_SDRAM_ADDR11
T13
DVSS
V12
DVSS
Y11
NC
AB10 DDR_SDRAM_ADDR13
T14
CORE_DVDD_1P2
V13
NC
Y12
SGMII_PLLAVSS
AB11 SGMII_PLLAVSS
T15
DVSS
V14
SGMII_VSS
Y13
SGMII_VSS
AB12 XTALI
T16
DVSS
V15
DVSS
Y14
SGMII_VSS
AB13 SGMII_VSS
T17
DVSS
V16
DVSS
Y15
SGMII_VSS
AB14 SGMII_TXDP
T18
DVSS
V17
GMAC_OVDD_25_33
Y16
SGMII_VSS
AB15 SGMII_VSS
T19
USB_DVDD_1P2
V18
DVSS
Y17
GMAC_TXEN
AB16 SGMII_RXDN
T20
NC
V19
GMAC_CRS
Y18
GMAC_TXD3
AB17 SGMII_VSS
T21
USB_AVSS
V20
MISC2_PLLAVSS
Y19
GMAC_RXER
AB18 GMAC_TXD0
T22
USB_RREF
V21
USB_PLLAVDD_1P2
Y20
CORE_PLLAVSS
AB19 GMAC_TXD2
U1
DDR_SDRAM_DQSN0
V22
USB_DATA_P
Y21
MISC1_PLLAVDD_1P2
AB20 GMAC_RXCLK
U2
DDR_SDRAM_DQSP0
W1
DDR_SDRAM_DQ6
Y22
NC
AB21 GMAC_RXD1
U3
DVSS
W2
DDR_SDRAM_DQ5
AA1
DDR_SDRAM_DQ2
AB22 GMAC_RXD0
U4
DVSS
W3
DDR_SDRAM_DQ4
AA2
DDR_SDRAM_DQ1
U5
DVSS
W4
DVSS
AA3
DDR_SDRAM_DM0
U6
DVSS
W5
DDR_SDRAM_CAS
AA4
DDR_SDRAM_REF
U7
DVSS
W6
DDR_SDRAM_CS_N
AA5
DDR_SDRAM_BA2
U8
DVSS
W7
DDR_SDRAM_ADDR3
AA6
DVSS
U9
DVSS
W8
DDR_OVDD_1P8
AA7
DDR_SDRAM_ADDR1
U10
DVSS
W9
DDR_SDRAM_ADDR9
AA8
DVSS
U11
DVSS
W10 DDR_SDRAM_ADDR12
AA9
DDR_SDRAM_ADDR7
U12
DVSS
W11 DDR_SDRAM_ZQ
AA10 DDR_SDRAM_ADDR14
BROADCOM
June 02, 2010 4706-DS00-R
Page 23
4/12/2011 DXKOG
BCM4706 Pin Tables
Table 3: BCM4706 Sorted by Signal Name

Signal
Ball
Signal
Ball
Signal
Ball
Signal
Ball
CORE_DVDD_1P2
G9
DDR_SDRAM_ADDR2
AB6
DDR_SDRAM_DQ27
E3
DVSS
C20
CORE_DVDD_1P2
G11
DDR_SDRAM_ADDR3
W7
DDR_SDRAM_DQ28
D1
DVSS
D2
CORE_DVDD_1P2
G13
DDR_SDRAM_ADDR4
Y8
DDR_SDRAM_DQ29
D3
DVSS
D4
CORE_DVDD_1P2
H10
DDR_SDRAM_ADDR5
AB7
DDR_SDRAM_DQ3
Y2
DVSS
E18
CORE_DVDD_1P2
H12
DDR_SDRAM_ADDR6
Y9
DDR_SDRAM_DQ30
A2
DVSS
E21
CORE_DVDD_1P2
H14
DDR_SDRAM_ADDR7
AA9
DDR_SDRAM_DQ31
A3
DVSS
F4
CORE_DVDD_1P2
J7
DDR_SDRAM_ADDR8
AB8
DDR_SDRAM_DQ4
W3
DVSS
F6
CORE_DVDD_1P2
K14
DDR_SDRAM_ADDR9
W9
DDR_SDRAM_DQ5
W2
DVSS
F8
CORE_DVDD_1P2
L7
DDR_SDRAM_BA0
AB5
DDR_SDRAM_DQ6
W1
DVSS
F10
CORE_DVDD_1P2
L9
DDR_SDRAM_BA1
Y6
DDR_SDRAM_DQ7
Y1
DVSS
F12
CORE_DVDD_1P2
M14
DDR_SDRAM_BA2
AA5
DDR_SDRAM_DQ8
P4
DVSS
F14
CORE_DVDD_1P2
N8
DDR_SDRAM_CAS
W5
DDR_SDRAM_DQ9
P2
DVSS
F16
CORE_DVDD_1P2
P14
DDR_SDRAM_CK0N
AB2
DDR_SDRAM_DQSN0
U1
DVSS
F18
CORE_DVDD_1P2
R8
DDR_SDRAM_CK0P
AB1
DDR_SDRAM_DQSN1
N2
DVSS
G2
CORE_DVDD_1P2
R11
DDR_SDRAM_CK2N
J2
DDR_SDRAM_DQSN2
H2
DVSS
G4
CORE_DVDD_1P2
T9
DDR_SDRAM_CK2P
J1
DDR_SDRAM_DQSN3
C2
DVSS
G5
CORE_DVDD_1P2
T14
DDR_SDRAM_CKE
V4
DDR_SDRAM_DQSP0
U2
DVSS
G6
CORE_PLLAVDD_1P2
AA21
DDR_SDRAM_CS_N
W6
DDR_SDRAM_DQSP1
N1
DVSS
G7
CORE_PLLAVSS
Y20
DDR_SDRAM_DM0
AA3
DDR_SDRAM_DQSP2
H1
DVSS
G8
DDR_OVDD_1P8
A1
DDR_SDRAM_DM1
R4
DDR_SDRAM_DQSP3
C1
DVSS
G10
DDR_OVDD_1P8
C3
DDR_SDRAM_DM2
L4
DDR_SDRAM_ODT
AB3
DVSS
G12
DDR_OVDD_1P8
G1
DDR_SDRAM_DM3
F3
DDR_SDRAM_RAS
V5
DVSS
G14
DDR_OVDD_1P8
G3
DDR_SDRAM_DQ0
Y3
DDR_SDRAM_REF
AA4
DVSS
G15
DDR_OVDD_1P8
H8
DDR_SDRAM_DQ1
AA2
DDR_SDRAM_WE
AB4
DVSS
G16
DDR_OVDD_1P8
J3
DDR_SDRAM_DQ10
R2
DDR_SDRAM_ZQ
W11
DVSS
G17
DDR_OVDD_1P8
M3
DDR_SDRAM_DQ11
R1
DVSS
B2
DVSS
H3
DDR_OVDD_1P8
M8
DDR_SDRAM_DQ12
P1
DVSS
B3
DVSS
H5
DDR_OVDD_1P8
P3
DDR_SDRAM_DQ13
N4
DVSS
B4
DVSS
H6
DDR_OVDD_1P8
R10
DDR_SDRAM_DQ14
M1
DVSS
B5
DVSS
H7
DDR_OVDD_1P8
V1
DDR_SDRAM_DQ15
M2
DVSS
B7
DVSS
H9
DDR_OVDD_1P8
V6
DDR_SDRAM_DQ16
K2
DVSS
B9
DVSS
H11
DDR_OVDD_1P8
V10
DDR_SDRAM_DQ17
K4
DVSS
B11
DVSS
H13
DDR_OVDD_1P8
W8
DDR_SDRAM_DQ18
L2
DVSS
B13
DVSS
H15
DDR_OVDD_1P8
Y4
DDR_SDRAM_DQ19
L1
DVSS
B15
DVSS
H16
DDR_SDRAM_ADDR0
Y7
DDR_SDRAM_DQ2
AA1
DVSS
B17
DVSS
H17
DDR_SDRAM_ADDR1
AA7
DDR_SDRAM_DQ20
K1
DVSS
C4
DVSS
J4
DDR_SDRAM_ADDR10 Y10
DDR_SDRAM_DQ21
H4
DVSS
C6
DVSS
J5
DDR_SDRAM_ADDR11 AB9
DDR_SDRAM_DQ22
E1
DVSS
C8
DVSS
J6
DDR_SDRAM_ADDR12 W10
DDR_SDRAM_DQ23
E2
DVSS
C10
DVSS
J8
DDR_SDRAM_ADDR13 AB10
DDR_SDRAM_DQ24
F1
DVSS
C12
DVSS
J9
DDR_SDRAM_ADDR14 AA10
DDR_SDRAM_DQ25
F2
DVSS
C14
DVSS
J10
DDR_SDRAM_DQ26
B1
DVSS
C16
DVSS
J11
BROADCOM
June 02, 2010 4706-DS00-R
Page 24
4/12/2011 DXKOG
BCM4706 Pin Tables
Signal
Ball
Signal
Ball
Signal
Ball
Signal
Ball
DVSS
J12
DVSS
N5
DVSS
T7
FLASH_ADDR14
A14
DVSS
J13
DVSS
N6
DVSS
T8
FLASH_ADDR15
D13
DVSS
J14
DVSS
N7
DVSS
T10
J15
DVSS
N9
DVSS
T11
FLASH_ADDR16/
PCIe_REFCLKSEL
E13
DVSS
DVSS
J16
DVSS
N10
DVSS
T12
C13
DVSS
J17
DVSS
N11
DVSS
T13
FLASH_ADDR17/
BOOT_FLASH_TYPE
DVSS
J18
DVSS
N12
DVSS
T15
FLASH_ADDR18/
SFLASH_BOOT
A13
DVSS
K3
DVSS
N13
DVSS
T16
K5
DVSS
N14
DVSS
T17
FLASH_ADDR19/
MIPS_ENDIAN
E12
DVSS
DVSS
K6
DVSS
N15
DVSS
T18
FLASH_ADDR2
A17
D12
DVSS
K7
DVSS
N16
DVSS
U3
FLASH_ADDR20
DVSS
K8
DVSS
P5
DVSS
U4
FLASH_ADDR21
B12
FLASH_ADDR22/
TX_DELAY_MODE
A12
FLASH_ADDR23/
RX_DELAY_MODE
D11
FLASH_ADDR24/
GMAC_MODE
E11
C11
DVSS
K9
DVSS
P6
DVSS
U5
DVSS
K10
DVSS
P7
DVSS
U6
DVSS
K11
DVSS
P8
DVSS
U7
DVSS
K12
DVSS
P9
DVSS
U8
DVSS
K13
DVSS
P10
DVSS
U9
DVSS
K15
DVSS
P11
DVSS
U10
DVSS
K17
DVSS
P12
DVSS
U11
FLASH_ADDR25/
GMAC_MODE
DVSS
L3
DVSS
P13
DVSS
U12
FLASH_ADDR26
A11
DVSS
L5
DVSS
P15
DVSS
U15
FLASH_ADDR3
E16
D16
DVSS
L6
DVSS
P16
DVSS
U16
FLASH_ADDR4
DVSS
L8
DVSS
P17
DVSS
U18
FLASH_ADDR5
B16
FLASH_ADDR6/
MIPS_EJTAG_MODE
A16
FLASH_ADDR7
D15
E15
DVSS
L10
DVSS
P18
DVSS
V2
DVSS
L11
DVSS
R3
DVSS
V3
DVSS
L12
DVSS
R5
DVSS
V7
DVSS
L13
DVSS
R6
DVSS
V8
FLASH_ADDR8/
GMAC_VSEL
DVSS
L14
DVSS
R7
DVSS
V9
FLASH_ADDR9
C15
DVSS
L15
DVSS
R9
DVSS
V12
FLASH_CS0_N
C18
DVSS
L16
DVSS
R12
DVSS
V15
FLASH_CS1_N
B6
DVSS
L17
DVSS
R13
DVSS
V16
FLASH_DATA0
E10
DVSS
M4
DVSS
R14
DVSS
V18
FLASH_DATA1
D10
DVSS
M5
DVSS
R15
DVSS
W4
FLASH_DATA10
B8
DVSS
M6
DVSS
R16
DVSS
Y5
FLASH_DATA11
A8
DVSS
M7
DVSS
R17
DVSS
AA6
FLASH_DATA12
D7
DVSS
M9
DVSS
R18
DVSS
AA8
FLASH_DATA13
E7
DVSS
M10
DVSS
R19
FLASH_ADDR0
E17
FLASH_DATA14
C7
DVSS
M11
DVSS
T1
FLASH_ADDR1
C17
FLASH_DATA15
A7
DVSS
M12
DVSS
T2
FLASH_ADDR10
A15
FLASH_DATA2
B10
DVSS
M13
DVSS
T3
FLASH_ADDR11
E14
FLASH_DATA3
A10
DVSS
M15
DVSS
T4
D14
FLASH_DATA4
D9
DVSS
M16
DVSS
T5
FLASH_ADDR12/
PCIe_DIS
DVSS
T6
B14
E9
N3
FLASH_ADDR13
FLASH_DATA5
DVSS
BROADCOM
June 02, 2010 4706-DS00-R
Page 25
4/12/2011 DXKOG
BCM4706 Pin Tables
Signal
Ball
Signal
Ball
Signal
Ball
Signal
Ball
FLASH_DATA6
C9
INT_OVDD_33
E19
PCIe_SDVDD_1P2
M17
SGMII_VSS
Y16
FLASH_DATA7
A9
INT_OVDD_33
F5
PCIe_SDVDD_1P2
M19
SGMII_VSS
AB13
FLASH_DATA8
E8
INT_OVDD_33
F7
PCIe_SDVDD_1P2
P19
SGMII_VSS
AB15
FLASH_DATA9
D8
INT_OVDD_33
F9
PCIe_SDVDD_1P2
R21
SGMII_VSS
AB17
FLASH_OE_N
A18
INT_OVDD_33
F11
PCIe_SDVSS
K16
TDM0_BITCLK
J22
FLASH_WE_N
B18
INT_OVDD_33
F13
PCIe_SDVSS
K20
TDM0_SDIO
J21
GMAC_COL
W18
INT_OVDD_33
F15
PCIe_SDVSS
M20
TDM0_WS
H22
GMAC_CRS
V19
INT_OVDD_33
F17
PCIe_SDVSS
N17
TDM1_BITCLK
K22
GMAC_OVDD_25_33
U17
INT_OVDD_33
G18
PCIe_SDVSS
N18
TDM1_SDIO
J20
GMAC_OVDD_25_33
V17
JTCK
C5
PCIe_SDVSS
R22
TDM1_WS
H21
GMAC_RXCLK
AB20
JTDI
E5
PCIe0_RDN
L20
UART_RX
A19
GMAC_RXD0
AB22
JTDO
D5
PCIe0_RDP
L19
UART_TX
B19
GMAC_RXD1
AB21
JTMS
A5
PCIe0_RST_N
K21
USB_AVDD_2P5
R20
GMAC_RXD2
AA20
JTRST
A4
PCIe0_TDN
N20
USB_AVDD_3P3
U19
GMAC_RXD3
AA19
MDC
A20
PCIe0_TDP
N19
USB_AVSS
T21
GMAC_RXDV
W19
MDIO
B20
PCIe1_RDN
M22
USB_AVSS
U20
GMAC_RXER
Y19
MISC1_PLLAVDD_1P2
Y21
PCIe1_RDP
M21
USB_DATA_N
U22
GMAC_TXCLK
W17
MISC1_PLLAVSS
W20
PCIe1_RST_N
L22
USB_DATA_P
V22
GMAC_TXD0
AB18
MISC2_PLLAVDD_1P2
W21
PCIe1_TDN
P22
USB_DVDD_1P2
T19
GMAC_TXD1
W16
MISC2_PLLAVSS
V20
PCIe1_TDP
P21
USB_OCD
D20
GMAC_TXD2
AB19
NC
D17
RESET_N
D19
USB_PLLAVDD_1P2
V21
GMAC_TXD3
Y18
NC
E4
SFlash_CLK
D6
USB_RREF
T22
GMAC_TXEN
Y17
NC
H18
SFlash_SI
E6
XTAL_PLLAVDD_3P3
AA11
GMAC_TXER
AA18
NC
H19
SFlash_SO
A6
XTALI
AB12
GPIO0/SPI_SCLK
G22
NC
H20
SGMII_PLLAVDD_1P2
U13
XTALO
AA12
GPIO1/SPI_SS0
G21
NC
J19
SGMII_PLLAVDD_1P2
W12
GPIO10/FLASH_CS2_N C22
NC
T20
SGMII_PLLAVSS
Y12
GPIO11/FLASH_CS3_N C21
NC
U21
SGMII_PLLAVSS
AB11
GPIO12
B22
NC
V11
SGMII_RXDN
AB16
GPIO13
B21
NC
V13
SGMII_RXDP
AA16
GPIO14
A22
NC
W22
SGMII_TXDN
AA14
GPIO15
A21
NC
Y11
SGMII_TXDP
AB14
GPIO2/SPI_MOSI
F22
NC
Y22
SGMII_VDD_1P2
U14
GPIO3/SPI_MISO
G20
NC
AA22
SGMII_VDD_1P2
W13
GPIO4
G19
OSC_XTAL_SEL
E20
SGMII_VDD_1P2
W14
GPIO5
F19
PCIe_PLLVDD_1P2
P20
SGMII_VDD_1P2
W15
GPIO6/UART_RX2
E22
PCIe_PLLVSS
K18
SGMII_VDD_1P2
AA13
GPIO7/UART_TX2
F21
PCIe_REFCLKN
L18
SGMII_VDD_1P2
AA15
GPIO8/SPI_SS1
F20
PCIe_REFCLKOUTN
N21
SGMII_VDD_1P2
AA17
GPIO9/SPI_SS2
D21
PCIe_REFCLKOUTP
N22
SGMII_VSS
V14
INT_OVDD_33
C19
PCIe_REFCLKP
M18
SGMII_VSS
Y13
INT_OVDD_33
D18
PCIe_SDVDD_1P2
K19
SGMII_VSS
Y14
INT_OVDD_33
D22
PCIe_SDVDD_1P2
L21
SGMII_VSS
Y15
BROADCOM
June 02, 2010 4706-DS00-R
Page 26
4/12/2011 DXKOG
BCM4706 Ballmap
BCM4706 Ballmap
4
DDR_OVD DDR_SDR DDR_SDR

D_1P8
AM_DQ30 AM_DQ31
JTRST
JTMS
SFlash_SO
DDR_SDR
AM_DQ26
DVSS
DVSS
FLASH_CS
1_N
DVSS
DVSS
DVSS
DDR_SDR DDR_SDR
DDR_OVD
AM_DQSP AM_DQSN
D_1P8
3
3
DVSS
JTCK
DDR_SDR
AM_DQ28
DVSS
JTDO
DDR_SDR DDR_SDR DDR_SDR

AM_DQ22 AM_DQ23 AM_DQ27
NC
JTDI

AM_DQ24 AM_DQ25 AM_DM3
DVSS
INT_OVDD
_33
DVSS
INT_OVDD
_33
DVSS
DVSS
G
H
DVSS
DDR_SDR
AM_DQ29
DDR_OVD
DDR_OVD
DVSS
DVSS
D_1P8
D_1P8
DDR_SDR DDR_SDR
DDR_SDR
DVSS
AM_DQSP AM_DQSN
AM_DQ21
2
2
4/12/2011 DXKOG
DDR_SDR DDR_SDR DDR_OVD

AM_CK2P AM_CK2N
D_1P8
DDR_SDR DDR_SDR
AM_DQ20 AM_DQ16
DDR_SDR DDR_SDR
AM_DQ19 AM_DQ18

AM_DQ14 AM_DQ15
D_1P8
DDR_SDR DDR_SDR
AM_DQSP AM_DQSN
1
1
DVSS
DVSS
DVSS
DVSS
10
11
FLASH_DA
TA14
FLASH_DA
TA10
DVSS
DVSS
FLASH_DA
TA6
FLASH_DA
TA2
DVSS
DVSS
FLASH_AD
DR25/GMA
C_MODE
DVSS
INT_OVDD
_33
DVSS
DVSS
DVSS
DVSS
DDR_OVD
D_1P8
DVSS
CORE_DV
DD_1P2
DVSS
DVSS
INT_OVDD
_33
CORE_DV
DD_1P2
DVSS
DVSS
CORE_DV
DD_1P2
DVSS
DVSS
GPIO7/
GPIO8/SPI
GPIO2/SPI
UART_TX2
_SS1
_MOSI
GPIO3/SPI GPIO1/SPI GPIO0/SPI
_MISO
_SS0
_SCLK
DVSS
DVSS
DVSS
DVSS
DVSS
PCIe_REF
CLKN
DVSS
DVSS
DVSS
DVSS
CORE_DV
DD_1P2
DVSS
DVSS
PCIe_SDV PCIe_REF PCIe_SDV PCIe_SDV PCIe1_RD PCIe1_RD

DD_1P2
CLKP
DD_1P2
SS
P
N
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
PCIe_SDV PCIe_SDV
SS
SS
DVSS
DVSS
DVSS
DVSS
DVSS
CORE_DV
DD_1P2
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
USB_AVD
D_2P5
DVSS
CORE_DV
DD_1P2
DVSS
USB_DVD
D_1P2
NC
DVSS
USB_AVD
USB_AVSS
D_3P3
DVSS
GMAC_CR MISC2_PL USB_PLLA USB_DATA

S
LAVSS
VDD_1P2
_P
DVSS
DVSS
DDR_SDR DDR_SDR
AM_DQ11 AM_DQ10
DDR_SDR
AM_DM1
DVSS
DVSS
DVSS
CORE_DV
DD_1P2
DVSS
DVSS
CORE_DV
DD_1P2
DDR_OVD CORE_DV
D_1P8
DD_1P2
DVSS
DVSS
DVSS
DVSS
DDR_OVD
D_1P8
DDR_SDR
DDR_OVD
AM_ADDR
D_1P8
9
DDR_SDR DDR_SDR
AM_ADDR AM_ADDR
4
6
DDR_SDR
DVSS
AM_ADDR
7
DDR_SDR DDR_SDR
AM_ADDR AM_ADDR
11
8
DDR_SDR
AM_ADDR
12
DDR_SDR
AM_ADDR
10
DDR_SDR
AM_ADDR
14
DDR_SDR
AM_ADDR
13
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
GMAC_OV
DD_25_33
DVSS
GMAC_OV
DD_25_33
DVSS
TDM1_WS TDM0_WS
DVSS
DVSS
DVSS
NC
TDM1_SDI TDM0_SDI TDM0_BIT

O
O
CLK
DVSS
DVSS
AB
GPIO5
DVSS
DDR_SDR DDR_SDR DDR_OVD DDR_SDR

AM_DQ12
AM_DQ9
D_1P8
AM_DQ8
AA
DVSS
DVSS
INT_OVDD
_33
DVSS
CORE_DV
DD_1P2
DVSS
DVSS
DVSS
DVSS
INT_OVDD
_33
GPIO6/
UART_RX2
PCIe_PLLV PCIe_SDV PCIe_SDV PCIe0_RS

SS
T_N
SS
DD_1P2
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DDR_SDR
DDR_SDR DDR_SDR
AM_ADDR
DVSS
AM_CAS AM_CS_N
3
DDR_SDR
DDR_SDR DDR_SDR DDR_SDR DDR_OVD
DDR_SDR
DVSS
AM_ADDR
AM_DQ7
AM_DQ3
AM_DQ0
D_1P8
AM_BA1
0
DDR_SDR
DDR_SDR DDR_SDR DDR_SDR DDR_SDR DDR_SDR
DVSS
AM_ADDR
AM_DQ2
AM_DQ1
AM_DM0
AM_REF
AM_BA2
1
DDR_SDR DDR_SDR
DDR_SDR DDR_SDR DDR_SDR DDR_SDR DDR_SDR
AM_ADDR AM_ADDR
AM_CK0P AM_CK0N AM_ODT
AM_WE
AM_BA0
5
2
GPIO9/SPI INT_OVDD
_SS2
_33
PCIe_SDV
SS
DDR_SDR
AM_DQ13
DVSS
USB_OCD
DVSS
DVSS
DVSS
DVSS
DVSS
DDR_OVD
D_1P8

AM_DQ6
AM_DQ5
AM_DQ4
GPIO12
GPIO11/FL GPIO10/FL
ASH_CS3_ ASH_CS2_
N
N
CORE_DV
DD_1P2
DVSS
GPIO13
MDIO
DVSS
DVSS
DVSS
22
GPIO14
INT_OVDD OSC_XTAL
_33
_SEL
NC
DVSS
21
GPIO15
DVSS
NC
DVSS
20
MDC
FLASH_AD
FLASH_AD FLASH_AD
DR8/GMAC
DR3
DR0
_VSEL
DVSS
DVSS
DVSS
INT_OVDD
RESET_N
_33
DVSS
DVSS
DVSS
NC
DVSS
DVSS
DVSS
FLASH_AD FLASH_CS INT_OVDD

DR1
0_N
_33
DVSS
CORE_DV
DD_1P2
DVSS
FLASH_
ADDR11
UART_TX
DVSS
DVSS

AM_CKE
AM_RAS
D_1P8
FLASH_AD
FLASH_AD FLASH_AD
DR12/PCIe
DR7
DR4
_DIS
FLASH_W
E_N
GPIO4
CORE_DV
DD_1P2
DVSS
DVSS
DVSS
INT_OVDD
_33
DVSS
DVSS
FLASH_AD
DR9
FLASH_AD
DR5
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DDR_SDR
AM_DM2
DDR_OVD
D_1P8
DVSS
FLASH_AD
DR13
DVSS
DVSS
DVSS
FLASH_AD
DR17/BOO
T_FLASH_
TYPE
DVSS
DVSS
DVSS
FLASH_AD
DR21
CORE_DV
DD_1P2
DVSS
DVSS
19
CORE_DV
DD_1P2
DVSS
DVSS
18
DVSS
DVSS
DVSS
17
CORE_DV
DD_1P2
DVSS
DVSS
16
CORE_DV
DD_1P2
DVSS
DDR_SDR DDR_SDR
AM_DQSN AM_DQSP
0
0
15
INT_OVDD
_33
DVSS
14
DVSS
DVSS
DVSS
13
FLASH_AD
SFlash_CL FLASH_DA FLASH_DA FLASH_DA FLASH_DA DR23/RX_ FLASH_AD FLASH_AD
DR20
DR15
K
TA12
TA9
TA4
TA1
DELAY_M
ODE
FLASH_AD
FLASH_AD FLASH_AD
DR16/PCIe
FLASH_DA FLASH_DA FLASH_DA FLASH_DA
DR24/GMA DR19/MIPS
SFlash_SI
_REFCLKS
TA13
TA8
TA5
TA0
C_MODE
_ENDIAN
EL
DDR_SDR
AM_DQ17
DVSS
12
FLASH_AD FLASH_AD
FLASH_AD
FLASH_DA FLASH_DA FLASH_DA FLASH_DA FLASH_AD DR22/TX_ DR18/SFL FLASH_AD FLASH_AD DR6/MIPS_ FLASH_AD FLASH_OE
UART_RX
TA15
TA11
TA7
TA3
DR26
DELAY_M ASH_BOO
DR14
DR10
EJTAG_M
DR2
_N
ODE
T
ODE
NC
TDM1_BIT
CLK
PCIe0_RD PCIe0_RD PCIe_SDV PCIe1_RS

P
N
DD_1P2
T_N
PCIe0_TD
P
PCIe0_TD
N
PCIe_REF
CLKOUTN
PCIe_REF
CLKOUTP
PCIe_SDV PCIe_PLLV PCIe1_TD

DD_1P2
DD_1P2
P
PCIe1_TD
N
PCIe_SDV PCIe_SDV
DD_1P2
SS
USB_AVSS
USB_RRE
F
NC
USB_DATA
_N
DVSS
SGMII_PLL SGMII_VD
AVDD_1P2
D_1P2
DVSS
SGMII_VS
S
DVSS
DDR_SDR SGMII_PLL SGMII_VD

AM_ZQ
AVDD_1P2
D_1P2
SGMII_VD
D_1P2
SGMII_VD
D_1P2
SGMII_PLL SGMII_VS
AVSS
S
SGMII_VS
S
SGMII_VS
S
XTALO
SGMII_VD
D_1P2
SGMII_TX
DN
SGMII_VD
D_1P2
SGMII_RX
DP
SGMII_VD
D_1P2
GMAC_TX GMAC_RX GMAC_RX CORE_PLL

ER
D3
D2
AVDD_1P2
XTALI
SGMII_VS
S
SGMII_TX
DP
SGMII_VS
S
SGMII_RX
DN
SGMII_VS
S
GMAC_TX GMAC_TX GMAC_RX GMAC_RX GMAC_RX

D0
D2
CLK
D1
D0
DVSS
NC
NC
XTAL_PLL
AVDD_3P3
SGMII_PLL
AVSS
NC
DVSS
MISC2_PL
GMAC_TX GMAC_TX GMAC_CO GMAC_RX MISC1_PL
LAVDD_1P
D1
CLK
L
DV
LAVSS
2
MISC1_PL
SGMII_VS GMAC_TX GMAC_TX GMAC_RX CORE_PLL
LAVDD_1P
S
EN
D3
ER
AVSS
2
NC
NC
NC
Figure 3: BCM4706 BallmapTop View
BROADCOM
June 02, 2010 4706-DS00-R
Page 27
Electrical Characteristics
Section 3: Electrical Characteristics

Absolute Maximum Ratings
Table 4: Absolute Maximum Ratingsa
Parameter
Symbol
Min
Max
Units
3.3V Supply Voltage
INT_OVDD_33, GMAC_OVDD_25_33,
USB_AVDD_3P3, XTAL_PLLAVDD_3P3
GMAC_OVDD_25_33, USB_AVDD_2P5
CORE_DVDD_1P2, CORE_PLLAVDD_1P2,
MISC1_PLLAVDD_1P2, MISC2_PLLAVDD_1P2,
PCIe_PLLVDD_1P2, PCIe_SDVDD_1P2,
SGMII_PLLAVDD_1P2, SGMII_VDD_1P2,
USB_DVDD_1P2, USB_PLLAVDD_1P2
DDR_OVDD_1P8
TJ_MAX
0.5
+3.63
0.5
0.5
+2.75
+1.32
V
V
0.5
+1.98
+125
V
oC
TA
+70
oC
TA
40
+85
oC
TSTG
40
+85
+125
60
%
o
C
%
2.5V Supply Voltage

1.2V Supply Voltage
1.8V Supply Voltage

Maximum Junction
Temperature
Commercial Ambient
Temperature (Operating)
Industrial Ambient
Temperature (Operating)
Operating Humidity
Storage Temperature
Storage Humidity
a. These specifications indicate levels where permanent damage to the device may occur. Functional operation
is not guaranteed under these conditions. Operation at maximum conditions for extended periods may
adversely affect long-term reliability of the device.
BROADCOM
June 02, 2010 4706-DS00-R
Page 28
4/12/2011 DXKOG
Recommended Operating Conditions and DC Characteristics
Recommended Operating Conditions and DC Characteristics

Table 5: Recommended Operating Conditions
Symbol
Nominal
Limits
Units
CORE_DVDD_1P2
1.2V
5%
V
CORE_PLLAVDD_1P2
1.2V
5%
V
MISC1_PLLAVDD_1P2
1.2V
5%
V
MISC2_PLLAVDD_1P2
1.2V
5%
V
DDR_OVDD_1P8
1.8V
0.1
V
INT_OVDD_33
3.3V
5%
V
GMAC_OVDD_25_33
2.5V/3.3V
5%
V
PCIe_PLLVDD_1P2
1.2V
5%
V
PCIe_SDVDD_1P2
1.2V
5%
V
SGMII_PLLAVDD_1P2
1.2V
5%
V
SGMII_VDD_1P2
1.2V
5%
V
USB_DVDD_1P2
1.2V
5%
V
USB_PLLAVDD_1P2
1.2V
5%
V
USB_AVDD_2P5
2.5V
5%
V
USB_AVDD_3P3
3.3V
5%
V
XTAL_PLLAVDD_3P3
3.3V
5%
V
Note: See the BCM4706 Hardware Design Guide on docSAFE for more information on power supplies
decoupling.
Table 6: Total Power and Supply Current

Supply Voltage
BCM4706 Typical Value
Units
3.3V
2.5V
1.8V
1.2V
75
105
840
1670
mW
mW
mW
mW
Note: These power consumption numbers were derived under nominal conditions. For example, typical
corner silicon, nominal temperature (25C), and nominal voltages.
BROADCOM
June 02, 2010 4706-DS00-R
Page 29
4/12/2011 DXKOG
Core and I/O Power Sequencing Requirements
Core and I/O Power Sequencing Requirements

The BCM4706 device requires specific power sequencing between the core and I/O supplies.
The BCM4706 device power sequence requires I/O power (3.3V; 2.5V; 1.8V) to come up first, followed by
the core power (1.2V). The requirement is that the core power (1.2V) should not be on until the I/O power
(3.3V, 2.5V, 1.8V) reaches at least 1.0V.
When core power reaches nominal core voltage (1.2V 5%), the I/O power should be stable at nominal I/O
voltage (3.3V 5%, 2.5V 5%, or 1.8V 5%)
The maximum ramp-up time for core power 1.2V (from 0V to nominal voltage 5%) is 2 ms as shown in
figure below.
In addition, for successful power-up, Broadcom recommends that the external hardware reset be asserted for
at least 50 ms after both I/O and core power are stable as shown in Figure 4.
Figure 4: Power Supply Sequencing
BROADCOM
June 02, 2010 4706-DS00-R
Page 30
4/12/2011 DXKOG
DDR2 SDRAM Memory Interface DC Characteristics
DDR2 SDRAM Memory Interface DC Characteristics

Table 7: DC Characteristics for DDR2 SDRAM Interface
Parameter
Symbol Min
Max
Units
Conditions
SSTL Reference Voltage
VREF
DDR_OVDD_1P8
0.49
DDR_OVDD_1P8
0.51
VIHDC
VREF + 0.125
DC Input Low Voltage

AC Input High Voltage
AC Input Low Voltage
DC Output High Voltage
VILDC
VIHAC
VILAC
VOH
V
V
V
V
DC Output Low Voltage

DC Output Source Current
DC Output Sink Current
Output Impedance
Termination Impedance
VOL
IOH
IOL
ZOUT
ZTERM
0.3
VREF + 0.2
DDR_OVDD_1P8 0.35
9
9
36
54
108
DDR_OVDD_1P8 +
0.3
VREF 0.125
VREF 0.2
Typically derived
from
DDR_OVDD_1P8
2
DC Input High Voltage
0.35
44
66
132
V
mA
mA
Strong termination
Weak termination
USB Host Interface DC Characteristics

Table 8: USB Host Interface DC Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Conditions
VHSCM
-50
500
mV
VHSDI
300
mV
Static | VIDP VIDN |
VHSSQ
150
625
100
525
mV
mV
mV
mV
Squelch detected
No Squelch detected
Disconnect detected
Disconnect undetected
360
10
400
0
440
10
mV
mV
Static condition
Static condition
Receiver HS mode
Input Common Mode Voltage
Range
Differential Input Voltage
Sensitivity
Squelch Detection Threshold
(differential)
Disconnect Detection Threshold VHSDSC

(differential)
TransmitterHS mode
Output High Voltage
Output Low Voltage
VHSOH
VHSOL
BROADCOM
June 02, 2010 4706-DS00-R
Page 31
4/12/2011 DXKOG
USB Host Interface DC Characteristics
Table 8: USB Host Interface DC Characteristics (Cont.)

Parameter
Symbol
Min
Typ
Max
Units
Conditions
Output Impedance
RO
40.5
45
49.5
ohm
Single-ended
Chirp-J Output Voltage

(differential)
VCHIRPJ
1100
mV
700
HS Termination
disabled RPU
connected
Chirp-K Output Voltage
VCHIRPK
-900
-500
mV
HS Termination
(differential)
disabled RPU
connected
Note: See Section 7 of the USB 2.0 specification (www.usb.org) for more info on the Receiver Eye Diagram
Template.
Table 9: USB 1.1 Electrical and Timing Parameters

Value
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
VDI
VCM
Static |VIDP VIDN 200

|
0.8
mV
2.5
VFSOH
VFSOL
VCRS
Static condition
Static condition
2.8
0.0
1.3
3.6
0.3
2.0
V
V
V
RO
Single-ended
28
36
44
RPD
14.25
15.75
ZIN
300
ReceiverFS
Differential Input Sensitivity
(min)
Differential Common Mode
Range (max)
TransmitterFS
Output High Voltage
Output Low Voltage
Output Signal Crossover
Voltage
Output Impedance
Terminations
Bus Pull-down Resistor on
Host Port
Input Impedance
BROADCOM
June 02, 2010 4706-DS00-R
Page 32
4/12/2011 DXKOG
PCIe DC Characteristics
PCIe DC Characteristics
Table 10 shows PCIe DC characteristics.
Table 10: PCIe DC Characteristics
Parameter
Description
Min
Typ
Max
Units
Transmitter Output Impedance (differential)

Transmitter Output Voltage (differential peak to peak)
100
1200
mVP-P
Receiver Input Impedance (differential)

Receiver Input Voltage (differential peak to peak)
175
100
2000
mVP-P
Transmitter
ZOUT
VOD
Receiver
ZIN
VID
1G SGMII/SerDes Port Signals

Table 11 shows the 1G SGMII/SerDes port signals. These signals are AC coupled.
Table 11: 1G SGMII/SerDes Port Signals
Parameter
Description
Min
Typ
Max
Units
VID
RIN
VOD
Receiver Input Voltage, differential peak to peak, AC coupled

Receiver Input Impedance, differential, integrated on-chip
Transmitter Output Voltage, differential peak-to-peak,
programmable
Transmitter Output Impedance (differential)
100
80
100
700
2000
120
1100
mV
mV
80
100
120
RO
BROADCOM
June 02, 2010 4706-DS00-R
Page 33
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Standard 3.3V Signals

These specifications apply to all 3.3V signals, such as Flash, Serial Flash, MII, I8S/TDM, GPIO, MDC/MDIO, UART,
JTAG interfaces, and global clock/reset pins.
Table 12: Standard 3.3V Signals
Parameter
Description
Min
Typ
Max
Units
VIN
VIL
VIH
VOL
VOH
CI
Input voltage
Input low voltage
Input high voltage
Output low voltage
Output high voltage
I/O pin capacitance
0.3
2.0
2.4
3.6
0.8
0.4
10
V
V
V
V
V
pF

These specifications apply to the RGMII interface.
Table 13: Standard 2.5V Signals
Parameter
Description
Min
Typ
Max
Units
VIN
VIL
VIH
VOL
VOH
CI
Input voltage
Input low voltage
Input high voltage
Output low voltage
Output high voltage
I/O pin capacitance
0.3
1.7
2.0
2.75
0.8
0.4
10
V
V
V
V
V
pF
XTAL Oscillator Interface

Table 14: XTAL Oscillator Interface
Parameter
Symbol
Min
Max
Units
Input Low Voltage

Input High Voltage
XTALIL
XTALIH
0.3
2.0
+0.8
XTAL_PLLAVDD_3P3 + 0.5
V
V
BROADCOM
June 02, 2010 4706-DS00-R
Page 34
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Timing Characteristics
Section 4: T iming Characteristics

Reset and Clock Timing
t210
Voltage
Rails
t204
t201
t203
XTAL_IN
(25 MHz)
t202
t208
t207
RESET_N
t209
Configuration
Strap Signals
Valid
Figure 5: Reset and Clock Timing

Table 15: Reset and Clock Timing
Parameter Description
Minimum
Typical
Maximum
Units
t201
t202
t203
t204
t207
t208
t209
t210
50
0
8.5
50
25.0000
20
20
110
10
MHz
ns
ns
ms
s
s
s
ms
XTALI frequency
XTALI high time
XTALI low time
RESET_N low pulse duration
Configuration valid setup to RESET_N rising
Configuration valid hold from RESET_N rising
RESET_N deassertion to normal operation
Reset low hold time after power supplies
stabilize
BROADCOM
June 02, 2010 4706-DS00-R
Page 35
4/12/2011 DXKOG
Parallel Flash Timing

Parallel Flash READ Timing
FLASH_ADDR[26:0]
Address Valid
t3
t2
t1
FLASH_CS[1:0]_N
FLASH_OE_N
t0
FLASH_DATA[15:0]
Data Valid
Figure 6: Parallel Flash READ Timing Diagram

Table 16: Parallel Flash READ Timing
Parameter Descriptions
Min
Typ
Max
Units
Comments
Internal reference
clock
Internal reference
clock
Internal reference
clock
Internal reference
clock
WaitCount0+
1
WaitCount1+
1
WaitCount2+
1
WaitCount3+
1
t0
Output Enable Assertion Time
32
t1
Chip Select Inactive Time
32
t2
Chip Select Low to Output Enable Low 1
32
t3
Output Enable High to Chip Select

High
32
Note: Each timing parameter can be programmed individually through the corresponding WaitCount
field on the FlashWaitCnt register.
Note: The internal reference clock runs at 150 MHz.
BROADCOM
June 02, 2010 4706-DS00-R
Page 36
4/12/2011 DXKOG
Parallel Flash WRITE Timing

FLASH_ADDR[26:0]
Address Valid
t3
t2
t1
FLASH_CS[1:0]_N
FLASH_WE_N
t0
FLASH_DATA[15:0]
Data Valid
Figure 7: Parallel Flash WRITE Timing Diagram

Table 17: Parallel Flash WRITE Timing
Parameter
Descriptions
Min
Typ
Max
Units
t0
t1
t2
Output Enable Assertion Time

Chip Select Inactive Time
Chip Select Low to Write Enable
Low
Write Enable High to Chip Select
High
1
1
1
32
32
32
Internal reference clock WaitCount0 + 1

32
t3
Comments
Note: Each timing parameter can be programmed individually through the corresponding WaitCount
field on the FlashWaitCnt register.
Note: The internal reference clock runs at 150 MHz.
BROADCOM
June 02, 2010 4706-DS00-R
Page 37
4/12/2011 DXKOG
Serial Flash Timing (ST Micro-compatible Device)
Serial Flash Timing (ST Micro-compatible Device)

tp
SFlash_CLK
t1
Flash_CSx_N
t2
t3
SFlash_SI
t4
SFlash_SO
Figure 8: Serial Flash Timing Diagram
Table 18: Serial Flash Timing
Parameter
Descriptions
Min
Typ
Max
Units
fFREQ
tP
t1
SFlash_CLK frequency
Cycle time: SFlash_CLK period
Delay time: Flash_CSx_N low to SFlash_CLK rising
edge
Setup time: SFlash_SI valid to SFlash_CLK falling
edge
Hold time: SFlash_CLK falling edge to SFlash_SI
invalid
Output valid time: SFlash_SO valid to SFlash_CLK
rising edge
26.67/40
20
37.5
MHz
ns
ns
10
ns
ns
5.5
ns
t2
t3
t4
BROADCOM
June 02, 2010 4706-DS00-R
Page 38
4/12/2011 DXKOG
DDR2 SDRAM AC Timing Characteristics
DDR2 SDRAM AC Timing Characteristics

Table 19 shows the AC characteristics for the DDR SDRAM interface.
Table 19: AC Characteristics for DDR SDRAM Interface
Min
Typ
Max
Units
tCK(avg)
Average clock period (programmable) 3.33
ns
tCH(avg)
Average clock HIGH pulse width
0.48
0.5
0.52
tCK(avg)
tCL(avg)
Average clock LOW pulse width
0.48
0.5
0.52
tCK(avg)
tJIT(per)
tJIT(cc)
tJIT(duty)
tDQSS
125
250
125
250
125
250
125
250
ps
ps
ps
ps
tDQSH
Clock period jitter

Cycle to cycle clock period jitter
Duty cycle jitter
DQS latching rising transitions to
associated clock edges (for write, also
related to tDSS, tDSH)
DQS HIGH pulse width (for write)
0.35
0.5
tCK(avg)
tDQSL
DQS LOW pulse width (for write)
0.35
0.5
tCK(avg)
tWPRE
Write preamble, DQS driver turn-on to 0.35

the first DQS edge
Write postamble, DQS time to high-Z 0.4
after the last falling DQS edge
Delay from clock to address and control
signals, VDL adjustable (related to tIS,
tIH at DDR2 SDRAM)
Control and address output pulse width 0.6
tCK(avg)
tCK(avg)
0.25
tCK(avg)
tCK(avg)
0.25
tCK(avg)
0.35
tCK(avg)
400
ns
ns
ns
tWPST
tCK2AC
tIPW
tWDQ2DQS Delay from DQ or DM to DQS, VDL

adjustable (for write, related to tDS,
tDH at DDR2 SDRAM)
tDIPW
DQ and DM output pulse width (for
write)
tDQSCK
DQS delay from clock (for read)
tRDQDQSS DQ to DQS setup time (for read)
tRDQDQSH DQ hold time after DQS (for read)
400
0.2-tCK(avg)/4
tCK(avg)/4+0.2
BROADCOM
June 02, 2010 4706-DS00-R
Page 39
4/12/2011 DXKOG
USB Host Interface AC Timing Characteristics
USB Host Interface AC Timing Characteristics

Table 20: USB 2.0 Host Interfaces Timing Parameters
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Baud Rate
Units Interval
BPS
UI
480
2083
Mbps
ps
THSRX
0.15
0.15
UI
THSR
THSF
THSTX
500
500
0.05
0.05
ps
ps
UI
10% to 90%
90% to 10%
Receiver HS mode
Receiver Jitter Tolerance
TransmitterHS mode
Output Rise Time
Output Fall Time
TX Output Jitter
Table 21: USB 1.1 Timing Parameters

Value
Parameter
Symbol
Condition Min
Typ
12
83.33
To next
18.5
transition
RX Jitter Tolerance
TJR2
For paired 9
transitions
Output Rise Time
TFSR
10 to 90% 4
Output Fall Time

TFSF
10 to 90% 4
Note: For details, see the USB 1.1 Specification, Section 7.3.2, Tables 7-5 and 7-6.
Baud Rate
Units Interval
RX Jitter Tolerance
BPS
UI
TJR1
BROADCOM
June 02, 2010 4706-DS00-R
Max
Units
18.5
Mbps
ns
ns
ns
20
20
ns
ns
Page 40
4/12/2011 DXKOG
PCIe Interface Timing

PCIe_REFCLKP/N Timing
Figure 9 shows PCIe_REFCLKP/N timing.
PCIe_REFCLKP/N
TF
TJ
TR
T CYCLE
Figure 9: PCIe_REFCLKP/N Timing

Table 22: PCIe_REFCLKP/N Timing
Parameter
Descriptions
Min
Typ
Max
Units
FREQ
TOL
VID
tR/tF
tJ
Frequency (1/TCYCLE)
Tolerance
Differential peak-to-peak amplitude
Rise/Fall time
Max RMS (10 kHz to 50 MHz)
50
1.32
100
+50
1.70
1.0
4.7
MHz
ppm
VP-P
ns
ps
PCIe[1:0]_RDP/N Timing
Figure 10 shows PCIe[1:0]_RDP/N timing.
TJITTER
PCIe[1:0]_RDP/N
Figure 10: PCIe[1:0]_RDP/N Timing
BROADCOM
June 02, 2010 4706-DS00-R
Page 41
4/12/2011 DXKOG
Table 23: PCIe[1:0]_RDP/N Timing

Parameter
Descriptions
Min
Typ
Max
Units
FREQ
ZIN
VID
tJ
Baud rate
Input impedance (differential)
Differential peak-to-peak input voltage
Jitter tolerance (minimum RX EYE width)
175
0.4
2.5
100
2000
GBaud
mVP-P
UI
PCIe[1:0]_TDP/N Timing
Figure 11 shows PCIe[1:0]_TDP/N timing.
TJITTER
PCIe[1:0]_TDP/N
TR
TF
Figure 11: PCIe[1:0]_TDP/N Timing

Table 24: PCIe[1:0]_TDP/N Timing
Parameter
Descriptions
Min
Typ
Max
Units
FREQ
ZOUT
VOD
TR/TF
tJ
Baud rate
Output impedance (differential)
Differential peak-to-peak output voltage
Output rise/fall time (20% to 80%)
Output jitter (minimum TX EYE width)
0.125
0.7
2.5
100
1200
GBaud
mVP-P
UI
UI
BROADCOM
June 02, 2010 4706-DS00-R
Page 42
4/12/2011 DXKOG
MII Interface Timing

This section shows timing information for the MII Interface pins.
MII Input Timing

t402
t401
t403
t404
GMAC_RXCLK
GMAC_RXDV
GMAC_RXD[3:0]
Figure 12: MII Input Timing

Table 25: MII Input Timing
t401
t402
t403
t404
Min
GMAC_RXDV, GMAC_RXD[3:0] to GMAC_RXC rising setup

10
time
GMAC_RXC clock period (10BASE-T mode)
GMAC_RXC clock period (100BASE-TX mode)
GMAC_RXC high/low time (10BASE-T mode)

160
GMAC_RXC high/low time (100BASE-TX mode)
16
GMAC_RXDV, GMAC_RXD[3:0] to GMAC_RXC rising hold time 10
Duty cycle
40
BROADCOM
June 02, 2010 4706-DS00-R
Typ
Max
Units
ns
400
40
50
240
24
60
ns
ns
ns
ns
ns
%
Page 43
4/12/2011 DXKOG
MII Output Timing
GMAC_TXCLK
GMAC_TXEN
GMAC_TXD[3:0]
Figure 13: MII Output Timing

Table 26: MII Output Timing
Min
Typ
Max
Units
t405
t406
0
0
25
ns
ns
GMAC_TXC high to GMAC_TXEN, GMAC_TXD[3:0] valid

GMAC_TXC high to GMAC_TXEN, GMAC_TXD[3:0] invalid
(hold)
BROADCOM
June 02, 2010 4706-DS00-R
Page 44
4/12/2011 DXKOG
RGMII Interface Timing

The following specifies timing information for the GMAC interface pins when configured in RGMII mode.
RGMII Output Timing (Normal Mode)

RGMII output timing defaults to the normal mode when the FLASH_ADDR22/TX_DELAY_MODE pin is pulled
low at power-on reset.
GMAC_TXCLK
GMAC_TXD[3:0]
Figure 14: RGMII Output Timing (Normal Mode)

Table 27: RGMII Output Timing (Normal Mode)
Min
Typ
Max
GMAC_TXCLK clock period (1000M mode)

7.2
8.0 8.8

36
40
44

360
400 440
t201
Tskew: Data to clock output skew
500 (1000M)
+500 (1000M)
Duty cycle for 1000M (GE)

45
50
55
Duty cycle for 10/100M (FE)

40
50
60
Note: The output timing in 10/100M operation is always as specified in the delayed mode.
BROADCOM
June 02, 2010 4706-DS00-R
Units
ns
ns
ns
ps
%
%
Page 45
4/12/2011 DXKOG
RGMII Output Timing (Delayed Mode)

RGMII output timing is set to the delayed mode when the FLASH_ADDR22/TX_DELAY_MODE pin is pulled high
at power-on reset.
GMAC_TXCLK
(internal)
Delayed
GMAC_TXCLK
(actual output
at source)
GMAC_TXD[3:0]
Figure 15: RGMII Output Timing (Delayed Mode)

Table 28: RGMII Output Timing (Delayed Mode)
Min
Typ Max Units
t201D
7.2
36
360
1.2 (all speeds)
8.0 8.8
40 44
400 440
2.0
ns
ns
ns
ns
1.2
2.0
ns
45
40
50
50
55
60
%
%
t202D

Tsetup, data valid to clock transition:
Available setup time at the output source (delayed mode)
Thold, clock transition to data valid:
Available hold time at the output source (delayed mode)
BROADCOM
June 02, 2010 4706-DS00-R
Page 46
4/12/2011 DXKOG
RGMII Input Timing (Normal Mode)

RGMII Input Timing defaults to the delayed mode when the FLASH_ADDR23/RX_DELAY_MODE pin is pulled
low at power-on reset. The receive clock will not be delayed with 2 ns internally.
GMAC_RXCLK
(internal)
GMAC_RXCLK
(actual)
GMAC_RXD[3:0]
Figure 16: RGMII Input Timing (Normal Mode)

Table 29: RGMII Input Timing (Normal Mode)
Min Typ Max Units
t301
t302
7.2
36
360
1.0
1.0
45
40
GMAC_RXCLK clock period (1000M mode)

Tsetup, input setup time: valid data to clock
Thold, input hold time: clock to valid data
BROADCOM
June 02, 2010 4706-DS00-R
8.0
40
400
2.0
2.0
50
50
8.8
44
440
55
60
ns
ns
ns
ns
ns
%
%
Page 47
4/12/2011 DXKOG
RGMII Input Timing (Delayed Mode)

RGMII Input Timing is set to the delayed mode when the FLASH_ADDR23/RX_DELAY_MODE pin is pulled high
at power-on reset. The receive clock will be delayed with 2 ns internally.
GMAC_RXCLK
(internal)
Delayed
GMAC_RXCLK
(actual output
at destination)
GMAC_RXD[3:0]
Figure 17: RGMII Input Timing (Delayed Mode)

Table 30: RGMII Input Timing (Delayed Mode)
Min
Typ
Max
Units
t301D
t302D
-1.0 (10/100/1000M)
3.0 (1000M)
9.0 (10/100M)
ns
ns
ns
Tsetup, input setup time (delayed mode)

Thold, input hold time (delayed mode)
BROADCOM
June 02, 2010 4706-DS00-R
Page 48
4/12/2011 DXKOG
SGMII/SerDes Serial Interface

This subsection specifies timing information for the serial interface.
Serial Interface Output Timing

SGMII_TXDP
SGMII_TXDN
t805
t803
t802
Figure 18: Serial Interface Output Timing

Table 31: Serial Interface Output Timing
Min
Typ
Max
Units
t801
t802
t803
t804
t805
100
100
1.25
200
200
0.24
GBaud
ps
ps
ps
UI
Transmit Data Signaling Speed

Transmit Data Rise Time (20%-80%)
Transmit Data Fall Time (20%- 80%)
Transmit Data Output Differential Skew
Transmit Data Total Jitter
BROADCOM
June 02, 2010 4706-DS00-R
Page 49
4/12/2011 DXKOG
Serial Interface Input Timing

SGMII_RXDP
SGMII_RXDN
t808
Figure 19: Serial Interface Input Timing

Table 32: Serial Interface Input Timing
Min
Typ
Max
Units
t806
t808
1.25
0.6
GBaud
UI
Receive Data Signaling Speed

Receive Data Jitter (peak-to-peak)
BROADCOM
June 02, 2010 4706-DS00-R
Page 50
4/12/2011 DXKOG
I8S/TDM Audio/Video AC Specification
I8S/TDM Audio/Video AC Specification

Tperiod
TDM[1:0]_BITCLK
Thigh
Tlow
TDM[1:0]_WS or
TDM[1:0]_SDIO
T pd
Figure 20: IXS Transmitter Timing
Tperiod
TDM[1:0]_BITCLK
Thigh
Tlow
TDM[1:0]_WS or
TDM[1:0]_SDIO
T hold
Tsetup
Figure 21: IXS Receiver Timing

I
Table 33: IXS Receiver Timing

Parameter
Description
Min
Max Units Conditions
Tcyc
Tperiod
Thigh
Tlow
Tduty_cyc
Tpd
TDM[1:0]_BITCLK frequency
TDM[1:0]_BITCLK period
TDM[1:0]_BITCLK high
TDM[1:0]_BITCLK low
TDM[1:0]_BITCLK duty cycle
TDM[1:0]_BITCLK to TDM[1:0]_WS or TDM[1:0]_SDIO
delay
TDM[1:0]_WS or TDM[1:0]_SDIO setup time
TDM[1:0]_WS or TDM[1:0]_SDIO hold time
DC
13.33
5.33
5.33
40
75
8
8
60
3
MHz
ns
ns
ns
%
ns
Programmable
Output mode
2
2
ns
ns
Input mode
Input mode
Tsetup
Thold
BROADCOM
June 02, 2010 4706-DS00-R
Page 51
4/12/2011 DXKOG
JTAG Interface
JTAG Interface
JTAG timing is synchronous to the JTCK clock.
Figure 22: JTAG Interface

Table 34: JTAG Interface
Parameter
Description
Min
Typ
Max
Units
TCYCLE
TSU
TH
TOD
JTAG Cycle Time

Input Setup Time
Input Hold Time
Output Delay Time Measured from Falling Edge of JTCK
50
10
10
22
ns
ns
ns
ns
BROADCOM
June 02, 2010 4706-DS00-R
Page 52
4/12/2011 DXKOG
MDC/MDIO Master Interface
MDC/MDIO Master Interface

MDIO timing is synchronous to the MDC clock. The BCM4706 is an MDC/MDIO master device that drives the
MDC clock.
t1
MDC
t2
MDIO (out)
t3
t4
MDIO (in)
Figure 23: MDC/MDIO Master Interface
Table 35: MDC/MDIO Master Interface
Parameter
Description
Min
Typ
Max
Units
t1
t2
t3
t4
MDC cycle time, software programmable

MDIO output delay from MDC falling
MDIO input setup time to MDC rising
MDIO input hold time to MDC rising
40/60a
20
0
15
ns
ns
ns
ns
a. Six internal reference clock cycles, which is 40 ns.
BROADCOM
June 02, 2010 4706-DS00-R
Page 53
4/12/2011 DXKOG
SPI Master Interface

BCM4706 GPIO pins can be configured as SPI master interfaces to connect up to three SPI slaves. This supports
all four combinations of clock phase and polarity.
Timing Parameters for CPHA=0

tp
SCLK
(GPIO0)
CPHA=0
CPOL=0
CPOL=0
CPOL=1
CPOL=1
SS0/1/2
(GPIO1/8/9)
t2
t1
t3
MOSI
(GPIO2)
t4
t5
MISO
(GPIO3)
Figure 24: SPI Master Interface: Timing Parameters for CPHA=0
Table 36: SPI Master Interface
tp
t1
t2
t3
t4
t5
Min
SCLK period, software programmable

80
Minimum leading time before the first SCLK edge
Minimum trailing time after the last SCLK edge
MOSI output delay from SCLK clock falling/rising (CPOL=0/

1)
MISO input setup time to SCLK clock rising/falling (CPOL=0/ 10
1)
MISO input hold time to SCLK clock rising/falling (CPOL=0/1) 10
BROADCOM
June 02, 2010 4706-DS00-R
Typ
Max
Units
1.5
0.5
10
ns
ns
ns
tp
tp
ns
Page 54
4/12/2011 DXKOG
Timing Parameters for CPHA=1

tp
SCLK
(GPIO0)
CPHA=1
CPOL=0
CPOL=0
CPOL=1
CPOL=1
SS0/1/2
(GPIO1/8/9)
t2
t1
t3
MOSI
(GPIO2)
t4
t5
MISO
(GPIO3)
Figure 25: SPI Master Interface: Timing Parameters for CPHA=1
Table 37: Timing Parameters for CPHA=1
Parameter
Description
Min
Typ
Max
Units
tp
t1
t2
t3
SCLK period, software programmable

Minimum leading time before the first SCLK edge
Minimum trailing time after the last SCLK edge
MOSI output delay from SCLK clock rising/falling
(CPOL=0/1)
MISO input setup time to SCLK clock falling/rising
(CPOL=0/1)
MISO input hold time to SCLK clock falling/rising
(CPOL=0/1)
80
1
1
10
ns
10
ns
10
ns
t4
t5
BROADCOM
June 02, 2010 4706-DS00-R
tp
tp
ns
Page 55
4/12/2011 DXKOG
Thermal Specifications
Section 5: Thermal Specifications

This section describes the device thermal specifications. The maximum ThetaJA is a function of the maximum
ambient air temperature of the system.
BCM4706
This subsection describes BCM4706 device thermal specifications.
BCM4706 Thermal Specifications Without External Heatsink at 70C

Table 38 and Table 39 show the simulation and thermal performance data on the 2s2p board, without external
heatsink. The maximum ThetaJA is a function of the maximum ambient air temperature of the system.
TA = 70C, P = 2.7W from Simulation
Parameter
Value
Device power dissipation, P(W)

Ambient air temperature TA (C)
JA in still air (C/W)
JB (C/W)
JC (C/W)
2.70
70
21.43
9.80
8.81
Table 39: BCM4706 Thermal Specifications Without External Heatsink at 70C

Air Velocity
m/s
ft/min
TJ_max (C)
TT_ (C)
JA (C/W)
JT (C/W)
JB (C/W)
0
0.508
1.016
2.032
3.048
0
100
200
400
600
127.86
122.36
119.63
116.60
114.87
109.20
103.65
100.86
97.73
95.93
21.43
19.39
18.38
17.26
16.62
6.91
6.93
6.95
6.99
7.02
12.25
12.16
12.05
11.89
11.78
BROADCOM
June 02, 2010 4706-DS00-R
Page 56
4/12/2011 DXKOG
BCM4706
BCM4706 Thermal Specifications with External Heatsink at 70C

Table 40 and Table 41 show the simulation and thermal performance data with the 30x30x25 mm external
heatsink for the 2s2p board. The maximum ThetaJA is a function of the maximum ambient air temperature of
the system.
Parameter
Value

JB (C/W)
JC (C/W)
2.70
70
15.33
9.80
8.81
Table 41: BCM4706 Thermal Specifications with 30x30x25 mm External Heatsink at 70C
Air Velocity
m/s
ft/min
TJ_max (C)
TT_ (C)
JA (C/W)
JT (C/W)
JB (C/W)
0
0.508
1.016
2.032
3.048
0
100
200
400
600
111.39
101.31
99.42
98.31
97.81
90.63
79.98
77.98
76.83
76.32
15.33
11.59
10.90
10.48
10.30
7.69
7.90
7.94
7.96
7.96
9.77
9.08
8.94
8.87
8.85
BROADCOM
June 02, 2010 4706-DS00-R
Page 57
4/12/2011 DXKOG
BCM4706
BCM4706 Thermal Specifications Without External Heatsink at 85C

Table 42 and Table 43 show the simulation and thermal performance data on the 2s2p board, without external
heatsink. The maximum ThetaJA is a function of the maximum ambient air temperature of the system.
TA = 85 C, P = 2.7 W from Simulation
Parameter
Value

JB (C/W)
JC (C/W)
2.70
85
21.43
9.80
8.81
Table 43: BCM4706 Thermal Specifications Without External Heatsink at 85C

Air Velocity
m/s
ft/min
TJ_max (C)
TT_ (C)
JA (C/W)
JT (C/W)
JB (C/W)
0
0.508
1.016
2.032
3.048
0
100
200
400
600
142.86
137.36
134.63
131.60
129.87
124.20
118.65
115.86
112.73
110.93
21.43
19.39
18.38
17.26
16.62
6.91
6.93
6.95
6.99
7.02
12.25
12.16
12.05
11.89
11.78
BROADCOM
June 02, 2010 4706-DS00-R
Page 58
4/12/2011 DXKOG
BCM4706
BCM4706 Thermal Specifications with External Heatsink at 85C

Table 44 and Table 45 show the simulation and thermal performance data with the 30x30x25 mm external
heatsink for the 2s2p board. The maximum ThetaJA is a function of the maximum ambient air temperature of
the system.
Parameter
Value

JB (C/W)
JC (C/W)
2.70
85
15.33
9.80
8.81
Table 45: BCM4706 Thermal Specifications with 30x30x25 mm External Heatsink at 85C
Air Velocity
m/s
ft/min
TJ_max (C)
TT_ (C)
JA (C/W)
JT (C/W)
JB (C/W)
0
0.508
1.016
2.032
3.048
0
100
200
400
600
126.39
116.31
114.42
113.31
112.81
105.63
94.98
92.98
91.83
91.32
15.33
11.59
10.90
10.48
10.30
7.69
7.90
7.94
7.96
7.96
9.77
9.08
8.94
8.87
8.85
BROADCOM
June 02, 2010 4706-DS00-R
Page 59
4/12/2011 DXKOG
Mechanical Information
Section 6: Mechanical Information

BCM4706
Figure 26: BCM4706 Mechanical Information
BROADCOM
June 02, 2010 4706-DS00-R
Page 60
4/12/2011 DXKOG
Ordering Information
Section 7: Ordering Information

Table 46: Ordering Information
Part Number
Package
Ambient Temperature
BCM4706KPBG
23 mm x 23 mm 484-pin PBGA (Lead-free)
0 to 70C
BROADCOM
June 02, 2010 4706-DS00-R
Page 61
4/12/2011 DXKOG
Broadcom Corporation reserves the right to make changes without further notice to any products
or data herein to improve reliability, function, or design.
Information furnished by Broadcom Corporation is believed to be accurate and reliable. However,
Broadcom Corporation does not assume any liability arising out of the application or use of this
information, nor the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
BROADCOM CORPORATION
5300 California Avenue

Irvine, CA 92617
2010 by BROADCOM CORPORATION. All rights reserved.
4706-DS00-R
June 02, 2010

4/12/2011 DXKOG
Phone: 949-926-5000
Fax: 949-926-5203
E-mail: info@broadcom.com
Web: www.broadcom.com

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Advance Data Sheet

The Broadcom BCM4706 processor is a

Advanced MIPS32 74K Core

At the center of the device is a high-performance

CPU Local Bus

Figure 1: Functional Block Diagram

June 02, 2010

BCM4706 Advance Data Sheet

Section 2: Hardware Signal Descriptions.......................................................................... 15

Section 3: Electrical Characteristics.................................................................................. 28

BCM4706 Advance Data Sheet

XTAL Oscillator Interface..............................................................................................................................34

Section 4: Timing Characteristics ..................................................................................... 35

Section 5: Thermal Specifications .................................................................................... 56

Section 6: Mechanical Information.................................................................................. 60

BCM4706 Advance Data Sheet

Section 7: Ordering Information ...................................................................................... 61

BCM4706 Advance Data Sheet

BCM4706 Advance Data Sheet

BCM4706 Advance Data Sheet

Table 36: SPI Master Interface .........................................................................................................................54

BCM4706 Advance Data Sheet

Section 1: Functional Description

Crystal Oscillator and Clock Generator

BCM4706 Advance Data Sheet

DDR2 SDRAM Interface

DDR2 SDRAM Interface

USB 2.0 Host Controllers

PCI Express Interface

BCM4706 Advance Data Sheet

PCI Express Interface

Figure 2: PCI Express Layer Model

Transaction Layer Interface

Data Link Layer

BCM4706 Advance Data Sheet

PCI Express Interface

BCM4706 Advance Data Sheet

10/100/1000 Ethernet MAC Controller

10/100/1000 Ethernet MAC Controller

BCM4706 Advance Data Sheet

Two parallel Flash

BCM4706 Advance Data Sheet

Hardware Signal Descriptions

Section 2: Hardware Signal Descriptions

DDR SDRAM Interface

DDR2 address bus

BCM4706 Advance Data Sheet

Hardware Signal Descriptions

Table 1: Hardware Signals (Cont.)

Parallel Flash Interface/Strap Pins

BCM4706 Advance Data Sheet

Hardware Signal Descriptions

Table 1: Hardware Signals (Cont.)

Ethernet Interface (RGMII/MII)

BCM4706 Advance Data Sheet

Hardware Signal Descriptions

Table 1: Hardware Signals (Cont.)

GPIO/SPI/UART Interfaces (internal PU/PD of GPIOs is user-configurable through register setting)

BCM4706 Advance Data Sheet

Hardware Signal Descriptions

Table 1: Hardware Signals (Cont.)

Positive leg of the differential pair transmit serial data on PCIe

Clock output for serial Flash