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The basics of SerDes (serializers/deserializers)

for interfacing
Atul Patel, Business Development Manager, Texas Instruments
9/16/2010 11:51 AM EDT
Atul Patel, Business Development Manager, Texas Instruments
Understand the concept and implementation of this increasingly common interconnection format
What is SerDes?
SerDes (serializers/deserializers) are devices that can take wide bit-width, single-ended signal buses and compress them to a
few, typically one, differential signal that switches at a much higher frequency rate than the wide single-ended data bus.
SerDes enable the movement of a large amount of data point-to-point while reducing the complexity, cost, power, and board
space usage associated with having to implement wide parallel data buses. SerDes usage becomes especially beneficial as the
frequency rate of parallel data buses moves beyond 500 MHz (1000 Mbps).
At these higher-frequency rates, the problems associated with wide parallel buses are further exacerbated. A faster-switching
parallel bus consumes more power and is much more difficult to route, given that timing tolerances are reduced.
For example, system designers often have a very difficult time maintaining comparable skew between the individual.
parallel-signal lines. Large skew mismatches can lead to system-timing issues at the receiver as many systems need to clock
in the parallel data as a group of aligned bits.
Many other problems arise for parallel data-bus implementations as frequency and transmission distance increase. Issues such
as signal integrity, power usage, and timing can all have a significant impact on a design. In todays compact systems, simply
using many slower parallel channels to transport more data is not an acceptable answer as board space is often limited
(Figure 1). In many applications, a SerDes can provide a very good solution for moving a large amount of data point-to-point
within systems, between systems, or even between systems in two different locations.

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Figure 1: Single-ended parallel-bus implementation versus SerDes-based data transmission.

(Click on image to enlarge)
Basic operation of a SerDes
The basic operation of a SerDes is relatively simple. The following is meant to be a high-level description of signal flow in a
SerDes device (Figure 2). (Specific implementations can vary from vendor to vendor, of course.) A parallel data bus,
switching at a given frequency, is fed into the parallel input bus of the SerDes device. These bits are clocked into the parallel
bit registers of the SerDes, based on the falling or rising edge of the reference clock provided, with the parallel data from the
source of the parallel data such as a media access controller (MAC) or system processor.
Often the clock can be provided by a related reference source, such as a crystal oscillator or clock generator IC that is
providing the reference clock to the system. Once the parallel data registers are loaded, the bits are typically encoded
(translated) using standard coding schemes such as 8Bit-10Bit (8B/10B) encoding.
The SerDes encoder/decoder (ENDEC) serves multiple functions. The most important is to shape the incoming application
data stream to make it suitable for serialization. For example, raw application data streams can have "pathological cases"
such as when the data stream is a long, continuous run of 0 bits (0000000) or a continuous run of 1 bits (1111111.).
In these cases, the SerDes has a very difficult time catching a bit transition after a long stream of consecutive identical bits.
The clock and data recovery (CDR) circuit in the SerDes needs to see some level of bit-transition density in the data stream in
order to avoid missed bits. By encoding data, the incoming parallel data word (pre-defined number of parallel data bits) are
encoded--that is, mapped--to a defined (standardized) bit pattern (word) that tends to be more suitable for serialization. For
example, with 8B/10B coding, the coding set maps to words that have a similar number of ones and zeros to provide a DCbalanced data stream.
Another issue with un-encoded data is that word delineation (word boundary points) is lost in the serialization process. In
order to aid the receiver, the ENDEC provides special code words that signify word boundaries. The receiver can use these
special codes to perform byte delineation. For example, the 8B/10B coding scheme has the concept of a comma code that an
application can use to establish initial word boundaries in the data stream.
The coded data bit bus is then serialized, and turned from a parallel bit bus to a serial bit bus. The serialization function of a
SerDes takes a parallel set of bits (data word) and serializes them for efficient transmission over a single differential
transmission channel. Often, serialization is implemented using shift registers as shown in Figure 2. Note that the data needs
to be clocked into the parallel registers based the byte clock.

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Figure 2: The serialization process.

(Click on image to enlarge)
The serialized bit bus is then fed into a differential line driver, also known as differential signal buffer. The signal buffer
drives the serialized bit stream out on to media such as copper cable or backplane trace.
On the SerDes receive side, the serialized bit stream is fed into the differential signal input buffer. The input buffer within
the SerDes receive circuitry resolves the incoming bits (represented by voltage swings) into a digital bit stream.
Another key function of the receiver is to perform clock recovery on the incoming serial data stream. The clock-recovery
circuit extracts a bit rate clock from the serial data stream being input into the receiver. This recovered clock is then used to
clock the received bit stream. The received bit stream is then de-serialized.
De-serialization is the process whereby the serial receive data is assembled back into parallel words that then can be decoded
to form the original data word. The de-serialization process depends on the clock/data recovery (CDR) circuit providing a
recovered clock to help drive the timing of the shift registers being used to reassemble the parallel coded data word.
The de-serialized (parallel) bit stream is decoded back to its original data bits. The data bits are then fed into parallel output
registers and clocked out by the parallel output signal buffers. Typically, output buffers are single-ended signal buffers. A
divided-down recovered clock is also provided with the parallel data. The clock is frequency-aligned to the data rate of the
incoming serial bit stream. Often, the transmit and receive paths for a SerDes work in tandem at the same frequency to form a
full duplex, transmit and receive at the same time, serial link.
The phase-locked loop (PLL)
The phase-locked loop is an important part of any SerDes device, as it produces the high-speed clock used to drive the serial
transmitter as well as receive path of the device. Depending on SerDes architecture, a SerDes can have one PLL for both the
transmit and receive paths, or the SerDes can have two PLLs: one for transmit and another for receive.
The PLL is a key block of the CDR circuit, and is driven by the reference clock input. Therefore, reference-clock inputs are
often specified to meet tight electrical and jitter requirements as a poor reference clock can have a dramatic impact on the
SerDes performance.The recovered clock is typically divided down to produce a word (byte) clock that is provided by the
SerDes with the parallel output data .
The importance of the reference clock
The reference clock is an input clock provided to a SerDes to drive the PLL(s) in the SerDes. The reference clock often has a
specific relationship to the serial data rate at which the SerDes needs to operate. For example, SerDes devices with 10-bit
parallel interfaces may use a 125-MHz reference clock in order for the SerDes to operate at serial rate of 1.25 Gbps. In this
case, the internal SerDes PLL is most likely providing a 10-times multiplier to the reference clock in order to achieve a bit
rate of 1.25 Gbps, assuming the clock is being sampled rising edge to rising edge.
s mentioned earlier, reference-clock quality is a key factor in the operation of a SerDes. If the reference clock has a lot of
jitter, then the serial data stream is likely to have higher jitter content. If the reference clock is not stable and exhibits wander,
then the serial data stream may exhibit similar characteristics. Since the reference clock is very important to the SerDes
function, the reference clock specification in the device data sheet tends to be very stringent for factors such as jitter, PPM
offset, and rise/fall times.

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Reference-clock requirements and frequency range supported vary from vendor to vendor, often following industry-standard
conventions. For example, SerDes solutions from Texas Instruments, such as the TLK1501, TLK3131, TLK3134 and
TLK6002, support fairly wide input-frequency ranges, and thereby support wide data ranges covering applications such as
Gigabit Ethernet, fiber channel, 10G Ethernet, common platform radio interface (CPRI) and other standards.
As rich media-based applications become more prevalent, using SerDes devices either as standalone or integrated into higher
level functions are becoming more common. SerDes devices provide a host of advantages for moving large amounts of data
within an application while enabling systems designers to meet power, usability, performance, and cost targets. Today's
SerDes ICs are highly integrated devices optimized for the specific application niche they target, Figure 3.

Figure 3: High-level SerDes IC block diagram.

(Click on image to enlarge)
Key SerDes data sheet specifications explained
Unit interval: In reference to SerDes, unit interval refers to the amount of time allocated for one bit for a given data rate of
operation. For example, at 1.25 Gb/s, the unit interval is 800 ps (1/1,250,000,000).
Jitter: Simply the deviation from the ideal pulse of a signal. For SerDes, jitter in reference to the clock input as well as serial
data streams are important specifications that impact the overall performance of the SerDes.
Reference clock jitter: The maximum amount of jitter that the input reference clock can contain and still preserve serial link
quality. Reference clock jitter is often specified as a peak-peak or RMS number, in time units such as picoseconds. In some
cases, reference clock jitter is given as phase noise over a frequency band.
Setup and hold times: Setup time is the amount of time that data on the parallel data bus must be stable before it can be
clocked into the parallel register. Hold time is the amount of time that the data must remain valid after being clocked into the
parallel register. Set/hold time violations are a common cause of implementation issues for SerDes.
Rise and fall times: Commonly referred to as the signal edge rate. Rise and fall times are commonly specified for the serial
I/O as a measure of serial switching performance. A rule of thumb is that the rise or fall time should be no greater than 25 to
30 percent of the unit interval for a given data rate of operation.
Power: Power is specified in watts or milliwatts and tends to scale (not necessarily linearly) with data rate.
Consecutive identical digits (CID): For SerDes, this specification provides a guide to how many consecutive identical ones
(111111) or zeros (00000) the SerDes is capable of receiving before the possibility of a missed transition becomes
highly likely. Certain communication standards such as SONET require a SerDes to meet specific minimum CID (run length)

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requirements.
References
Additional information is available about these SerDes-related ICs:
l TLK1501: www.ti.com/tlk1501-ca
l TLK3131: www.ti.com/tlk3131-ca
l TLK3134: www.ti.com/tlk3134-ca
l TLK6002: www.ti.com/tlk6002-ca
About the Author
Atul Patel is new business development manager for Gigabit SerDes products within the Communication Interface Products
Group at Texas Instruments. Atul has a Bachelor of Science in Computer Engineering as well as an MBA from the
University of Central Florida.

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