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Aims

Familiarize students with combinational and sequential digital logic circuits, the analogue-digital

interface, and the hardware and basic operation

of microprocessors, memory and the associated

electronic circuits which are required to build microprocessor based systems.

Information Processing

Handout 1

Combinational Logic

Richard Prager

Tim Flack

January 2009

1

of digital and microprocessor-based systems, give

students the ability to design simple systems of

this kind, and understand microprocessor operation at the assembly-code level.

Contents of Handout 1

Section A

This section covers the material

for questions 1 and 2 on

examples paper 1.

Section B

This section covers the material

for questions 3 6 on

examples paper 1.

Section C

Introduction to VHDL.

This section covers the material

for questions 7 11 on

examples paper 1.

Section D

This section covers the material

for questions 1 5 on

examples paper 2.

3

Logic Variables

Logic variables

Handout 1 Section A

Binary variables

Boolean variables

All names for the same thing.

In this section we introduce Boolean algebra and logic

gates.

TRUE or FALSE

1 or 0

In electronic circuits the two states of a logic variable

are represented by two voltage levels. For example, a

high voltage for 1 and a low voltage for 0.

5

Washing Machine

Heating Boiler

If drum not turning and no water in drum and program finished then permit door to be

opened.

house is cold and pilot light lit

then open main fuel valve to

start up boiler.

T

W

P

L

B = chimney blocked

=

=

=

=

drum turning

water in drum

program active

door unlocked

C = house is cold

P = pilot alight

V

We can write this using bars above the symbols to

denote NOT.

L = T AND W AND P

7

Logic Gates

Electronic circuits that have logic signals as their inputs and outputs are known as LOGIC CIRCUITS or

DIGITAL CIRCUITS.

NOT Gate

output, are also known as GATES.

GATES are used as building blocks in the design of

more complex logic circuits.

There are several ways of representing logic functions:

Graphical

Symbol

Input-output

Map

0

1

1

0

Boolean

representation

Y =A

A circle on the output of a gate always implies that it

is an inverting output.

Input-output maps.

Boolean algebra.

9

10

OR Gate

AND Gate

Graphical

Symbol

Input-output

Map

A

B

Graphical

Symbol

Boolean

representation

Input-output

Map

B 0

0 0

1

0

1 0

Y = A.B

In Boolean algebra AND is represented by a dot .

11

A

B

0

0 0

1

1

1 1

Boolean

representation

Y =A+B

In Boolean algebra OR is represented

by a plus sign +

12

EXCLUSIVE OR Gate

Graphical

Symbol

Input-output

Map

A

B

B 0

0 0

1

1

1 1

NAND Gate

Boolean

representation

Graphical

Symbol

Input-output

Map

Y =AB

A

B

0

0 1

1

1

1 1

Boolean

representation

Y = A.B

13

14

Boiler Example

NOR Gate

lit then open main fuel valve to start up boiler.

B = chimney blocked

Graphical

Symbol

Input-output

Map

A

B

B 0

0 1

1

0

1 0

Boolean

representation

C = house is cold

P = pilot alight

V

V = B.C.P

Y =A+B

Y is FALSE if A is TRUE or B is TRUE (or both).

B

C

P

15

16

Handout 1 Section B

If drum not turning and no water in drum and program

finished then permit door to be opened.

T = drum turning

W = water in drum

P = program active

graphical technique for analyzing non-linear circuits.

L = door unlocked

field effect transistor is described.

L = T .W .P

and OR gates, and estimate the speed of NMOS circuits.

T

W

L

A discussion of the power consumption of NMOS gates

leads to the introduction of the CMOS inverter circuit.

P

17

18

Implementing Logic Gates

A high voltage represents logic 1.

A zero voltage represents logic 0.

when we introduce non-linear components.

10v

1

x

2

0v

in

Inverter

circuit

Vout

Current

through

1 ohm

Current

through

2 ohm

V+

ic

rist istor

e

t

c res

ara

Ch ohm

of 2

out

linear.

0v

0v

V+

V

in

19

tic

ris

te

ac

ar hm

Ch 1 o

of

ideal characteristic for

an inverter circuit.

1 ohm

20

10v

1

x

Thing

x

1

0v

Current

through

Thing

Current

through

1 ohm

C

of hara

1 ct

oh er

m ist

tic

ris

te

ac

ar hm

Ch 1 o

of

0v Voltage across

Thing

Thing

0v

Current

through

1 ohm

Characteristic

of Thing

The characteristic of

I

the upper component is

drawn backwards along

the V axis, starting at

the supply voltage.

10v

Current

through

Thing

Thing

characteristic

ic

Thing

Suppose we now recharacteristic

place the lower resistor

I

with a non-linear component (that we will call

a Thing).

1 ohm

0v

21

Voltage across

1 ohm

Characteristic

of Thing

x

Voltage across

Thing

10v

22

N-channel MOSFET

OFF

Drain +VD

Gate

111

000

n+

000

111

0v

Source 0v

111

000

n+

000

111

Reverse biased

p-n junction

p-type

substrate

Enhancement mode: means off when VGS = 0. The

alternative is a depletion mode transistor which is on

(i.e. conducts from drain to source) when VGS = 0.

G

ON

Drain +VD

Gate

+VG

Source 0v

111

000

000

111

n+

00

11

000

111

00

11

00

11

00

11

000

111

00

11

000

111

n+

000

111

N-type layer:

inversion

p-type

substrate

23

24

NMOS Inverter

NMOSFET Characteristics

IDS 12

mA 10

8

6

4

2

0

VGS = 10v

VGS = 8v

VGS = 6v

10

8

VDS Volts

NMOS FET and a 1k resistor.

VDD = 10v

1k

VGS = 4v

VGS = 2v

VGS = 0v

Vout

Vin

VGS

IDS as a function of

VGS at constant VDS

when VGS reaches the

Threshold voltage: VT

VDS

0v

IDS

mA

IDS 12

mA 10

8

6

4

2

0

3

VT

VGS

6

Volts

VGS = 10v

VGS = 8v

VGS = 6v

8

10

VDS Volts

NMOS FET

Characteristic

25

VGS = 4v

VGS = 2v

VGS = 0v

I 12

mA 10

8

6

4

2

0

6

V

8

10

Volts

Resistor

Characteristic

26

IDS 12

mA 10

8

6

4

2

0

VGS = 10v

Voltage Levels

VGS = 8v

VGS = 6v

8

10

VDS Volts

VGS = 4v

VGS = 2v

VGS = 0v

from the ideal we originally

wanted.

10

Vout

8

6

4

2

0

However if we say:

10

Vin

Vout

8

voltage > 9v

voltage < 2v

6

4

is logic 1

is logic 0

2

0

Vin

Vin > 9v

Vin < 2v

10

27

Vout < 2v

Vout > 9v

28

10

VDD

VDD

R

R

VY

VA

VY

VB

VA

0v

Think of the transistors as switches. When VGS is

high they conduct. Otherwise they dont conduct.

A

low

B

low

Y

high

high

low

low

high

low

low

high

high

VB

0v

A

low

high

low

B

Y

low high

low high

high high

high

high

low

low

29

30

When we have a complicated logic function to implement, (eg. the boiler example previously discussed

V = B.C.P ), you dont have to design a special transistor circuit to provide the functionality.

is due to stray capacitance. The output of each gate is

connected by a length of metal track to the input of the

next. This has capacitance to ground. We therefore

modify the circuit model.

provides the appropriate gates.

VDD = 10v

IR

R = 1k

Vout

ID

IC

AND gate and an inverter.

31

Vin

0v

32

A big advantage of chips is that they are small.

Implementing a resistor on a chip takes up a lot of

space on the silicon.

IR = IC

VDD Vout

dVout

= C

R

dt

(almost) like a resistor by connecting the Gate to the

Drain. Thus VGS = VDS .

So

IDS 12

mA 10

8

6

4

2

0

Vout

V

dVout

+

= DD

dt

RC

RC

t

Vout = VDD + (1 VDD ) exp

RC

a time of 3RC.

33

VGS = 10v

VGS = 8v

VGS = 6v

8

10

VDS Volts

VGS = 4v

VGS = 2v

VGS = 0v

the exactly same as a resistor. However, its roughly

like 900.

34

Power Consumption

Smaller NMOS Inverter

10

VDD = 10v

a revised design for an inverter circuit that is easier to

miniaturize.

VDD = 10v

6

Vout

4

2

0v

Vin

10

is therefore no power dissipated.

Vout

through the resistor and heat will be generated.

switch

Vin

1k

Vin

pseudo-resistor (load)

Vout

ID = 9mA so 81mW will be dissipated in the resistor

and 9mW will be dissipated in the FET.

0v

35

36

Complementary MOS

CMOS Inverter

The problem with NMOS logic is power dissipation in

the resistors. To solve this, CMOS logic was invented.

This uses both NMOSFETS and PMOSFETS.

VSS = 10v

polarities reversed:

IDS -12

mA -10

-8

-6

-4

-2

0

VGS = -10v

S

G

PMOS

D

D

Vin

VGS = -8v

NMOS

G

VGS = -6v

-2

-4

-6

-8 -10

VDS Volts

VGS = -4v

VGS = -2v

VGS = 0v

0v

Vin

low

high

G

S

Vout

NMOS PMOS

off

on

on

off

Vout

high

low

D

37

38

PMOS

NMOS Characteristic

IDS 12

mA 10

8

6

4

2

0

VGS = 10v

VGS = 8v

VGS = 6v

10

8

VDS Volts

VGS = 4v

VGS = 2v

VGS = 0v

PMOS Characteristic

IDS -12

mA -10

-8

-6

-4

-2

0

VGS = -10v

VGS = -8v

VGS = -6v

-2

-4

-6

-8 -10

VDS Volts

VGS = -4v

VGS = -2v

VGS = 0v

PMOS

VGS = -10v

12

I 10

mA 8

6

4

2

0

VGS = -6v

12

I 10

mA 8

6

4

2

0

Intersection of curves

NMOS

VGS = 4v

0

10

Voltage across

PMOS

NMOS

Intersection of curves

VGS = 0v

10

12

10

Intersection of curves

I

8

mA

6

4

2

0

0

2

4

6

8

NMOS

VGS = 6v

PMOS

VGS = -4v

10

Voltage across

NMOS

(a)

Vin = 0v Vout = 10v. No current flows.

39

40

12

I 10

mA 8

6

4

2

PMOS

VGS = 0v

NMOS

Intersection of curves

VGS = 10v

10

(d)

Vin = 10v Vout = 0v. No current flows.

I /mA

Power /mW

0

2

4

5

6

8

10

0.0

1.0

2.7

3.6

2.7

1.0

0.0

0

10

27

36

27

10

0

40

only flows when the

Power

gate is changing

30

state. This means mW

that power is only

20

dissipated as the

10

gate switches on or

off.

10

can construct the input- Vout

8

output characteristic of

the inverter circuit. Note

6

that the CMOS inverter

4

is much closer to our

2

ideal than the NMOS

inverter was.

0

Vin

Vin

41

10

Vin

42

10

Logic Families

VSS = 10v

NMOS Compact, slowish, cheap.

T2

T1

VB

VA

1240 MHz for gates in individual packages. Power

consumption < 106 W/gate when not changing,

and about 104 W/gate when changing at 100

kHz.

VY

T3

TTL Constructed from bipolar transistors. Propagation delay 1.510 nS, max clock frequency 35

200 MHz. Power consumption is about 102 W/gate.

T4

0v

VA

low

low

high

high

VB

low

high

low

high

T1

on

on

off

off

T2

on

off

on

off

T3

off

on

off

on

T4

off

off

on

on

VY

high

high

high

low

High power consumption; current flows all the time.

43

44

Handout 1 Section C

Combinational Logic Design

Boolean Algebra for Logic Design

In this section we introduce the laws of Boolean algebra and show how it can be used to design combinational logic circuits. We then introduce the hardware description language VHDL. This language can

be used to enable computer-aided design of logic circuits.

ment the logic function

W

L = T .W .P

fact that

L = T .W .P = (T + W + P )

stored state; the output is a function of the current

inputs. (Later in the course we will study circuits with

a stored internal state. These are called sequential

logic circuits.)

45

the whole job.

T

W

P

L

46

We need:

In an extreme example, it would be very useful to be

able to work out that

A

1. Techniques for simplifying logic expressions. Simpler expressions mean fewer gates which lead to

lower cost.

the required function can be computed using gates

of only certain types. We thus only need to stock

a limited range of gates which can be readily available and cheap.

Y

C

D

can be replaced by

We are going to study two ways of solving these problems: Boolean algebra and Karnaugh maps.

B

C

Y

Boolean algebra rigorous, computable.

This sort of problem can be solved using Boolean algebra and Karnaugh maps.

47

5 variables.

48

Boolean Algebra

ORs

A+0=A

A+A=A

A+1=1

A+A=1

Commutation

A+B =B+A

A.B = B.A

normal

normal

Association

(A + B) + C = A + (B + C)

(A.B).C = A.(B.C)

normal

normal

ANDs

A.0 = 0

A.A = A

A.1 = A

A.A = 0

For example A.B + C.D = (A.B) + (C.D).

Every Boolean law has a dual: any valid statement is

also valid with

Distribution

A.(B + C + . . .) = (A.B) + (A.C) + . . .

A + (B.C. . . .) = (A + B).(A + C). . . .

normal

NEW

Absorption

A + (A.C) = A

A.(A + C) = A

NEW

NEW

49

.

+

0

1

replaced by

replaced by

replaced by

replaced by

+

.

1

0

50

A useful technique is to expand each term until it includes one instance of each variable (or its compliment). It may be possible to simplify the expression

by canceling terms in this expanded form.

A.(A + B) = A.A + A.B

= 0 + A.B

= A.B

or A.B are fine as they stand because they already

include all the variables. A term A would need to be

expanded to A.B + A.B.

the absorption rule:

A + (A.B) = (A + A).(A + B)

A + A.B

= 1.(A + B)

= A+B

=A

51

52

De Morgans Theorem

Simplify X.Y + Y .Z + X.Z + X.Y.Z

A + B + C + . . . = A.B.C. . . .

= X.Y + Y.Z + X.Z

A.B.C. . . . = A + B + C + . . .

A + B + C + . . . = A.B.C. . . .

A.B.C. . . . = A + B + C + . . .

In a simple expression like A + B + C (or A.B.C) you

can change all the operators from OR to AND (or vice

versa) provided you put a bar over each term individually and a further bar over the whole expression.

= X.Y + Y.Z

53

54

Washing Machine Example

For two variables we can prove A + B = A.B and

A.B = A + B using a truth table.

A

0

0

1

1

B

0

1

0

1

A+B

1

0

0

0

A.B

1

1

1

0

A

1

1

0

0

B

1

0

1

0

A.B

1

0

0

0

A+B

1

1

1

0

In our washing machine example we needed to implement the logic function L = T .W .P . This can be

simplified with a single application of De Morgans theorem:

L = T .W .P

= T +W +P

A + B + C = (A + B).C = (A.B).C = A.B.C

etc.

55

56

Simplify A.B + A.(B + C) + B.(B + C)

= A.B + A.B + A.C + B.B + B.C (distribute)

(B.B = B)

(De Morgan)

(repeated A.B)

= A.B + A.B.C

(B.B = 0)

= A.B + A.C + B

(B + B.C = B)

= A.B

(absorption))

= A.C + B

(A.B + B = B)

57

58

Simplify:

A

B

Y

C

= (A.B.(C + B + D) + A + B).C.D

(De Morgan)

= (A.B.C + A.B.B + A.B.D + A + B).C.D

(distribute)

= (A.B.C + A.B.D + A + B).C.D

(cancel A.B.B)

= A.B.C.D + A.B.D.C.D + A.C.D + B.C.D

(distribute)

= A.B.C.D + A.C.D + B.C.D

(cancel A.B.D.C.D)

= (A.B + A + B).C.D

(distribute)

= (A.B + A.B).C.D

(De Morgan)

= C.D

(A.B + A.B = 1)

59

= A.B.B.C.B.C.C.D

= (A.B + B.C).(B.C + C.D)

(De Morgan)

= A.B.B.C + A.B.C.D + B.C.B.C + B.C.C.D

(distribute)

= A.B.C + A.B.C.D + B.C + B.C.D

(remove repeated variables)

= B.C

(absorption)

60

A power plant is cooled by 3 ventilation fans, numbered 1 to 3, with flow rates F , 2F and 3F respectively. An alarm is to be sounded if the plant is running

and the air flow rate is less than 3.5F . Design a logic

circuit to do this.

A1

A2

A3

Y

A1 implies that fan 1 is running.

A2 implies that fan 2 is running.

A3 implies that fan 3 is running.

B implies that the plant is running.

Y sounds the alarm.

Y

= (A3 + A1.A2).B

= A3.B + A1.A2.B

= (A3.B).(A1.A2.B)

If A3 = 0 or if both A1 and A2 equal 0 then, provided

A1

A2

= (A3 + A1.A2).B

B

Y

A3

61

62

best to go back to the original problem and write down

an expression for when the alarm should be off i.e. Y

Sum of Products (SOP): usually best to write down

an expression for Y directly.

Y = A3.B + A1.A2.B

= A1.A3 + A2.A3 + B

an expression for Y and use De Morgans theorem.

Y

= A1.A3 + A2.A3 + B

= (A1 + A3) + (A2 + A3) + B

A1

algebraic manipulation. Best to consider all the binary

permutations not included in one expression and then

write down the other to include them. A Karnaugh

map makes this easier.

A3

A2

B

63

64

VHDL

Structure of VHDL

Computer-aided design tools are required for the development of complex digital systems. These tools

enable the simulation, modelling and testing of designs before they are built.

A hardware description language is required to describe the systems. It must be clear and readable for

the designer, yet sufficiently precise to enable rigorous testing of the design.

abbreviated VHDL, has been developed over many

years and is the IEEE standard 1076-1993.

65

Each entity consists of two parts. The interface and

the architecture specification.

entity compont name is

list of input and output ports

end compont name;

architecture arch name of compont name is

declarations of internal signals;

begin

description of what the the entity does

and how it is implemented

end arch name;

66

entity INV is

port(A : in BIT;

Y : out BIT);

end INV;

entity NOR2 is

port(A, B : in BIT;

Y

: out BIT);

end NOR2;

begin

Y <= not A;

end IMOD;

begin

Y <= not (A or B);

end NO2M;

entity NAND2 is

port(A, B : in BIT;

Y

: out BIT);

end NAND2;

entity NOR3 is

port(A, B, C :

Y

:

end NOR3;

begin

Y <= not (A and B);

end NA2M;

begin

Y <= not (A or B or C);

end NO3M;

67

in BIT;

out BIT);

68

To use a gate directly in a larger design you can use

the following syntax.

unique label to refer to this version of the gate

:

entity

name of gate entity

(

name of gate architecture

)

port map

(

port list of signals connected to gate

);

eg.

V1:entity INV(IMOD) port map(A, ABAR);

69

entity PLANT ALARM is

port(A1, A2, A3, B :

Y

:

end PLANT ALARM;

in BIT;

out BIT);

signal A1X,A2X,A3X,R12,R3 : BIT;

begin

I1:entity INV(IMOD) port map(A1,A1X);

I2:entity INV(IMOD) port map(A2,A2X);

I3:entity INV(IMOD) port map(A3,A3X);

N1:entity NAND3(NA3M)

port map(A1X,A2X,B,R12);

N2:entity NAND2(NA2M)

port map(A3X,B,R3);

N3:entity NAND2(NA2M)

port map(R12,R3,Y);

end NAND GATES;

70

entity PLANT ALARM is

port(A1, A2, A3, B :

Y

:

end PLANT ALARM;

Handout 1 Section D

in BIT;

out BIT);

signal A1X,A2X,A3X,BX,R1,R2 : BIT;

begin

I1:entity INV(IMOD) port map(A1,A1X);

I2:entity INV(IMOD) port map(A2,A2X);

I3:entity INV(IMOD) port map(A3,A3X);

I4:entity INV(IMOD) port map(B,BX);

N1:entity NOR2(NO2M)

port map(A1X,A3X,R1);

N2:entity NOR2(NO2M)

port map(A2X,A3X,R2);

N3:entity NOR3(NO3M)

port map(R1,R2,BX,Y);

end NOR GATES;

71

how they can be used to design combinatorial logic

circuits.

Static and dynamic hazards are introduced and techniques for removing them using Karnaugh maps are

described.

Finally, there is a discussion of the relationship between Karnaugh maps and unit-distance codes.

72

Karnaugh Map

A

Karnaugh maps are a powerful visual tool for carrying out simplification and manipulation of logic expressions with up to 5 input variables.

AB

00 01

CD

00 1

possible state of the input variables corresponds uniquely

to one of the cells, and in the cell we write the corresponding output state.

Y = A3.B + A1.A2.B

01 1

11

10

A

A1 A 2

00

A3 B

A1

11 10

1

01

11

10

AB

00 01

CD

00 1

11 10

00

01

11

B

1

A3

01

11

C

1

10 1

10

A2

73

74

A

AB

00 01

CD

00

1

1

11 10

1

01

11

10

D

C

A

1

AB

CD

00 01

11 10

00 1

11

C

1

1

D

01

11 10

1

11

C

1

01

AB

00 01

CD

00 1

10 1

10 1

B

75

76

that different Boolean terms produce:

Four variable expression

eg. A.B.C.D

eg. A.B.C

Karnaugh map.

1

0

AB

CD

00

00

A.B

1

Two variable expression

eg. A.B

1

or

01

C.D

11

1.B

0

A

01 11 10

1

1

C

1

One variable expression

eg. A

C.D

10

Remember that the Karnaugh map wraps round topbottom and side-to-side.

77

A.B + C.D

78

A1

= A3.B + A1.A2.B

1

B

= (A3.B).(A1.A2.B)

for the output from the Karnaugh map.

A3

A2

Use De Morgan to convert this to an expression

using NAND gates.

A1

A1

A3

sum-of-products expression for the inverse of the

output. This involves finding terms to cover the

blanks between the boxes filled with 1s.

A3

A2

A1

B

A3

A2

A2

= A1.A3 + A2.A3 + B

= (A1 + A3) + (A2 + A3) + B

using NOR gates.

79

80

So far the rule has been map the 1s to produce a simple NAND circuit and map the 0s (or gaps) to produce

a simple NOR circuit.

A1

A2

B

Sometimes you can produce a simpler circuit by mapping the opposite way (i.e. 0s for NAND and 1s for

NOR) and then use a final inverter gate to change the

output back again.

A3

A1

NOR solution for this map then

it is probably easiest to use

A3

A2

A

1

1

= A.B + C.D

C

1

= (A + B) + (C + D)

B

81

82

Other Sizes of Karnaugh Map

E

A

A

D

C

AB

CD

00

AB

00 01 11 10

C

0

01

11

10

00

01

11

10

00

01

11

10

E=0

83

E=1

84

A1

care state A1.A2.A3.B.

In some applications the output state for certain combinations of input variables may not matter. Such states

are known as dont care states and are marked with

an X on the Karnaugh map.

produce the simplest logic (i.e. fewest, simplest terms).

For example suppose, in the power-station fans example, it happens to be impossible for fan number 2

to fail on its own. We therefore dont care whether or

not the alarm goes off when only fan number 2 fails

(because we know that, in practice, this situation will

never occur). This would make A1.A2.A3.B a dont

care state.

85

1

B

= A3.B + A2.B

1

A3

= (A3.B).(A2.B)

A2

care state A1.A2.A3.B.

A1

A3

1

B

= A2.A3 + B

= (A2 + A3) + B

A2

= (A2 + A3) + B

86

Hazards

A static hazard is when a signal undergoes a momentary transition when it is supposed to remain unchanged.

A2

B

Y

A dynamic hazard is when a signal changes more

than once when it is supposed to change just once.

A3

A3

A2

Logic 1

Logic 0

Static 1-hazard

Logic 1

Logic 0

Static 0-hazard

Logic 1

Logic 0

Dynamic hazard

Logic 1

Logic 0

Dynamic hazard

Time

87

88

Static 1-Hazard

Removing Hazards

X

Y

U

T

This circuit

W implements

W=X.Y+Z.Y

map of the output concerned. Make sure all the

sum-of-products terms overlap.

Consider what

happens when

Z=1 and X=1

and Y changes

from 1 to 0.

map of the inverse of the output concerned. Make

sure all the sum-of-products terms representing

the inverse overlap.

simplify the logic. (This is a 3rd year topic; dont

worry about dynamic hazards for now.)

W

Time

89

90

W = X.Y + Z.Y

Hazard-Free Circuit

X

extra gate to compute the term added to the Karnaugh

map: W = X.Y + Z.Y + X.Z

1

1

X

Y

W

X

Z

1

1

Y

91

92

Applications exist where a code is required in which

not more than one bit changes between consecutive

numbers.

map only one variable changes. Because the map

wraps round this is also true when moving from top to

bottom and from far left to far right.

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

ABCD

B

Note the potential for ambiguity during the transition

from 0111 to 1000.

93

only one bit changes at a time.

94

Karnaugh map.

This particular unit distance code is called the

Grey code.

A

different path around the Karnaugh map.

D

C

B

A

0

0

0

0

0

0

0

0

B

0

0

0

0

1

1

1

1

C

0

0

1

1

1

1

0

0

D

0

1

1

0

0

1

1

0

A

1

1

1

1

1

1

1

1

B

1

1

1

1

0

0

0

0

C

0

0

1

1

1

1

0

0

D

0

1

1

0

0

1

1

0

95

96

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