FPGA/CPLD Based Designs

Vinay Sharma
vinay@ni2designs.com
ni logic Pvt. Ltd., Pune
1

Agenda
World of Electronics
Introduction to Programmable Logic
CPLD
Working principle, Architecture, I/O Block, Macrocell, programming, features, examples.

FPGA
Working principle, Architecture, I/O Block, CLB, embedded memory, clock management,
DSP capability, programming, features, examples.

Comparison of CPLD / FPGA Architecture.

VHDL and its examples
PLD Design flow
Timing Aspects & analysis of PLDs
Latest trends in PLD Market
Design Consideration for PLDs
Advantages of PLDs
Prototyping Solutions
Conclusion
Q&A
2

World of Electronics
Communication Interface
Serial, parallel, high speed, USB, irDA, PCI

Digital Logic
FPGAs/CPLDs

Master
Microprocessor/Microcontroller

Memory
SRAM, FLASH, DRAM

Power Electronics
SCRs, optical isolators,
relays, IGBT

Analog Circuitry
Sensors, Buffers,
amplifiers, ADC, DAC

An Electronic System

Displays
LCDs,LEDs
3

World of Integrated Circuits

Integrated Circuits
Full-Custom
ASICs

Semi-Custom
ASICs

User
Programmable

PLD

CPLD

PAL

PLA

Controllers

FPGA

Programmable Logic
Since the invent of PLD from 1980s with few gate count, they have grown into
million gates, so as there usage in different applications.
Advantages like programmability and reconfiguration of PLDs has given ideas and
shape to many applications.
Todays PLDs like FPGAs can compete with ASICs in terms of performance and
gate counts.
From the time their use has increased in all sectors, like defense, consumer, multi
media, communications, DSP, etc.

What is Available?
CPLD (Complex Programmable Logic Device)
consists of multiple PLA blocks that are
interconnected to realize larger digital systems.
FPGA (Field Programmable Gate Array) has
narrower logic choices and more memory
elements. LUT (Lookup Table) may replace actual
logic gates.

CPLD Working Principle (SOP)

Programmable AND array followed by fixed fan-in OR gates
A

C
Programmable switch or fuse

f1 = A B C + A B C

f2 = A B + A B C

AND plane

What is an CPLD ?
Integration of several PLD blocks with a programmable interconnect on
a single chip

PLD
PLD
Block
Block

I/O Block
Block
I/O

PLD
PLD
Block
Block

I/O Block
Block
I/O

I/O Block
Block
I/O

Interconnection
Interconnection Matrix
Matrix

I/O Block
Block
I/O

PLD
PLD
Block
Block

PLD
PLD
Block
Block

FPGA - Working Principle (LUT)

Look-up table with N-inputs can be used to implement any combinatorial function of
N inputs
LUT is programmed with the truth-table
A

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

0
1
1
1
0
1
1
1
0
1
1
1
0
0
0

Truth-table

A
B
C
D

LUT
LUT

LUT implementation
A
B
Z
C
D

Gate implementation

What is an FPGA ?
FPGA building blocks:
Programmable logic blocks
Implement combinatorial and
sequential logic

I/O

I/O

Programmable I/O blocks

Special logic blocks at the
periphery of device for
external connections

Interconnection switches

I/O

Programmable interconnect
Wires to connect inputs and
outputs to logic blocks

Logic block

I/O

10

CPLD
Architecture and Examples

11

CPLD Working Principle(SOP)

Programmable AND array followed by fixed fan-in OR gates
A

C
Programmable switch or fuse

f1 = A B C + A B C

f2 = A B + A B C

AND plane

12

CPLD Structure
Integration of several PLD blocks with a programmable interconnect on
a single chip

PLD
PLD
Block
Block

I/O Block
Block
I/O

PLD
PLD
Block
Block

I/O Block
Block
I/O

I/O Block
Block
I/O

Interconnection
Interconnection Matrix
Matrix

I/O Block
Block
I/O

PLD
PLD
Block
Block

PLD
PLD
Block
Block

13

CPLD Example- Xilinx XC 9500

JTAG
port

JTAG
controller

In system Programming Controller

14

Architecture Description
Each XC9500 device is a subsystem consisting of multiple
Function Blocks (FBs)
Provides programmable logic capability with 36 inputs and 18 outputs.
I/O Blocks(IOBs)
The IOBs provide buffering for device inputs and outputs.
FastConnect switch matrix.
Connects all FB outputs and inputs signals to the FB inputs.

15

Function Block

Global
Set/Reset

Global
Clocks

16

PLD - Macrocell

Select

Enable

f
1
Flip-flop
MUX
D

Clock

AND plane

17

Macrocell
Set control
Programmable
inversion or XOR
product term
Up to 5 product terms
Global clock or product-term
clock
Reset control

OE control
18

I/O Block

19

I/O Block
Interfaces between internal Logic and I/O Pins.
IOB consists of an
Input Buffer
Compatible with standard 5V volt CMOS, 5VTTL and 3.3 V signal
levels.
Output Driver
Capable of supplying 24 mA output drive.
Output enable selection multiplexer
Can be generated from, A product term signal, Any of the global OE
signals
User programmable ground control
To reduce system noise generated from large number of
simultaneous switching outputs.

20

CPLD Example - Altera MAX7000

EPM7000 Series Device Macrocell

21

Technology Used
CPLDs are non-volatile devices, I.e retain the program after Power-off.
The EPROM, EEPROM, FastFlash are the non-volatile type of memory.
The FastFlash technology is used because of its advantage over the EEPROM.
High Performance Logic Device.
High Memory cell density
Electrical erasable
High reliability and endurance
Fast device programming times

22

Xilinx CPLD Product Portfolio

1.8V core
1.5V - 3.3V I/O
SSTL, HSTL, LVCMOS,
LVTTL
Lower power

DataGATE
Clocking features

Clock Divide

CoolCLOCK

DualEDGE

3.3V core
2.7V - 5V I/O
LVCMOS, LVTTL
Low power

Fast Zero Power

2.5V core
1.8V - 3.3V I/O
LVCMOS, LVTTL
I/O Banking
3.3V core
2.5V - 5.0V I/O
LVCMOS, LVTTL

23

Altera CPLD Products

24

FPGA
Architecture and Examples

25

What is an FPGA?
Configurable
Logic
Blocks
Block RAMs

Block RAMs

I/O
Blocks
Block
RAMs

26

FPGA Block Diagram

27

Other FPGA Building Blocks

Clock distribution
Embedded memory blocks
Special purpose blocks:
DSP blocks:
Hardware multipliers, adders and registers
Embedded microprocessors/microcontrollers
High-speed serial transceivers

28

FPGA Basic Logic Element

LUT to implement combinatorial logic
Register for sequential circuits
Additional logic (not shown):
Carry logic for arithmetic functions
Expansion logic for functions requiring more than 4 inputs

Select

Out
A
B
C
D

LUT
LUT

Clock
29

FPGA - Working Principle (LUT)

Look-up table with N-inputs can be used to implement any combinatorial function of
N inputs
LUT is programmed with the truth-table
A

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

0
1
1
1
0
1
1
1
0
1
1
1
0
0
0

Truth-table

A
B
C
D

LUT
LUT

LUT implementation
A
B
Z
C
D

Gate implementation

30

LUT Implementation
Example: 3-input LUT
Based on multiplexers (pass
transistors)
LUT entries stored in configuration
memory cells

X1
X2
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1

0/1
0/1
0/1
0/1

Configuration memory
cells

0/1
0/1
X3
31

CLB Contains Four LUTs (Slices)

Each CLB is connected to one switch matrix
Providing access to general routing resources
COUT

COUT

High level of logic integration

Wide-input functions
16:1 multiplexer in 1 CLB or
any function
32:1 multiplixer in 2 CLBs

TBUF
TBUF
Slice S3
X1Y1

Switch
Matrix

Slice S2
X1Y0

SHIFT

Slice S1
X0Y1

Slice S0
X0Y0

CIN

Fast Connects

CIN

Fast arithmetic functions

2 look-ahead carry chains per
CLB column
Addressable shift registers in LUT
16-b shift register in 1 LUT
128-b shift register in 1 CLB
(dedicated shift chain)

32

Block RAM
Spartan-III
True Dual-Port
Block RAM

Port B

Port A

Most efficient memory implementation

Dedicated blocks of memory
Ideal for most memory requirements
4 to 104 memory blocks
18 kbits = 18,432 bits per block
Use multiple blocks for larger
memories
Builds both single and true dual-port
RAMs

Block RAM

33

Digital Clock Manager (DCM)

Up to 12 DCMs per device
Located on top and bottom edges of the die
Driven by clock input pads
DCMs provide:
Delay-Locked Loop
Digital Frequency Synthesizer
Digital Phase Shifter
Digital Spread Spectrum
Multiple outputs of each DCM can drive onto global clock buffers
All DCM outputs can drive general routing

34

Xilinx - 18 x 18 Embedded Multiplier

Embedded 18-bit x 18-bit multiplier
2s complement signed operation
Multipliers are organized in columns

Data_A
(18 bits)

18 x 18
Multiplier
Data_B
(18 bits)

Output
(36 bits)

4x4 signed

~255 MHz

8x8 signed

~210 MHz

12x12 signed

~170 MHz

18x18 signed

~140 MHz

18 x 18 signed multiplier
Fully combinatorial
Optional registers with CE & RST (pipeline)
Independent from adjacent block RAM

35

Altera: Embedded DSP Blocks

Two DSP Block columns per device
Number varies by height of column
Can implement:
Eight 9x9 multipliers
Four 18x18 multipliers
One 36x36 multiplier
Contains adder/subtractor/accumulator
Registered inputs can become shift register

36

Altera: Embedded DSP Block

37

Input/Output Blocks (IOBs)

IOB provides interface between the package pins and CLBs
Each IOB can work as uni- or bi-directional I/O
Outputs can be forced into High Impedance
Inputs and outputs can be registered
Advised for high-performance I/O
Inputs can be delayed

38

Basic I/O Block Structure

D Q
EC

Three-State
FF Enable
Clock

SR

Three-State
Control

Set/Reset
D Q
EC

Output
FF Enable

SR

Output Path

Direct Input
FF Enable
Registered
Input

D
EC

Input Path

SR

What more?

39

Spartan-3 I/O Pin

Storage Element Functions
Double-Data-Rate
Transmission
Slew Rate Control and
Drive Strength
Pull-Up and Pull-Down
Resistors
Digitally Controlled
Impedance (DCI)
Keeper Circuit
ESD Protection
SelectIO Signal Standards

40

Spartan-3 I/O Pin

Output Path

41

Spartan-3 I/O Pin

Input Path

42

Programmable Interconnect
Interconnect hierarchy
Fast local interconnect
Horizontal and vertical lines of various lengths

LL
EE

LL
EE
Switch
Matrix

LL
EE

LL
EE
Switch
Matrix

LL
EE

LL
EE
43

Switch Matrix Operation

Before Programming

After Programming

6 pass transistors per switch matrix

interconnect point
Pass transistors act as
programmable switches
Pass transistor gates are driven by
configuration memory cells
44

Configuration Storage Elements

Static Random Access Memory (SRAM)
each switch is a pass transistor controlled by the state of an SRAM bit
FPGA needs to be configured at power-on
Flash Erasable Programmable ROM (Flash)
each switch is a floating-gate transistor that can be turned off by injecting
charge onto its gate. FPGA itself holds the program
reprogrammable, even in-circuit
Fusible Links (Antifuse)
Forms a forms a low resistance path when electrically programmed
one-time programmable in special programming machine
radiation tolerant

45

FPGA Programming/Configuration
Configuration is process of loading design and device specific bit-stream into one
or more FPGAs.
Volatile nature of FPGA makes the configuration considerations important because
the configuration is required on each power-on.
FPGAs can be programmed from PC via programming cable or the programming
file(BIT file) can be stored in a PROM.
Take care of other system modules during FPGA configuration.

46

FPGA Programming/Configuration

47

Major FPGA Vendors

SRAM-based FPGAs
Xilinx, Inc.
Altera Corp.
Atmel
Lattice Semiconductor

Share over 80% of the market

Flash & antifuse FPGAs

Actel Corp.
Quick Logic Corp.

48

FPGA Vendors & Device Families

Xilinx
Virtex-II/Virtex-4: Feature-packed
high-performance SRAM-based
FPGA
Spartan 3: low-cost feature reduced
version
CoolRunner: CPLDs
Altera
Stratix/Stratix-II
High-performance SRAM-based
FPGAs
Cyclone/Cyclone-II
Low-cost feature reduced
version for cost-critical
applications
MAX3000/7000 CPLDs
MAX-II: Flash-based CPLDs

Actel
Anti-fuse based FPGAs
Radiation tolerant
Flash-based FPGAs
Lattice
Flash-based FPGAs
CPLDs (EEPROM)
QuickLogic
ViaLink-based FPGAs

49

Xilinx FPGA Families

Old families
XC3000, XC4000, XC5200
Old 0.5m, 0.35m and 0.25m
technology. Not recommended for
modern designs.
High-performance families
Virtex (0.22m)
Virtex-E, Virtex-EM (0.18m)
Virtex-II, Virtex-II PRO (0.13m)
Virtex-4 (0.09m)
Low Cost Family
Spartan/XL derived from XC4000
Spartan-II derived from Virtex
Spartan-IIE derived from Virtex-E
Spartan-3 derived from Virtex-II

50

Altera FPGA Families

Old Families
FLEX 10K, FLEX 6000, FLEX
8000
High-performance Families
Mercury
Stratix, Stratix GX, Stratix II
APEX 20K , APEX II
Excalibur
Low Cost Family
Cyclone, Cyclone II

51

Comparison of CPLD / FPGA Architecture

52

CPLD Vs FPGA
Interconnect structure.
In-system performance.
Logic Utilization.
Applications.

53

Interconnect Structure
CPLD uses a Continuous interconnect structure :
Consists of metal lines of uniform length traverse the entire length and width of
the device.
Since the resistances and capacitances of all interconnect paths is fixed,
delays between any two logic cells can be predictable.
This minimizes the logic skew.
FPGA uses a segmented interconnect structure.
Consists of matrix of metal interconnects that run throughout the device.
Switch matrices or Antifuses join the ends of these segments allowing signals
to travel between logic cells.
Number of segments required to interconnect signals is neither constant nor
predictable, so delays are not fixed or specified until place and route is
completed.

54

Logic Utilization
Logic cells in most FPGA architecture have fine granularity, therefore more logic
cells are required to implement a function in FPGA than in a CPLD.
Logic cells in FPGA can contain only small portion of a design, so a heavy burden
is placed on its segmented interconnect structure.
As design complexity increases, the probability of routing conflicts also increases
leading to lower FPGA device utilization.
Logic density in FPGA is less due to only 9 variables, where as CPLD has 36
variables available.

55

Applications - FPGAs
FPGAs
Basically register intensive applications.
Data paths.
Hardware Emulation.
Image controller.
Battery powered applications.
Field-test equipments.
Gate-array prototyping.

56

Applications - CPLDs
CPLDs
Basically combinatorial functions.
Bus interfacings.
Comparators.
High-speed wide decoders.
Large fast state micro controllers.
High speed GLUE Logic.
System video controller.
PAL integration.

57

VHDL and its examples.

58

VHDL Language
Hardware Description Language (HDL)
High-level language for to model, simulate, and synthesize digital circuits
and systems.
History
1980: US Department of Defense Very High Speed Integrated Circuit program
(VHSIC)
1987: Institute of Electrical and Electronics Engineers ratifies IEEE Standard
1076 (VHDL87)
1993: VHDL language was revised and updated
Verilog is the other major HDL
Syntax similar to C language
Many tools accept both Verilog and VHDL

59

Terminology
Behavioral modeling
Describes the functionality of a component/system
For the purpose of simulation and synthesis
Structural modeling
A component is described by the interconnection of lower level
components/primitives
For the purpose of synthesis and simulation
Synthesis:
Translating the HDL code into a circuit, which is then optimized
Register Transfer Level (RTL):
Type of behavioral model used for instance for synthesis

60

Digital Circuits and VHDL Primitives

Most digital systems can be described based on a few basic circuit elements:
Combinational Logic Gates:
NOT, OR, AND
Flip Flop
Latch
Tri-state Buffer
Each circuit primitive can be described in VHDL and used as the basis for
describing more complex circuits.

61

Digital Circuit Primitives

Combinational Logic Gates: NOT, OR, AND
Flip Flop/Latch
Tri-state Buffer
Logic gates can be modeled using concurrent signal assignments:
Z <= not A;
Y <= A or B;
X <= C and D;
W <= E nor F;
U <= B nand D;
V <= C xor F;

C
D

AND
E

NOR

It is possible to design circuits from logic gates in this way

62

4-to-1 Multiplexer
Libraries
library
libraryIEEE;
IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;

External world interface

entity
entitymux
muxisis
port
port( (
a,a,b,
b,c,c,d:
d:ininstd_logic;
std_logic;
s:s:inin std_logic_vector(1
std_logic_vector(1downto
downto0);
0);
y:y:out
std_logic);
out std_logic);
end
entity
end entitymux;
mux;
architecture
architecturemux1
mux1of
ofmux
muxisis
begin
begin
process
process(a,
(a,b,
b,c,c,d,
d,s)s)
begin
begin
case
casessisis
when
when"00
"00=>
=>yy<=
<=a;a;
when
when"01"
"01"=>
=>yy<=
<=b;
b;
when
"10"
=>
y
<=
c;
when "10" => y <= c;
when
when"11"
"11"=>
=>yy<=
<=d;
d;
end
case;
end case;
end
endprocess;
process;
end
architecture
end architecturemux1;
mux1;

a
b

c
d

Internal logic design

S(1) S(0)

63

Sequential Logic: D-Flip Flop

architecture
architecture rtl
rtl of
of D_FF
D_FF is
is
begin
begin
process
process (Clock,
(Clock, Reset)
Reset) is
is
begin
begin
if
if Reset
Reset == 1
1 then
then
QQ <=
0;
<= 0;
if
if rising_edge(Clock)
rising_edge(Clock) then
then
QQ <=
D;
<= D;
end
if;
end if;
end
end process;
process;
end
architecture
end architecture rtl;
rtl;

Flip-flop
D
Clock

Reset

64

Binary Counter
entity
entity counter
counter is
is
generic
(n
:
integer
generic (n : integer :=
:= 4);
4);
port
(
port (
clk
clk :: in
in std_logic;
std_logic;
reset:
in
std_logic;
reset: in std_logic;
count:
count: out
out std_logic_vector(n-1
std_logic_vector(n-1
downto
0)
downto 0)
);
);
end
use
end entity
entity counter;
counter;
use ieee.numeric_std.all;
ieee.numeric_std.all;

This example is not explicit on

the primitives that are to be used
to construct the circuit.
The + operator is used to
indicate the increment operation.

architecture
architecture binary
binary of
of counter
counter is
is
Signal
cnt
:
std_logic_vector(n-1
downto
Signal cnt : std_logic_vector(n-1 downto0);
0);
begin
begin
process
process (clk,
(clk, reset)
reset)
begin
begin
if
if reset
reset == '1'
'1' then
then --- async
async
reset
reset
cnt
cnt <=
<= (others
(others =>
=> '0');
'0');
elsif
rising_edge(clk)
elsif rising_edge(clk) then
then
cnt
<=
cnt
+
1;
cnt <= cnt + 1;
end
end if;
if;
end
process;
end process;
Count
<=
Count
<= cnt;
cnt;
end
architecture
end architecture binary;
binary;
65

State Machine
If a trigger signal is received, will stretch it to 2 cycles and wait for accept signal

entity
entity trigger
trigger is
is
port
(
port (
clk,
in
clk, reset:
reset:
in
std_logic;
std_logic;
trigger,
trigger, accept
accept :: in
in
std_logic;
std_logic;
active:
out
active:
out
std_logic);
std_logic);
end
end entity
entity trigger;
trigger;

curr_state

trigger

architecture
architecture rtl
rtl of
of trigger
trigger is
is
type
state_type
is
(s0,
s1,
type state_type is (s0, s1, s2);
s2);
signal
cur_state,
signal cur_state,
next_state:
next_state: state_type;
state_type;
begin
begin
registers:
registers: process
process (clk,
(clk, reset)
reset)
begin
begin
if
if (reset='1')
(reset='1') then
then
cur_state
<=
s0;
cur_state <= s0;
elsif
elsif rising_edge(clk)
rising_edge(clk) then
then
cur_state
<=
next_state;
cur_state <= next_state;
end
end if;
if;
end
process;
end process;

clk

State
State
Transition
Transition
Logic
Logic

Output
Output
Logic
Logic

accept

reset

66

State Machine (cont.)

process
process (cur_state,
(cur_state, trigger,
trigger,
accept)
is
accept) is
begin
begin
case
case cur_state
cur_state is
is
when
s0
=>
when s0 =>
active
active <=
<= '0';
'0';
if
(trigger
if (trigger == '1')
'1') then
then
next_state
<=
s1;
next_state <= s1;
else
else
next_state
next_state <=
<= s0;
s0;
end
if;
end if;
when
when s1
s1 =>
=>
active
active <=
<= '1';
'1';
next_state
next_state <=
<= s2;
s2;
when
s2
=>
when s2 =>
active
active <=
<= '1';
'1';
if
(accept
if (accept == '1')
'1') then
then
next_state
<=
s0;
next_state <= s0;
else
else
next_state
next_state <=
<= s2;
s2;
end
if;
end if;
end
case;
end case;
end
end process;
process;

S0

accept

trigger

S1

S2

clk
curr_state

State
State
Transition
Transition
Logic
Logic

Output
Output
Logic
Logic
R

67

PLD Design flow

68

FPGA Design Flow

Design Specification

Design Entry/RTL Coding

Behavioral or Structural Description of Design

RTL Simulation
Functional Simulation
Verify Logic Model & Data Flow
(No Timing Delays)

LE
MEM

Synthesis
I/O

Translate Design into Device Specific Primitives

Optimization to Meet Required Area & Performance
Constraints

Place & Route

Map Primitives to Specific Locations inside
Target Technology with Reference to Area &
Performance Constraints
Specify Routing Resources to Be Used
69

FPGA Design Flow

tclk

Timing Analysis
- Verify Performance Specifications Were Met
- Static Timing Analysis

Gate Level Simulation

- Timing Simulation
- Verify Design Will Work in Target Technology

Program & Test

- Program & Test Device on Board

70

Design Flow
Specifications

Test Bench

Functional
Simulation

Design Entry

Pre-Layout
Simulation

Logic Synthesis
Static Timing Analysis

Sch, VHDL, Verilog

Synth. Lib
Constraints
Timing Lib.

Post-Layout
Simulation

System partitioning
and Floor-planning
Placement and Routing
Static Timing Analysis

Programming
Production

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EDA Tools : Altera Quartus II

Fully integrated design tool
Multiple design entry methods
Text-based: VHDL, Verilog,
AHDL
Built-in schematics editor
Logic synthesis
Place & route
Simulation
Timing & power analysis
Create netlist for timing
simulation
Device programming
Xilinx ISE has similar kind of features

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Timing Aspects & Analysis of PLDs

73

Timing Issues
Basic Questions
Does my design meet a given timing requirement, or
How fast I can run the design?
Are there any chances of failures?
We know about nominal delay simulation; why not use it..?
Requires too many patterns.
Increases exponentially with the number of design inputs.
Even worse if we consider sequences needed to initialize latches.
So what we do instead..??
Separate function from time,
Determine when transitions occur without worrying about how.

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Timing Issues
The basic idea of Static Timing Analysis is,
To find that the data is transferred through the system safely.
Instead of considering an infinitely long simulation sequence, fold all possible
transitions back into a single clock cycle.
If the design is working extremes, we can guarantee it always will.
Static part just means we arent doing simulation (dynamic).

A
B
D

Data rate?

Clock rate?

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FPGAs - Fmax

All in MHz
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Synchronous or Asynchronous
Synchronous designs have a clock that determines when signals should be
sampled. The signals are either sampled at the rising edge or at the falling edge of
the clock.
Unit of Time is Fixed
Asynchronous designs do not operate with a clock. Relies on handshaking
between logic. Sensitive to glitches and ordering of signals.
Unit of Time is NOT Fixed

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Why Synchronous?
Signals are sampled at well- defined time intervals.
Interfacing two synchronous blocks is simple. Interfacing asynchronous blocks is
not simple.
Synthesis and other tools does not handle asynchronous logic very well.
FPGAs are NOT good for Asynchronous designs.

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Timing Issues
n

k-bit
Present State
Value

Combinational
Logic
Circuit
K

DFF
Q D

k-bit
Next State
Value
k
clk

What is the MAXIMUM frequency of operation for above system?

Maximum Frequency = 1/ (longest delay path I.e. Critical Path)

79

How To Improve Speed?

The register-to-register delay is usually the delay path that sets the maximum
clock rate.
From a design point of view,one can only affect the combinational logic between
the registers
Need to shorten the maximum combinational delay path
Setup/Hold time of registers are fixed
Can shorten the delay by placing a register in the combinational logic to break
longest delay path
This technique is called pipelining
Adds latency to the output (the number of clocks between an input value and
its corresponding output result)

80

Latest trends in PLD Market

81

Fight of Titans

82

State of the Art in FPGAs

90 nm process on 300 mm wafers
Lower cost per function (LUT + register)
Smaller and faster transistors: Higher speed
System speed up to 500 MHz
Mainly through smart interconnects, clock management, dedicated circuits,
flexible I/O.
Integrated transceivers running at 10 Gigabits/sec
More Logic and Better Features:
>100,000 LUTs & flip-flops
>200 embedded RAMs, and same number 18 x 18 multipliers
1156 pins (balls) with >800 GP I/O
50 I/O standards, incl. LVDS with internal termination
16 low-skew global clock lines
Multiple clock management circuits
On-chip microprocessor(s) and multi-Gbps transceivers
83

Latest Devices: Capacity & Features

Xilinx Virtex-4
90nm process
Up to 960 I/Os
>2,00,000 logic cells
Up to 552 18kb block RAMs (~10Mb
RAM)
192 DSP slices (18x18 multiplieraccumulator)
20 digital clock managers (DCM)
24 high-speed serial transceivers
(622Mb/s to 11.1Gb/s)
Up to four PowerPC 405 cores

Altera Stratix-II
90nm process
Up to 1170 I/Os
1,79,000 logic elements
9.6Mb embedded RAM
96 DSP blocks: 380 18x18 multipliers
12 PLLs
Serial I/O up to 1Gb/s
No hard processor cores

84

Design Consideration for PLDs

85

Designing with FPGA

A complete flat land (logic elements,
memory, gates).
No predefined architecture or
controllers.
Generation of timings and timing
match.
Control of bus.
Handshaking of signals.
Protocol development.
Verification of logic.
User to describe complete logic with
HDLs.
Logic
dependant
on
..HDL..HDL..HDL

86

Designing with FPGA

Microcontroller
Memories
Analog Circuits
Communication
Peripherals

Handshaking

FPGA
Timing

Voltage Levels

Protocols, Speed

Bus Control, triggering

87

Advantages of PLDs

88

Why to go for PLDs ?

Flexibility.
In system programmability.
Less project development time.
Best prototyping solution.
Cost effective solutions.
Involves less risk.
Design security.
Consumes less board area.
Reconfigurable computing.
Best suits hardware verification for design.

89

Prototyping Solutions

90

Prototyping Solutions
A system model to test and develop the
product before its final implementation.
Prototyping is like headache to designers
Ease of prototyping is necessity
Flexibility is must
Individual eval boards or kits available
Need for universal platform integration
Modular approach
Up gradation and addition of modules at regular interval.

91

Prototyping Boards
Multi-vendor
device support for
Xilinx and Altera
PLDs.
All FPGA I/Os
accessible
through headers.

92

Prototyping Boards
A universal platform for various
technologies
An excellent prototyping and
system development platform
Modular approach
Modules can be integrated
according to needs
Flexible and easy up gradation

93

Prog. Port

One Platform

Keypad Interface
Box Osc.

Configuable I/Os
7 Seg Disp,
LCD interface

FPGA

FPGA

SRAM
89c51
PIC uC
Modules

ADC/DAC
..more
94

Embedded System Development.

High-Resolution Image Processing.
High speed Digital Signal Processing.
NIOS-II/ Microblaze Soft Processor Development.
USB / LAN based application development.
Process Control, automation and Industrial Systems
Universal Prototyping Platform.
95

Conclusion
PLDs are
Cheaper
Faster
Bigger
More versatile
and easier to use
And obviously best choice for the system designer.

96

Thank You..!

ni logic Pvt. Ltd.,

Email: info@ni2designs.com
URL: www.ni2designs.com

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