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Line Protection
Series Capacitors
Improve power transfer
Improve system stability
Location of capacitor varies
Dedicated protection
Spark gap
Gap-Protected Bank
Series
Capacitor
Spark
Gap
Discharge
Reactor
Bypass
Switch
MOV-Protected Bank
Series
Capacitor
MOV
Discharge
Reactor
Triggered Air
Gap
Bypass
Switch
mXL
XC
I
V
Fault
ES
ER
XC > mXL
XC < XS + mXL
I
Fault
XL + XR
XC
R
V
ES
ER
XC > mXL
XC < mXL + XL + XR
Line 1
XC1
Fault 1
Line 2
XC2
Fault 2
Relay
XL
XC
XR
Phase-to-Ground
Fault
V2
V2
XC > X2S
V2F
Current Inversion
S
XS
XC
XL
XR
Fault
IS
IS
VS
IR
XC > XS
VR
IR
ZL
2
ZL
2
XC
B
ZL
B
jXC
B
A
XC
ZL
X
B
ZL
B
A
jXC
Subharmonic-Frequency Transient
X 4
1
0
2
2
R
Mho Characteristic
XI
mZ
V = m ZR I V
V
VP
RI
ZR I VPMEM
VPMEM
= TRIP
V
= NO TRIP
I
V=0
With Memory
No Memory
V VPMEM
VPMEM
= NO TRIP
I
ZR I
With Memory
V V
= TRIP
No Memory
V2
Z2S
I2
Z2L
Relay
Z2R
Z1L + Z2R
Z1L
Z2F
Z2R
Forward Faults
R2
Z2S
Z1L
Relay
10
XC
R
XC
Z1L
Relay
Ratio
1
VMEAS
Threshold
VCALC
1180
I
Re R
IL
Internal Faults
With Outfeed at L
11
Internal
Faults
87LR
1 180
Restraint
Region
Re IR
IL
Trip
Region
87LANG
2
1180
Advantage in
Tolerance to
Outfeed
I
Re R
IL
I
Im R
IL
1180
(b)
(a)
12
I
Re R
IL
IR
IL
Re IR
IL
13
14
Zone 1 Setting
If spark gap fires for external faults: Set
Zone 1 to 80% of compensated line
impedance
If spark gap does not fire for external faults
or MOVs are used: Set Zone 1 to 50% of
compensated line impedance
Validate settings with transient simulation
studies or testing
15
R
XC
ZL
Relay
Infeed
ZL
2
XC
ZL
2
Relay
Relay
Z 2F
Z1L XC
2
Z 2R Z 2F 0.1
16
XC
ZL
Relay
Relay
Z 2F
Z1L XC
2
Z 2R Z 2F 0.1
XC
ZL
Relay
Relay
Z 2F
Z1L XC
XC
2
Z 2R Z 2F 0.1
17
XCS
ZL
XCR
Relay
Relay
Z 2F
Z 2R Z 2F 0.1
XCS
ZL
Relay
XCR
Relay
18
19
Voltage Ratio
Zone 1 Trip
Threshold
6
9
10
Time (Cycles)
11
12
Voltage Ratio
Zone 1 Trip
Threshold
9
10
Time (Cycles)
20
11
12
Measured Impedance
(Ohms)
Line Impedance
11
13
Time (Cycles)
15
Angle (Degrees)
160
120
80
40
0
3
5
Time (Cycles)
21
Voltage Inversion V1
Angle (Degrees)
60
40
20
4
5
Time (Cycles)
Conclusions
Memory polarization and directional element
offset address voltage inversion
Line differential elements are immune to
voltage inversion and tolerant of current
inversion and subharmonic-frequency
transients
22
Conclusions
Subharmonic-frequency transients can
cause overreach and underreach of
distance elements
Transient simulation and testing is
strongly recommended
23