Design of a FinFET Based Inverter Using

MTCMOS and SVL Leakage Reduction

Technique
Manorama, Saurabh Khandelwal and Shyam Akashe

Abstract-- Scaling of the Standard single-gate bulk MOSFETs

faces great challenges in the nanometer regime due to the severe
short-channel effects that cause an exponential increase in the
leakage current and enhanced sensitivity to process variations.
Double-gate FinFET has better SCEs performance compared to
the conventional CMOS and stimulates technology scaling
because of the self-alignment of the two gates. In this paper, we
describe different mode of FinFET technology and performed
the comparative analysis of stand-by leakage (when the circuit is
idle), delay and the total power of the logic circuit, on Cadence
Virtuoso tool at 45nm By applying MTCMOS and SVL are
effective circuit-level techniques and that provides a high
performance and low power design by utilizing both low and
high-threshold voltage transistor. The leakage power of the
FinFETs based inverter using SVL technique is 50-60% lower
than the normal FinFETs based inverter and the total power
consumption of FinFETs based inverter using MTCMOS
technique is 65-70% lower than the normal FinFETs based
inverter.
Index Terms-- FinFETs, High-performance, Independent gate
(IG) mode, Low power (LP) mode, Short channel effects (SCEs),
Shorted gate (SG) mode.

I. INTRODUCTION
In fabrication of MOSFET, the minimum channel length
has been decrease incessantly. The inspiration after this
decrease has been an increasing interest in high speed devices
and in very large scale integrated circuits. As we go down to
65nm there seem to be no viable options of continuing forth
with the conventional MOSFET. Sever short channel effects
(SCE) such as VT roll off and drain induced barrier lowering
(DIBL), increasing leakage current such as subthreshold S/D
leakage, D/B (GIDL), gate direct tunneling leakage, and hot
carrier effects that result in device degradation [1], are
observed. The gate leakage current causes increased power
Manorama is with the Electronics and Communication Engineering
Department,
ITM
University,
Gwalior-474001,
India
(e-mail:
chauhanmanorama@ymail.com).
S. Khandelwal and S. Akashe are with the Department of Electronics and
Communication, ITM University, Gwalior-474001, India (e-mail:
saurabhkhandelwal52@yahoo.com, shyam.akashe@yahoo.com).

978-1-4673-5630-5//13/$31.00 2013 IEEE

consumption and may affect device and circuit functionality.

Thus, the leakage current imposes a practical limit on oxide
thickness [2]. The equation (1) shows overall power
consumption as the sum of dynamic and static power:
ACV f

Vl

(1)

The first term is the dynamic power lost from charging and
discharging the processors capacitive loads. A defines the
fraction of gates switching, C is the total capacitance load of
all gates, the VDD supply and f is the gate switch frequency.
The second term is the standby power lost due to leakage
current, lleak.
Equation (2) shows that the Leakage current and the source
of static power consumption, is defined as the sum of
subthreshold and gate-oxide leakage. Subthreshold leakage
current depends on threshold voltage and supply voltage.
Equation (3) shows K1 and n are experimentally derived, W is
the gate width, and V is the thermal voltage and it increases
linearly with temperature. Gate-oxide leakage is less
understood than subthreshold leakage. In equation (4) K and
are experimentally derived. Tox represents oxide thickness and
as it is increased its effects reduces the gate leakage current
[3].
(2)
We

(1

(3)
(4)

The multi-gate MOSFETs offer distinct advantages for

simultaneously suppressing the subthreshold and gate
dielectric leakage currents in the sub-45-nm CMOS
technologies. The two electrically coupled gates and thin
silicon body suppress the short-channel effects in a doublegate MOSFET, which reduces the subthreshold leakage
current [4].The FinFET is the most attractive choice among
the double-gate device architectures due to the self-alignment
of the two gates, it is referred to as a quasi-planar device,
because its geometry is in the vertical direction (the fin
height). The narrow fin structure prepared efficiently by
spacer fin patterning, flexibly manages the drive current and
circuit performance. The drive current of FinFET is greater
than the DGMOSFETs, because a thin gate oxide is used in

the top channel of the Si-fin as is the case in the sidewall

channel [5].

Vdd

Lg
Vhigh

Spacer
material
Gate
Tox

Source
PN
junction

Drain

Vin

Vout

Wfin

Hfi

Leff

Gnd

Drain

Source

(b) IG mode

Gate
Leff of
FinFET

Vdd

Fig. 1. FinFET structure: Lg= gate length, Tox= gate oxide thickness, Leff=
effective channel length, Hfin= height of fin, Wfin= width of fin.

The channel width for a FinFETs device is given by equation

(5),
(5)
2
The relation among the gate length (Lg) and Wfin is described
at Lg= 1.5 * Wfin as the well known criteria for limiting SCEs
in FinFET [6].
Designing of different FinFETs, inverter can be configured
in one of the subsequent modes, (a) Shorted-gate (SG) mode,
in this mode both gate are shorted and we get improved drive
strength and have better control over the channel length (b)
Independent-gate (IG) mode, in which independent signals
drive the two device gates, this may reduce the number of
transistors in the circuit. (c) Low-power (LP) mode, in which
we are applying a low voltage to n-type FinFET and high
voltage to p-type FinFET. This varies the threshold voltage of
the devices which reduces the leakage power dissipation at the
cost of increased delay. (d) A hybrid IG/LP-mode is a
combination of LP and IG modes [7].

Vhigh

Vin

Vout
Vlow

Gnd
(c) LP mode
Vdd

Vdd

Vin

Vout
Vlow

Vin

Vout

Gnd
(d) IG/LP mode

Gnd
(a) SG mode

Fig. 2. Different modes of an inverter circuit (a) Shorted-gate mode, (b)

Independent gate mode, (c) Low power gate mode, (d) hybrid mode
combination of IG and LP mode.

The inverter schematic of each of the above four model is

shown in Figure 2, and Figure 2(a) illustrate shorted-gate (SG)
mode inverter in which both transistor p-type FinFET and ntype FinFET back gate are connected its front gate, this
configuration is best appropriate for high-performance
applications. Figure 2 (b) illustrate independent gate (IG)
mode inverter in which n- type FinFET back gate is shorted
with its front gate, and p- type FinFET back gate is biased at
high (Vhigh = 0.9V). This mode has low area means reduced
no. of transistor and switched capacitance. Figure 2 (c)
illustrate low power (LP) mode inverter in which p-type
FinFET back gate is biased at high (Vhigh = 0.9V) and n-type
FinFET back gate is reverse biased at low (Vlow = -0.1 V),
back gate applied potential changes the threshold voltages of
the both FinFETs, which is essential for low-power
applications at a cost of increased delay. Figure 2 (d) illustrate
hybrid mode that is combination of low power and
independent mode which gives the Low leakage, area and
switched capacitance.
II. LEAKAGE CURRENT REDUCTION TECHNIQUES
In a CMOS circuit, the total power consumption is
described as the sum of dynamic and static components of
power throughout the operation of the circuit. When the
circuit is in idle state, the power consumption is due to the
leakage current. Dynamic power consumption consists of two
components. The switching power contributed by charging
and discharging of load capacitance [8], [9].Hence, to restrain
the power consumption in low-voltage circuits, it is needed to
reduce the leakage power in standby modes of operation [10].
A. Multithreshold CMOS Technique (MTCMOS)
There are several techniques for reducing standby power
Pst. First is to use a multithreshold-voltage CMOS
(MTCMOS), shown in Fig. 3 This technique reduces standby
power by using the pMOSFET switches with higher threshold
voltage Vthp in between power supply and low Vth pmos
transistor for disconnecting the power supply and nMOSFET
switches with higher threshold voltage Vthn using in between
ground and low Vth nmos transistor for disconnecting the
ground from low Vth nmos transistor in the active mode low
Vth transistors can operate with high speed and low switching
power dissipation. When the circuit is in sleep mode the high
Vth transistors are turned off causing isolation of low Vth
transistor from supply voltage and ground thereby reducing
sub-threshold leakage current. However, it has serious
drawbacks such as the need for additional fabrication process
for higher Vthp and higher Vthn and the fact that storage circuits
based on this technique cannot retain data [11],[12].
B. Self-Controllable Voltage Level Technique (SVL)
Three types of self-controlled voltage level (SVL) circuit
technique were developed and in the figure 4 shows that
FinFETs inverter as a load circuit.

vdd
CLB

High Vth

Low Vth
vdd
Vout

Vg

Gnd
Load circuit

CL

Low Vth
High Vth

Gnd
Fig. 3. Multithreshold voltage CMOS (MTCMOS) Conventional technique
for reducing standby power.

Type-1 Figure 4 (a) has an upper SVL circuit, in which use

single p-MOSFET switch (p-SW) and n no. of n-MOSFET
switches (n-SWs) connected in series. The on p-SW connects
a power supply (VDD) and the load circuit in the active mode
on request, and on n-SWs connected and the load circuit in
standby mode. Type-2 Figure 4 (b) has a lower SVL circuit, in
which use single n-MOSFET switch (n-SW) and n no. of pMOSFET switches (p-SWs) connected in series. The lower
SVL circuit not only supplies VSS to the active-load circuit
through the on n-SW but also supplies Vss to the standby load
circuit through the use of the on p-SWs. Type-3 Figure 4 (c)
has a combination of lower and upper SVL circuit [13].While
gate voltage (VG) of the stand-by inverter shown Fig. 4(a) is
kept at 0, the p-MOSFET (p-MOS) is turned on while the nMOSFET (n-MOS) is turned off. When control signal (CLB)
turns on n-SW1 and turns off p-SW, VDD is supplied to the
inverter through n n-SWs. Thus, a drain-to-source voltage
(Vdsn), to be exact, a drain voltage (VD) of the off n-MOS,
can be articulated as:
nv
(6)
In the equation (6) v is voltage drop of the single n-SW,
Vdsn can be changed by varying n or v (or both). Decreasing
Vdsn by increasing nv will increase the barrier height of the
off n-MOS; that is, it will diminish the drain-inducedbarrier-lowering (DIBL) effect [3] and, as a result, Vth
increases. This results in a decrease in the subthreshold
current of the n-MOS. that is, the leakage current through the
inverter decreases [14],[15].
In the case of the Type-2 SVL circuit, a negative control
signal (CL) turns on p-SW1 and turns off n-SW so that VSS is
supplied to the stand-by inverter with VG of 0 (i.e., nv)
through n p-SWs. Thus, according to Equation (vi), reduced
Vdsn reduces subthreshold leakage current. Further, source
voltage (VS) is increased by nv, so the substrate bias (i.e.,
back-gate bias) (VSub) is increased and it is expressed by:
(7)

Upper SVL circuit

Vdd

n- SW1
CLB

Both the reduction in the DIBL effect and the increase in

the back-gate bias effect lead to further increase in Vth. Thus,
in this case, subthreshold indicated further decreased. The
DIBL effect on n-MOS in the stand-by inverter incorporating
the Type-3 SVL circuit is further decreased, since Vdsn in this
case can be expressed as:
2
(8)

n-SWn
p-SW

III. SIMULATION RESULT AND DISCUSSION

VD

Vdd
Vg
Gnd

4 (a)
Gnd

In this section we present a comparative analysis in

between normal FinFETs based inverter, MTCMOS technique
on FinFETs based inverter and SVL technique on FinFETs
based inverter at 45nm using Cadence Virtuoso tool. Figure 5
shows the simulated output and leakage current characteristics
of the normal FinFETs based inverter.

Vdd
Vdd
Vout

Vg

Gnd
VS

p- SW1

CL
n-SW

p-SWn

4 (b)
Fig. 5. Waveform for FinFETs based inverter, leakage current, output and
input.

Lower SVL circuit

Upper SVL circuit

Vdd
n- SW1

Figure 6 shows the simulated output and leakage current

characteristics of the FinFETs based inverter using MTCMOS
technique. And Figure 7 shows the simulated output and
leakage current characteristics of the FinFETs based inverter
using SVL technique.

CL
n-SWn

p-SW
Vd

Vdd

Vg

Gnd
VS

Lower SVL circuit

p-SWn

CL

p-SW1
n-SW
4 (c)

Gnd

Fig. 4. Self-controllable-voltage-level (SVL) circuit for supplying Vd and VS.

(a) Type-1 SVL circuit (upper SVL), (b) Type-2 SVL circuit (lower SVL), (c)
Type-3 SVL circuit.

Fig. 6. Waveform for FinFETs based inverter using MTCMOS technique,

leakage current, output and input.

Fig. 7. Waveform for FinFETs based inverter using SVL technique, output,
input and leakage current.

Fig. 10. Power consumption waveform for FinFETs based inverter using
SVL technique.

Figure 8, 9 and 10 shows the power consumption waveform

for normal FinFETs based inverter, FinFETs based inverter
using MTCMOS technique, FinFETs based inverter using
SVL technique respectively, and in the table II mention the
average values of these power consumption waveform.
Table I
Comparison Result For Leakage Current In Between Normal Finfets Based
Inverter, Finfets Based Inverter Using MTCMOS Technique, Finfets Based
Inverter Using SVL Technique.

FinFETs
based Inverter

FinFETs
mode
Fig 8. Power consumption waveform for normal FinFETs based inverter.

SGmode
LPmode
IG mode
LP/IGmode

Leakage
Power(nW)
3.8
1.2
1.7
10.42

FinFETs
based inverter
using
MTCMOS
technique
Leakage
Power(pW)
1.285
0.32
0.87
1.56

FinFETs
based inverter
using SVL
technique
Leakage
Power(fW)
98.43
57.34
34.45
104.23

Table II
Comparison result for Power consumption in between normal FinFETs based
inverter, FinFETs based inverter using MTCMOS technique, FinFETs based
inverter using SVL technique.

FinFE
Ts
mode

Fig. 9. Power consumption waveform for FinFETs based inverter using

MTCMOS technique.

SG
LP
IG
LP/IG

FinFETs based
Inverter
Power
Consumption(n
W)
709.2
567.6
587.3
710.4

FinFETs based
inverter using
MTCMOS
technique
Power
Consumption(p
W)
52.71
23.34
38.19
44.04

FinFETs based
inverter using
SVL technique
Power
Consumption(n
W)
430.4
102.34
245.5
290.34

[3]
Table III
Comparison result for Delay in between normal FinFETs based inverter,
FinFETs based inverter usisng MTCMOS technique, FinFETs based inverter
using SVL technique.

FinFETs
mode
SG mode
LP mode
IG mode
LP/IG mode

FinFETs
based Inverter
Delay(pS)
250.4
220.7
223.1
254.7

FinFETs
based inverter
using
MTCMOS
technique
Delay(pS)
234.4
218.7
224.1
289.7

FinFETs
based inverter
using SVL
technique

[5]

Delay(pS)
208.98
200.2
201.22
267.5

[7]

Table I, II and III states simulation result for the leakage

power, power consumption and delay respectively of normal
FinFETs based inverter, FinFETs based inverter using
MTCMOS technique, FinFETs based inverter using SVL
technique and these simulation results shows that the SVL
technique is better for reducing leakage current and delay but
it is not good for active power consumption of the circuit.
IV. CONCLUSION
We have discussed various logic styles for low-power
FinFET based inverter. Four modes are investigated using
Cadence Virtuoso tool. Our results indicate that on an
average, LP and IG mode has 40% low leakage power, 25%
low power consumption and 10% low delay than the other
mode of FinFETs respectively. This paper concludes in
between normal FinFETs based inverter, FinFETs based
inverter using MTCMOS technique, FinFETs based inverter
using SVL technique. Simulation result shows the FinFETs
based inverter using SVL technique has 50-60% low leakage
power than the normal FinFETS based inverter and 25-30%
lower than the FinFETs based inverter using MTCMOS
technique. FinFETs based inverter using MTCMOS technique
consume 65-70% less power than the normal based inverter
and 35-40% than the FinFETs based inverter using SVL
technique respectively. In the case of delay FinFETs based
inverter using SVL and MTCMOS technique has 12-15% and
8-10% low than the normal FinFETs based inverter
respectively. For reducing the leakage power and delay SVL
technique is better than the MTCMOS technique but power
consumption in the SVL technique is more than the
MTCMOS technique.
Acknowledgement
This work is supported by ITM University, Gwalior, India
in Collaboration with Cadence System Design, Banglore,
India.
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