COE758 XilinxISE9.

2Tutorial1
CreatingSimpleProject
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StartXilinxISEsoftware,andpressOKonTipoftheDaytogettoascreen
as shown above
asshownabove
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CreatenewprojectbyselectingFile>NewProject
New window will open
Newwindowwillopen.
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Projectlocation selectthedirectoryfortheprojects
Project Name selectprojectname.Noticehowdirectorywithsame
ProjectName
select project name Notice how directory with same
projectnameisaddedintheProjectLocationtextfield.
PressNext>

IntheDevicePropertiesselectionofthedeviceandpackageisdone.
In
the Device Properties selection of the device and package is done.
Family:Spartan3E
Device:XC3S500E
Package:FG320
S d 5
Speed:5
PreferredLanguage:VHDL
KeeptherestofthesettingsandpressNext>

Inthiswindowyoucaneitheraddnewsource,orleaveitforlaterasitis
done in this tutorial
doneinthistutorial.
Press Next>severaltimesuntilfinishandpressFinish onthelastwindow.
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Whennewprojectiscreatedsourcefilescanbeadded.Rightclickonthe
device and select New Source
deviceandselectNewSource.
NewWizardwindowisopened
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SelectVHDLModuleandenterthenameofthevhdl sourcefile.
Press Next>
PressNext>
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Inthiswindowinputandoutputsignalsarespecified.
Notice that for led and switch signals Bus checkbox is selected and size of
NoticethatforledandswitchsignalsBuscheckboxisselectedandsizeof
thebusisspecified.
PressNext>

Lastwindowinthewizardshowssummaryofthesourceincludinginputs
and outputs for that module
andoutputsforthatmodule.
PressFinish toaddsourcefiletoproject.
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WhensourcefileisaddedISEtoolwindowshouldlookasabove
Next step is to add actual processing source code
Nextstepistoaddactualprocessingsourcecode.
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SampleVHDLprogram
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;

Librarydefinitions

entitytutorialis
Port(clk :inSTD_LOGIC;
led:outSTD_LOGIC_VECTOR(7downto 0);
switch:inSTD_LOGIC_VECTOR(3downto 0));
endtutorial;

Input/Output definitions

architectureBehavioraloftutorialis
signalcounter:std_logic_vector(29downto 0);

counterdefinition

begin
process(clk)
begin
if(clk'Event andclk='1')then
if(switch(0)='1')then
counter<=counter+'1';
else
counter<=counter'1';
endif;
endif;
endprocess;
led(7downto 0)<=counter(29downto 22);

Counter counting up if switch is on, and counting

down if switch is off. Every addition occurs on every
positive clock edge.
edge
OutputofthetopbitsofcounteronLEDs

end Behavioral;
endBehavioral;

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WhenprogramiswrittenitssyntaxcanbecheckedbyexpandingSynthesize
and double clicking on Check Syntax If errors are found double click on
anddoubleclickingonCheckSyntax.Iferrorsarefound,doubleclickon
errorandcorrectthemistake.
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WhenalloftheerrorswerecorrectedandSynthesishasbeencompleted
successfullyanassignmentofinputsandoutputshastobedone.Since
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FPGAisalreadymountedonthedevelopmentplatforminputsandoutputs
arerestrictedandhavetobespecified.
Onlyonesthatareusedhavetobespecifiedintheconstraintfile.
Add new source same way as before but this time select Implementation
Addnewsourcesamewayasbefore,butthistimeselect
Implementation
ConstraintFile,andspecifynamefortheconstraintfile.
Press Next>

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UCFconstraintfileisaddedtotheVHDLfile.
Select constraint file and double click on Edit Constraints (Text)
SelectconstraintfileanddoubleclickonEditConstraints(Text)
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EnterconstraintsfortheLEDsandSwitchesthatarelocatedinthelower
right corner
rightcorner.
ClocksignalforallofthedesignsisconnectedtopinC9onFPGA
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Whencodeisdebuggedandconstraintfileiscorrectlyenteredwecan
generate a configuration file Right click on Generate Programming File and
generateaconfigurationfile.RightclickonGenerateProgrammingFileand
selectRun.
Similarlyasbefore,iferrorsoccur,doubleclickontheerrorandcorrectit.

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Ifconfigurationfileisgeneratedsuccessfullywecanloaditontothe
platform.
platform
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ExpandGenerateProgrammingFile,rightclickonConfigureDevice
(iMPACT) and select Run iMPACT wizardwindowwillopen.
(iMPACT)andselectRun.iMPACT
wizard window will open
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SelecttopoptionofconfiguringusingJTAGandpressFINISH.

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OntheinitialiMPACT loadwizardwillprompttoselectconfigurationfiles
for all of the devices present on the JTAG chain Press Esc keyforallofthe
forallofthedevicespresentontheJTAGchain.PressEsc
key for all of the
windows.RightclickontheleftdevicewhichrepresentsSpartan3EFPGA
andselectAssignNewConfigurationFile

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ToloadprogramontheFPGAdevice,rightclickontheFPGAiconandselect
Program Programming properties window will be shown
Program.Programmingpropertieswindowwillbeshown.
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OntheProgrammingPropertiesmakesureverifyisUNCHECKED.
Press OK atwhichpointconfigurationfilewillbeuploadedtoFPGA.
PressOK
at which point configuration file will be uploaded to FPGA
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Conclusion
Thiscompletesfirstsimpletutorialwhichincluded:
Creatingnewproject
Adding
AddingVHDLsourcefile
VHDL source file
Writingsimpleprograminvolvinginputsandoutputswithsimpleinternal
counter
Creatingconstraintfile
Generatingconfigurationfile
G
i
fi
i fil
UploadingconfigurationtoFPGAdevice
SecondtutorialcoversuseofinternalBlockRAM
f
andaChipscope
p p Proembedded
logicanalyzerwhichisrequiredforcompletionofallthelabsinthecourse.

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