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In a linear regulator, the power delivery is continuous. The regulating

components (like a transistor) in the converter work in the linear region,
which means that theres no abrupt voltage or current change for that
components (no switching). Therefore, the regulator tends to be more
quite (less noisy).
The linear regulators limitation of the efficiency is because of the fact that
the linear device must drop in voltage between the input and output. The
power dissipated by the linear device is (Vin-Vout) x Io. This leads to poor
efficiency when the difference between Vin and Vout is high.
However, the linear regulators have many desirable characteristics, such as
simplicity, low output ripple, excellent line and load regulation, fast
response time to load or line changes and low EMI.

The circuit shown here is a typical topology of a linear regulator with

feedback loop control.
In the circuit the feedback resistor R1, R2 and the error amplifier form a
sense/control circuit monitoring the output voltage that can control the
pass transistor to hold the voltage level.
The output voltage is sensed by R1 and R2 and applied to the inverting
input of the error amplifier as the feedback. The non-inverting input is a
reference voltage. The amplifier will constantly adjust its output to control
the pass transistors current so that the input voltages are equal.
If the output voltage is increased, the feedback voltage is raised following
it, and as a result the output of the amplifier will decrease and the
resistance of the transistor will increased. So the regulators output will
drop back to its normal level. If the output voltage is decreased, in the
similar way, the feedback loop will make it rise back. Therefore, the output
voltage can be maintained.

Dropout voltage is the minimum input-to-output voltage difference (drop)

for the linear regulator to hold the output voltage level. In other words,
the regulator cannot make its resistance smaller to increase the output
voltage further.

LDO stands for low dropout regulator, which has low dropout voltage
comparing to other non-LDO linear regulator.
In general, non-LDO uses emitter follower topology with NPN transistor or
Darlington pair as pass element (the two drawings on the left). Each NPN
transistor use in the regulator contributes a Vbe (base to emitter) voltage
drop (typically 0.7V ). In a result, the dropout voltage is high (1.5V to 2.5V).
It is good for applications that have large Vin-Vout difference, but the
efficiency is low.
LDO is configured in open-collector (PNP transistor) or open-drain (PMOSFET) topology, which makes the voltage drop as low as the saturation
voltage over the transistor (Vce or Vds, less than 1V). P-MOSFET LDO is
more common, as driving a PNP transistor more power is needed in the
control circuit.

The Vds is the drain-to-source voltage across the FET, which is the voltage
dropout from Vin to Vout.
The typical I-V curve of a FET shows how an LDO can control the resistance
of the FET. By changing the gate-source voltage (Vgs), the drain current will
be controlled in order to keep the output in regulation.
For example, an LDO operates at 5V Vin and 3.3V Vout and 500mA load
current. The FET is at point A, and Vgs should be equal to 3V. If the load
condition requires lower Vin-Vout voltage, the operation point on the plot
will shift towards left. But the FET has a minimum resistance limited by the
saturation line. The saturation line in the figure represents a resistance of
0.8Ohm, and the resistance required by point A is (5V-3.3V)/0.5A=3.4Ohm,
which is larger than saturation resistance. In other words, point A is on the
right side of the line, and the LDO can operate at that condition.
Note that the dropout will varies over temperature. Usually, the datasheet
gives a worse case graph showing dropout vs output current at different
temperature conditions.

Besides the input voltage and output voltage/current, the linear regulator
has some important parameters that need to be considered
Quiescent current is also called ground-pin current as the current flow to
ground within the regulator rather than reaching the load. It is measured
when the regulator working in no load condition.
PSRR indicates how well the linear regulator rejects ripples from the input
power source at a wide range of frequency. A higher PSRR means the input
noise can be better filtered out through the regulator before affecting the
output. It is usually a critical parameter in many RF and wireless
applications.

BROADBAND NOISE: Total noise energy over a specific frequency range is

used to specify broadband noise. Lower is always better, and low noise is
required for things like PLLs and sensitive analog circuitry. Low quiescent
current regulators can have higher noise because their reference is noisier
and contributes the main noise component.

LDOs are the best regulator when the difference between input and output
is small or load is low or the efficiency is a secondary concern compared to
the output noise, ripple, cost and solution size.
The table gives a summary of LDO characteristics and suggestions for
selection on an LDO.
LNA Low Noise Amplifier
PLL Phase Locked Loop
TCXO - Temperature Compensated Crystal Oscillators
IF Intermediate frequency

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