Limited Magnitude Error Locating Parity Check

Codes for Flash Memories

Myeongwoon Jeon , Sungkyu Chung , Beomju Shin and Jungwoo Lee
School of Electrical Engineering and Computer Science, INMAC
Seoul National University, Seoul 151-744, Korea
Hynix Semiconductor Inc., Icheon, Korea

Email: ifindme@wspl.snu.ac.kr , csungq@wspl.snu.ac.kr , beomju.shin@hynix.com , junglee@snu.ac.kr

AbstractNAND multi-level cell (MLC) flash memories are

widely used due to low cost and high capacity. However the
increased number of levels in MLC results in larger interference
and errors. The errors in MLC flash memories tend to be
asymmetric and with limited-magnitude. To take advantage of
the characteristics, we propose limited-magnitude parity check
codes, which can reduce errors more effectively. A key advantage
of the proposed method is that it has low complexity for encoding
and decoding. Another useful feature of the proposed method
is that the code rate and the block size can be chosen almost
continuously unlike conventional error correcting codes.

Fig. 1.

I. I NTRODUCTION
NAND flash memory has been used widely because of
the various digital information storage demand and portable
features. Recently multi level cell (MLC) flash memory has
been studied for improving memory capacity. Multi level
cell flash memory makes cell voltages be various levels and
puts two or more bits into a single cell. However error
increases rapidly with the number of levels in a cell because of
the interference caused by cell-to-cell coupling, temperature,
disturbance, and so on [1]. The conventional error correcting
codes (ECC) have been used for solving these problems, but
the ECC redundancy becomes larger rapidly as increasing the
number of levels in a cell.
MLC flash memory errors have asymmetry and limitedmagnitude. Various factors of interference lead to the threshold
voltage ( ) shift of the cell, and especially dominant factors
such as cell to cell interference increase . In flash memories, noise and interference mostly have limited amplitude,
and most errors occur between adjacent levels. With the
assumption of limited error magnitude of 1, one erroneous cell
causes only one bit error if gray code is employed in MLC
flash memories. The conventional error correction codes can
be inefficient for MLC flash memory because these codes are
constructed for all possible error types that error magnitude
and direction are random. Therefore we can use these MLC
flash memory error features for constructing efficient error correction codes. Error correction codes for asymmetric channels
with limited-magnitude error [2] [3], and coding schemes for
flash memory devices have been developed recently.
In this paper, we propose two new error correcting codes
which are effective for the interference. We assume that there
is at most one error in each code block, and the codes are
designed to correct one single error in a code block. Because

978-1-4673-2527-1/12/$31.00 2012 IEEE

The threshold voltage shift of multi-level cell flash memories.

the errors have limited magnitude, the remainder values which

are generated with modulo operation still contains the
error information. By taking advantages of the characteristics,
we introduce effective asymmetric and symmetric limitedmagnitude parity error correction codes for the MLC flash
memory error with lower redundancy. In the following section,
the threshold voltage shift phenomenon, and the interference
models are explained, and the directional limited-magnitude
errors are dealt with. We then propose new efficient error
correcting codes for MLC flash memory in Section III. Simulation results of the new algorithms are presented in Section
IV. Finally, we conclude the paper in Section V.
II. MLC F LASH M EMORY I NTERFERENCE AND ECC
A. Threshold voltage Shift and cell to cell interference
The threshold voltage ( ) is used to distinguish data levels
in MLC memory. Several factors may change the distribution
of the floating-gate threshold-voltage. One of the dominant
factors is the cell to cell interference, which is caused by
the change of the neighboring cells in the programming
(writing) operation. Fig. 1 illustrates the shift in the
4-level (two bit) MLC. The interference can be estimated
quantitatively by measurements or an interference model.
Fig. 2 shows an interference model based on the parasitic
capacitance between neighboring cells. Suppose that , ,
and are the cell voltages of the horizontal, the vertical, and
the diagonal neighbor cells, respectively. The interference in
terms of threshold voltage shift ( ) is given by
= (1 1 + 2 2 ) + (1 1 + 2 2 )
+ (1 1 + 2 2 + 3 3 + 4 4 )
(1)
where , , and are the coupling coefficients for the
horizontal, the vertical, and the diagonal neighbor cells, re-

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Fig. 3.
Fig. 2. Interference model based on parasitic capacitances in a NAND Flash
array.

Asymmetric limited-magnitude channel.

by = (1 , 2 , , ) and = (1 , 2 , , ). The
codewords can be modified by a modulus operation, i.e.,

= mod and = mod . Note that is

determined by the number of error types. If the maximum error
magnitude is and > , we have = ( ) mod .
We also have

spectively. One cell can only be interfered by its neighbor cells

which are programmed after this cell has been programmed.
has binary value, 0 or 1 and means whether the cell is
interfered by the th cell or not. The actual cell to cell interference model depends on the program order, page architecture,
and conventional LSB/MSB techniques [4], and these factors
are considered in the simulations.

= = ( ) mod
= ( mod mod ) mod
= (
) mod .

(2)
(3)
(4)

In other words, the error can be obtained from

and
, so the error information does not change by the modulo
technique. The -ary data can be converted into -ary data
by the modulo technique, and the redundancy for error
correction can be reduced [3]. The limited magnitude error
parity check (LMEPC) algorithm for asymmetric error using
modulo 2 is described as follows.

B. Asymmetric Channel and Limited Magnitude Errors

To reduce the error in MLC Flash memories, conventional
ECC techniques have been used. The conventional codes
are constructed for random, symmetric, and errors without
limited magnitude. However MLC flash memory errors have
several characteristics, which can be taken advantage of in
designing new codes. The cell-to-cell interference and the
corresponding shift have asymmetric property, and cause
the asymmetric errors. Asymmetric codes have been studied
for several decades [6]. The topic was studied initially for a
binary asymmetric channel (Z-channel). In a Z-channel, the
input and the output are binary, and 1 can be changed to 0
with probability , but 0 can not be changed to 1. Recently
many asymmetric codes for MLC flash memories have been
studied [3]. These codes can also consider other characteristics
of MLC flash memories. In MLC memories, most errors have
limited magnitude since the threshold voltage shift tends to be
small. We assume that the error level magnitude is limited to
1 in constructing new error correcting codes in this paper.

LMEPC Mod 2 Algorithm for Asymmetric Errors

(Initialization) The q-ary data:

= {1,1 , 1,2 , . . . , 1, , 2,1 , . . . , , }.
1)
Get the remainder of message by modulo 2.
= {1,1 , 1,2 , . . . , , } where , = , mod

2.
2)
Generate the parity codes for each row and col} where =
umn.

= { } and = {
( =1 , ) mod 2 and = ( =1 , ) mod 2.
3)
Store the message data and parity check codes.
Parity codes are converted to q-ary data,
, where and are -ary
version of and .
, , and are stored separately.

(Initialization) The q-ary received data and parity

information with interference and hard decision:
= {1,1 , 1,2 , . . . , ,1 , , }, , .
The -ary parity cell data is converted back to binary
data: = { }, = { }.
1)
Get the remainder of received message by mod 2.
= { 1,1 , 1,2 , . . . , , } where , =

III. PARITY C HECK C ODES FOR E RRORS WITH L IMITED

M AGNITUDE
A. Parity Check Codes for Errors with Limited Magnitude:
Asymmetric Error
We propose efficient error correcting codes for limitedmagnitude errors in MLC Flash memories. At first, asymmetric
limited-magnitude errors are considered. Fig. 3 (a) shows
an example of 4-level (X2) asymmetric limited-magnitude
channel, where the error magnitude is limited 1. Let us
consider a case where the error is asymmetric.
Suppose that and is the -ary input and output
codeword, respectively. The codewords can be represented

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codes. The code rate can be adjusted continuously by adjusting

the data block size. If there are rows and columns in a
data block, there are message cells for 2 -level MLC. The
code rate is given by
=

.
+
+

(5)

If equals , then the code rate is maximal. One parity

block can correct one error, so the code rate can be determined
considering error correction capability.
B. Error Parity Check Codes with Limited Magnitude: Symmetric Error

Fig. 4.

2)

3)
4)

Although the cell-to-cell interference which produces

upward errors is a dominant factor for the errors in MLC
flash memories, there are other types of noise such as
symmetric (random-telegraph noise) and downward (retention
noise and stress induced leakage current) interference, which
may be less significant [4]. In practice, the read voltage for
NAND flash memories is made based on the distribution
after (not before) the cell-to-cell interference takes effect,
which means the read voltage is near-optimal. Therefore to
improve the BER performance, symmetric errors need to be
considered. Even if the errors are symmetric, the magnitude
of the errors is still limited. Fig. 3 (b) shows the 4-level (X2)
MLC channel with symmetric errors. We use a modulo-3
technique which can correct two types of errors (upward and
downward). In theory, it is possible to correct 1 error
types by using a modulo- technique. The modulo-3 based
encoding and decoding methods by the limited magnitude
error parity check (LMEPC) algorithm are given as follows.

Error correction process of asymmetric limited-magnitude errors.

, mod 2.
Generate the parity codes of the received data for
each row and column.

} and = {

} where =
= {

( =1 , ) mod 2 and = ( =1 , ) mod 2.

Check the parity and obtain the location of error.
If = & = , the error location is , .
Correct the asymmetric upward error, , = , 1.

LMEPC Mod 3 Algorithm for Symmetric Errors

The original message set is denoted by , which consists

of -ary cell messages (, ). The remainder set of ,
The row parity and the column parity
is denoted by .

are generated from . The received message data, the

row parity check codes, and the column parity check codes
are denoted by , , and , respectively. It is assumed
that at most one asymmetric error of magnitude one occurs.
When an error occurs in the data set , the error location can
be identified by the given parity check algorithm. Suppose an
error occurs in one of the cells storing the check bits. Since
the decoding algorithm will make a correction if it detects an
error in both of the row and the column parity, the data bits
will not be affected by the decoding algorithm.
Errors usually occur in the programming (writing) operation, and the stored parity check codes can be used after the
reading operation to locate the errors. The following is an
example of 8-level (X3) limited-magnitude parity check codes.
This parity check codes correct asymmetric errors using the
mod 2 technique. Fig. 4 shows an example of the parity check

1)

2)

3)

(Initialization) The q-ary data:

= {1,1 , 1,2 , . . . , 1, , 2,1 , . . . , , }
Get the remainder of message by modulo 3.
= {1,1 , 1,2 , . . . , , } where , = , mod

3.
Generate the parity codes for each row and column.

= { } and = {
} where =

( =1 , ) mod 3 and = ( =1 , ) mod 3.

Store the message data and the parity check codes.
Parity codes are converted to q-ary data,
, .

(Initialization) The -ary received data and parity

codes with interference and hard decision:
= {1,1 , 1,2 , . . . , ,1 , , }, , .
The -ary parity cell data is converted back to binary
data:
= { }, = { }.

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2)

3)
4)

Get the remainder of received message by mod 3.

= { 1,1 , 1,2 , . . . , , } where , =

, mod 3.
Generate the parity codes of the received message
data for each row and each column.

} and = {

} where =
= {

( =1 , ) mod 3 and = ( =1 , ) mod 3.

Check the parity and obtain the location of error.
If = & = , the error location is , .
Decide the type of error and make a correction.
If ( ) mod 3 = 2, an upward error occurs
and , , 1.
If ( ) mod 3 = 1, a downward error occurs
and , , + 1.

No ECC
Limited Error Parity Check (Asymmetric)
Limited Error Parity Check (Symmetric)

10

BER

1)

10

10

0.84

0.86

0.88

0.9

0.92

0.94

0.96

0.98

Code Rate

Fig. 5. BER plot of the asymmetric and symmetric limited-magnitude error

parity check codes.

Unlike the example of Fig.4, data 6 can be changed

erroneously to 5 or 7 in the symmetric error case, and we
can determine whether the error is upward or downward by
using mod 3 parity check methods. If we use entropy coding,
a ternary parity symbol {0, 1, 2} can be represented by log2 3
bits which is optimal. If there are rows and columns in
a data block, the corresponding code rate is upperbounded
by

(6)

.
+ log2 3
+ log2 3

V. C ONCLUSION
To reduce errors of the MLC flash memories, we propose
two new error correcting codes by taking advantage of limited
magnitude of errors. One deals with asymmetric errors, and the
other with symmetric errors. These new error correcting codes
use a two dimensional parity check structure with modulo
operations. One of the key advantages of the proposed method
is that it has low encoding/decoding complexity compared to
conventional correcting codes such as the BCH codes. Another
notable advantage is the flexibility in choosing the code rate
and the block size.

If is equal to , the code rate is maximal as expected. The

proposed LMEPC methods have advantages in terms of computational complexity of encoding and decoding processes.
The decoder complexity (BCH ) of the BCH codes has the
order of ((log2 ())2 ) [7], and it can be easily shown
that the decoder complexity (LMEPC ) of the proposed
LMEPC codes has the order of (). For a large block
size ( 1), we have LMEPC BCH .

ACKNOWLEDGMENT
This research was supported in part by Hynix Semiconductor Inc., Basic Science Research Program (2010-0013397) and
Mid-career Researcher Program (2010-0027155) through the
NRF funded by the MEST, and INMAC, BK21.

IV. S IMULATION R ESULTS

R EFERENCES

We simulated the two proposed error correction codes.

One is the asymmetric limited magnitude parity check codes
(mod 2) for asymmetric errors, and the other is the symmetric limited magnitude parity check codes for symmetric errors
(mod 3). Bit error rate (BER) is used as the performance
measure. We simulate the algorithm for a 8-level flash memory
model(3 bits in a cell).
Fig. 5 shows the BER performance of limited-magnitude
parity check codes for asymmetric errors. As the code rate
decreases, the data block size gets smaller and the error
correction improves. However the bit error rate of the asymmetric codes stays almost the same when the code rate is
below 0.95. Because the adjusted hard-decision reference
voltage compensates the upward shift by the cell to cell
interference, which makes the errors more symmetric rather
than asymmetric. These symmetric codes reduce the bit error
rate by a factor of about 103 compared to the no ECC case
at a low code rate, which depends on the interference and the
noise model used in the simulations.

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