Logic gates

DIET-Dept of ECE

Experiment No:
Date:

1. LOGIC GATES
AIM:
To Verify the truth tables of AND, OR, NOT, NAND, NOR, EX-OR logic
gates using ICS.
APPARATUS:
1. Bread board Digital IC trainer kit

1 No.

2.
3.
4.
5.
6.
7.
8.

1 No.
1 No.
1 No.
1 No.
1 No.
1 No.

IC 74LS08 (AND)
IC 74LS32 (OR)
IC 74LS04 (NOT)
IC 74LS00 (NAND)
IC 74LS02 (NOR)
IC 74LS86 (EX-OR)
Connecting wires

THEORY:

AND gate: If two or more operands are ANDed, then the result will be logic 1 only if
all the operands are 1.A . Sign is used to represent the AND operation. If A and B are the
logic operands and Y is the result of the AND operation, then Y is 1(TRUE) only if both A
AND B are 1(TRUE). For all other combinations of the inputs, Y is 0(FALSE). The
expression for AND operation is given as Y=A. B.
OR gate: If two or more operands are ORed, then the result will be logic 1 if any of
the operands is a logic1. A + Sign is used to represent the OR operation. If A and B are the
logic operands and Y is the result of the OR operation, then Y is 1(TRUE) if either A OR B is
1 (TRUE). Y is 0 (FALSE) only when both A and B are 0. The expression for OR operation is
given as Y=A + B.

2013-17

DIET-Dept of ECE

Logic gates

NOT gate: The NOT operation corresponds to complementing the input variable. In
this there could be only one input and one output and the output is NOT the input. If the input
is 1 (TRUE) then the output is 0 (FALSE) and if the input is 0, the output is 1. The NOT
operation is given by the expression Y = .
NAND gate: NAND gate is the gate indicating NOT AND i.e., the output of the
NAND gate will be the complement of the output of the AND gate. This is shown in the table
1.1. In the table, A and B are the inputs, Y corresponds to the output of an AND gate and Y
corresponds to the output of a NAND gate. It can be seen that the output of the NAND gate
is the complement of that of the AND gate.
The NAND operation is given by the expression
NOR gate: NOR gate is the gate indicating NOT OR i.e., the output of the NOR gate
will be the complement of the output of the OR gate. This is shown in the table 1.1. In the
table, A and B are the inputs, Y corresponds to the output of an NOR gate. It can be seen that
the output of the NOR gate is the complement of that of the OR gate. The NOR operation is
given by the expression
X-OR gate: The X-OR logic is different from other gates whose output is one, only
when the applied inputs are different i.e., it is an odd function and is one when it contains
odd number of ones.
So, at A=0, B=1 or A=1, B=0 the output of X-OR is 1.

2013-17

DIET-Dept of ECE

Logic gates

CIRCUIT DIAGRAMS:

2013-17

DIET-Dept of ECE

2013-17

Logic gates

DIET-Dept of ECE

2013-17

Logic gates

DIET-Dept of ECE

Logic gates

TRUTH TABLES AND OBSERVATION TABLES:

Table 1.1: Truth tables and observation tables for logic gates

PROCEDURE:
1. +5V DC is applied at Vcc (pin no 14) of each IC w.r.t ground (pin no7).
2. I/Ps are applied (at pin nos l&2) and output is taken from (pin no 3).
3. I/Ps are applied from toggle switches and o/p is observed at o/p indicators.

2013-17

Logic gates

DIET-Dept of ECE

PRECAUTIONS:
1. The open circuit voltage of the power supply must be stable and close to 5V.
2. Correct components should be connected on the bread board with proper
polarities.
3. A multimeter reading greater than VDD indicates an open connection in the
circuit. Verify the circuit before proceeding.
4. Use multimeter probe tip to gently ease the IC out of breadboard. The midsection groove of the breadboard can be used to gently lift the IC. Using bare
hands might cause IC pins to break.
5. In case the logic gate outputs do not make sense, check your circuit
thoroughly. If the problem is still not resolved, get the IC tested by the
technician.
RESULT:
Verified the truth tables of AND, OR, NOT, NAND, NOR, EX-OR gates
using ICS.
VIVA QUESTIONS
1) What changes should be made in the above circuits for negative logic?
2) Explain how NOT gate acts as inverter?
3) Draw IEEE rectangular shape symbols for logic gates.
4) How is average power dissipation in a logic gate calculated?
5) Define noise margin. Draw a visual representation of noise margin idea.

*****

2013-17