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CHAPTER 1
INTRODUCTION
1.1 INTRODUCTION TO VLSI :

Very-large-scale integration (VLSI) is the process of creating an integrated circuit by combining


thousands of transistors into a single chip. VLSI began when complex

semiconductor

and communication technologies were being developed. Before the introduction of VLSI
technology most ICs had a limited set of functions they could perform. An electronic
circuit might consist of a CPU, ROM, RAM and other peripherals; VLSI lets IC makers add all
of these into one chip. The first semiconductor chips held two transistors each. Subsequent
advances added more transistors, and as a consequence, more individual functions or systems
were integrated over time. The first integrated circuits held only a few devices with
ten diodes, transistors, resistors and capacitors making it possible to fabricate one or more logic
gates on a single device. The fabrication of ICs began with Small Scale Integration (SSI),
improvements in technique led to devices with hundreds of logic gates, known as Medium Scale
Integration (MSI), followed by thousands of logic gates called Large Scale Integration (LSI).
Current technology has moved far past this mark having many millions of transistors fabricated
on single chip known as Very large Scale Integration (VLSI).In the course of enhancement of
technology suitable softwares like VHDL were developed during electric circuit design to work
in real time applications for military purpose by the USA. VHDL an acronym for VHSIC
hardware description language (VHSIC is an acronym for Very High Speed Integrated circuits ).
It is a hardware description language that can be used to model a digital system at many levels of
abstraction, ranging from algorithm level to gate level. It contains elements that can be used to
describe the behavior or structure of the digital system, with the provision for specifying its
timing explicitly and supporting system hierarchy

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1.2 . ADVANTAGES OF VLSI:


Very Large Scale integration is a method of putting the functionality of many different types of
electronic components into a small space or chip

Reduces the Size of the device

Reduces the cost of the device

Reduces the power consumption

Increases the Speed of operation

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CHAPTER 2
BLOCK DIAGRAM
LFSR is widely used as test pattern generator because of its small circuit area and excellent
random characteristics. The proposed architecture consists of a seed generator (SG) with LFSR,
a n-bit counter, a Gray encoder and an exclusive-OR array. The n-bit counter and Gray encoder
generate single input changing patterns.

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Working:
According to the design the proposed structure of TPG C[n-1:0] is the counter output and G[n1:0] is the gray encoder output. The counter and SG are controlled by test clock TCK. The initial
value of the n-bit counter is all zeroes, and it generates 2n continuous binary data periodically.
The output of NOR operation of C[m-1:0] will be the clock control signal of SG where m<=n. It
can be found that SG will generate the next seed only when C[m-1:0] are all 0 and NOR output
changes to 1. The period of the single input changing sequences will be 2m.Gray encoder in
Fig. 1 is used to encode the counters output C[n-1:0] so that two successive values of its output
G[n-1:0] will differ in only one bit. Gray encoder can be implemented by following logic.
G[0] = C[0] XOR C[1]
G[1] = C[1] XOR C[2]
G[2] = C[2] XOR C[3]
.
G[n-2] = C[n-2] XOR C[n-1]G[n-1] = C[n-1] The seed generating circuit SG is a modified
LFSR. The theory stated that the conventional LFSRs outputs cant be taken as the seed directly
because some seeds may share the same vectors. So the seed generator circuit should make sure
that any two of the signal input changing sequences do not share the same vectors or share as few
vectors as possible. The final test patterns are implemented as following logic.
V[0] = S[0] XOR G[0]
V[1] = S[1] XOR G[1]
V[2] = S[2] XOR G[2]

V[n-1] = S[n-1] XOR G[n-1]


The Seed Generators clock will be TCK/2m due to the control signal. As SICGs cyclic
sequences are single input changing patterns, the XOR result of the sequences and a certain
vector must be a single input changing sequence too. The circuit structure of single input
changing generator (SICG), consists of an n-bit counter and a Gray code encoder. The n-bit
counter consists of n D flip-flops and the gray encoder consists of n-1 exclusive-OR gates.
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BLOCK DIAGRAM DESCRIPTION:


2.1 Linear Feedback shift Register (LFSR):
A linear feedback shift register (LFSR) is a shift register whose input bit is a linear function of its
previous state. The most commonly used linear function of single bits is XOR. Thus, an LFSR is
most often a shift register whose input bit is driven by the exclusive-or (XOR) of some bits of the
overall shift register value.
The initial value of the LFSR is called the seed, and because the operation of the register is
deterministic, the stream of values produced by the register is completely determined by its
current (or previous) state. Likewise, because the register has a finite number of possible states, it
must eventually enter a repeating cycle. However, an LFSR with a well-chosen feedback
function can produce a sequence of bits which appears random and which has a very long cycle.
.
Linear feedback shift registers make extremely good pseudorandom pattern generators. When the
outputs of the flip-flops are loaded with a seed value (anything except all 0s, which would cause
the LFSR to produce all 0 patterns) and when the LFSR is clocked, it will generate the test
patterns necessary for the clock and a pseudorandom pattern of 1s and 0s.

2.1.1 Circuit Diagram

FIG. LINEAR FEED BACK SHIFT REGISTER

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2.2 GRAY CODES:


A Gray code is an encoding of numbers so that adjacent numbers have a single digit differing by
1. The term Gray code is often used to refer to a "reflected" code, or more specifically still, the
binary reflected Gray code. Code is a symbolic representation of discrete information. Codes are
of different types. Gray Code is one of the most important codes. It is a non-weighted code
which belongs to a class of codes called minimum change codes. In this codes while traversing
from one step to another step only one bit in the code group changes. In case of Gray Code two
adjacent code numbers differs from each other by only one bit. The idea of it can be cleared from
the table given below:

Decimal Number

Binary Code

Gray Code

0000

0000

0001

0001

0010

0011

0011

0010

0100

0110

0101

0111

0110

0101

0111

0100

1000

1100

1001

1101

10

1010

1111

11

1011

1110

12

1100

1010

13

1101

1011

14

1110

1001

15

1111

1000

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To convert a binary number d_1d_2...d_(n-1)d_n to its corresponding binary reflected Gray


code, start at the right with the digit d_n (the nth, or last, digit). If the d_(n-1) is 1, replace d_n
by 1-d_n; otherwise, leave it unchanged. Then proceed to d_(n-1). Continue up to the first digit
d_1, which is kept the same since d_0 is assumed to be a 0. The resulting number g_1g_2...g_(n1)g_n is the reflected binary Gray code.

2.2.1 Circuit Diagram:

2.2.2 Advantages of gray codes:

power consumption and decoding logic is less

Helps to reduce the digital noise issue for counter application.

used as a counter, changes only one bit, so it is glitch free

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CHAPTER 4
SOFT WARE TOOLS
This Chapter deals with the Software tools used in this Application
4.1 XILINX SOFTWARE:
Xilinx ISE(Integrated Software Environment) is a software tool produced by Xilinx for Synthesis
and analysis of HDL designs ,enabling the developer to synthesize(compile) their designs,
perform timing analysis ,examine RTL diagrams, simulate a designs reaction to different
stimuli, and configure the target device with the programmer

4.2 Steps to write program in Xilinx on VHDL environment

Create New project from File menu

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Give the file name

Select options as shown below

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Press Next two times in the follow-up window and then finish at last
Select New source by clicking on project in source window as shown below

Select VHDL module and name the file .Then click next

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Give port declaration as we do in entity .Then click Next and then hit Finish

VHDL Code with entity and libraries are present on the screen, Now we just have to
write the code in architecture

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Select New Source by clicking on the project in Source script and then select Test Bench
waveform and name the file .Then click Next and then select the file for which u would
like to write the test bench and then finish

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A new window appears as shown below .For combinational circuits select combinational
clock

Change the source type to behavioral in the source box and from the process window
simulate the file

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The simulation output is observed at last

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CHAPTER-5
IMPLEMENTATION
In our project we are going to implement test pattern generator by using LFSR . The power
dissipation of the test pattern generator mainly depends on the switching activities. So mainly we
concentrate on reducing the switching activities from one pattern to the other pattern. We in our
project are going to implement 8 bit pattern generator.
8 BIT PATTERN GENERATOR:
An 8bit pattern generator is used to generate 8bit single bit changing output. We are going to
implement 8bit lfsr , 8bit gray code counter, along with clock gating circuit for this pattern
generation. LFSR generate a random pattern for every clock pulse depending on the input seed.
Whenever the seed is changed the LFSR patterns differs from the previously generated patterns.
Gray code counter is used for generation of single bit changing sequences. These are generated
from the binary count value. The clock gating circuitry is a clock enabling circuit which provides
the clock input to the LFSR. This clock is activated for every 256 clock pulses. Thus LFSR
generates a pattern for every 256 clock pulses .this is a low power technique for generating Low
power TPG using lfsr. The output of lfsr is Ex-ored with the gray code counter which in turn
generates a random single bit changing pattern. In similar way we generate another 8bit pattern
by changing seed of the LFSR.

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5.1 VHDL CODE FOR 8BIT GRAY CODE GENERATOR:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gray code is


generic(n:integer:=8);
port( rst,clk:in std_logic; bin_count:out std_logic_vector(n-1 downto 0);
y: out std_logic_vector(n-1 downto 0));
end gray_code;

architecture Behavioral of gray_code is


signal count:std_logic_vector(n-1 downto 0):="00000000";

begin
process(rst,clk)
begin
if rst='1' then
count <= (others =>'0');
elsif clk'event and clk='1' then
count<= count+'1';
end if;
end process;
bin_count<=count;
y <= count(7)&(count(7) xor count(6))&(count(6) xor count(5))&(count(5) xor count(4)) &
(count(4) xor count(3)) & (count(3) xor count(2)) & (count(2) xor count(1)) & (count(1) xor
count(0));
end Behavioral;
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5.2 VHDL CODE FOR 8 BIT LFSR (LINEAR FEEDBACK SHIFT


REGISTER):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity LFSR_3_16_2013 is
port(
clk:
in std_logic;
rst:
in std_logic;
pseu_rand: out std_logic_vector(7 downto 0));
end LFSR_3_16_2013;
architecture Behavioral of LFSR_3_16_2013 is
--signal clk: std_logic;
--signal rst: std_logic;
signal seed: std_logic_vector(7 downto 0):= "10000000";
signal biffer: std_logic_vector(7 downto 0);
--signal pseu_rand: std_logic_vector(7 downto 0);
begin
lfsr : PROCESS(clk,rst)
begin
if(rst='1') then
--pseu_rand <= seed;
biffer <= seed;
pseu_rand <= biffer;
elsif (clk'event and clk='1') then
biffer(0) <= biffer(7) xor biffer(6);
biffer(7 downto 1) <= biffer(6 downto 0);
pseu_rand <= biffer;
end if;
end process lfsr;
end Behavioral;

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5.3 VHDL CODE FOR CLOCK GATING :
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clk_gen1 is
port(clk,rst:in std_logic;
--temp:in std_logic;
clkout:out std_logic);
end clk_gen1;

architecture Behavioral of clk_gen1 is


component gray_code is
generic(n:integer:=8);
port(rst,clk:in std_logic;
bin_count:out std_logic_vector(n-1 downto 0);
y: out std_logic_vector(n-1 downto 0));
end component;
signal ctr:std_logic;
signal bin_count:std_logic_vector(7 downto 0);
signal y:std_logic_vector(7 downto 0);
signal clkout1:std_logic;
begin
uut:gray_code generic map(8) port map(rst,clk,bin_count,y);
process(clk,rst)

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begin
if rst='1' then
ctr<='0';
elsif clk'event and clk='1' then
if bin_count="00000000" then
ctr<='1';
else ctr<='0';
end if;
end if;
end process;
clkout <=ctr;
end Behavioral;

5.4 8 BIT SHIFT ALU:


We are going to implement 8bit efficient arithmetic operations using alu . The two inputs to the
alu are given by the two pattern generator outputs that are generated. The inputs to the alu are
single bit changing inputs so the alu implemented will consume less power compared to the other
implementations.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity alu1 is
port( clk,rst:in std_logic; alu_in1 : in std_logic_vector(7 downto 0) ;
alu_in2 : in std_logic_vector(7 downto 0) ; alu_fun : in std_logic_vector(3 downto 0) ;
cin : in std_logic ; alu_out : out std_logic_vector(7 downto 0));
end alu1;
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architecture arch1 of alu1 is


begin
process(alu_fun,alu_in1,alu_in2,cin)
begin
case alu_fun is
when "0000" => alu_out <= alu_in1 and alu_in2;
when "0001" => alu_out <=alu_in1 xor alu_in2;
when "0010" => alu_out <= alu_in1 - alu_in2;
when "0011" => alu_out <= alu_in2 - alu_in1;
when "0100" => alu_out <= alu_in1 + alu_in2;
when "0101" => alu_out <= alu_in1 + alu_in2 + cin;
when "0110" => alu_out <= alu_in1 - alu_in2 - not(cin);
when "0111" => alu_out <= alu_in2 - alu_in1 - not(cin);
when "1000" => alu_out <=alu_in1 or alu_in2;----ORR
when "1001" => alu_out <= alu_in1 and not(alu_in2);---BIC
when "1010" => alu_out <= not(alu_in1);---------not of input1
when "1011" => alu_out <= not(alu_in2);---------not of input2
when others => alu_out <= (others => 'Z');
end case;
end process;
end arch1;

5.5 VHDL CODE FOR 8 BIT TEST PATTERN GENERATOR :


library ieee;
use IEEE.STD_LOGIC_1164.ALL;
entity pattern_bit_2 is
port(clk,rst:in std_logic;
pattern_out:out std_logic_vector(7 downto 0));
end pattern_bit_2;

architecture Behavioral of pattern_bit_2 is


component clk_gen1 is
port(clk,rst:in std_logic;
--temp:in std_logic;
clkout:out std_logic);
end component;

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component gray_code is
generic(n:integer:=8);
port(rst,clk:in std_logic;
bin_count:out std_logic_vector(n-1 downto 0);
y: out std_logic_vector(n-1 downto 0));
end component;

signal bin_count:std_logic_vector(7 downto 0);


signal y:std_logic_vector(7 downto 0);

component LFSR_11_16_2013 is
port(
rst:

clk:

in std_logic;

in std_logic;

pseu_rand: out std_logic_vector(7 downto 0));


end component;

signal pseu_rand:std_logic_vector(7 downto 0);


signal sig_clk:std_logic;

begin
uut:clk_gen1 port map(clk,rst,sig_clk);
uut2:LFSR_11_16_2013 port map(sig_clk,rst,pseu_rand);
uut3:gray_code port map(rst,clk,bin_count,y);

pattern_out<=pseu_rand xor y;
end Behavioral;

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5.6 VHDL CODE FOR 8BIT TOP LEVEL MODULE :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top_fm57_8bit is
Port ( clk : in STD_LOGIC; rst : in STD_LOGIC;
patt_out1 : out STD_LOGIC_VECTOR (7 downto 0);
patt_out2 : out STD_LOGIC_VECTOR (7 downto 0);
product_out:out std_logic_vector(15 downto 0));
end top_fm57_8bit;

architecture Behavioral of top_fm57_8bit is


component bit_multiplier is
port(

num1, num2: in std_logic_vector(7 downto 0);

product: out std_logic_vector(15 downto 0)


);
end component;

component pattern_bit is
port(clk,rst:in std_logic;
pattern_out:out std_logic_vector(7 downto 0));
end component;

component pattern_bit_2 is
port(clk,rst:in std_logic;
pattern_out:out std_logic_vector(7 downto 0));
end component;

signal temp_out1:std_logic_vector(7 downto 0);


signal temp_out2:std_logic_vector(7 downto 0);
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begin

uut1:pattern_bit port map(clk,rst,temp_out1);


uut2:pattern_bit_2 port map(clk,rst,temp_out2);
uut3:bit_multiplier port map(temp_out1,temp_out2,product_out);

patt_out1<=temp_out1;
patt_out2<=temp_out2;
end Behavioral;

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CHAPTER 6
SIMULATION RESULT

Modelsim Tool for Seeing the Simulation Flow of the Project:


1. Open the Modelsim 6.2c simulator software to

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2. Go to File Option and choose the correct Code path from the Change directory option

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3. Select the Project code path from the displayed window. And click Ok. It will go the source
directory.

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4. Open the Top level code from the open option in the File tab. It opens the code of that module.

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5. Then we should open script do files present in directory by typing the pwd (present working
directory) in the transcript window.

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6. Then we should open script do files present in directory by Typing the dir * do in the
transcript window.

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7. It opens the All Do files written in the project. Then select the fine named as do build.do and
copy the Transcript window with do as prefix (do build_tb_fault_new.do). Do build.do is a script
file which compiles all the modules that are involved in the given directory .

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8. After running the build.do script file, the simulation results of the project will be displayed.

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9. These are The Total simulation results of the 8 bit test pattern generator.

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The Total simulation results which consists of the signal as:


Clk

-- For synchronization purpose (sequential we use clock for digital operation).

Rst

-- For reset all signals to initial position and start from new next rising edge of the

clock.
Pattern_out1: This is the output from the low power Test pattern generator . it is a single bit
changing pattern with reduced switching activities. It is given as an input to the multiplier.

Pattern_out2: This is the output from the Test pattern generator . It is a single bit changing
pattern with reduced switching activities . It is given as second input to the 8 bit multiplier or
ALU.
Product: This is a final output for the 8bit . We are implementing 4bit shift add multiplier with
the input taken from the pattern generators.
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Block diagram for test pattern generator :

Above figure shown is the block diagram for N bit test pattern generator. Here Gray code is used
for reducing the switching activities and LFSR is used for random pattern generation scheme.
Additional to this we are going to implement Clock gating technique.
The new clock is generated depending on the binary count. For a 4 bit pattern generation new
clock is generated for every 16 clock pulse. In the similar manner for 8 bit pattern generation
new clock is generated for every 256 clock pulses.

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The signals under Pattern generation 1 are shown below:


Clk

-- For synchronization purpose (sequential we use clock for digital operation).

Rst

-- For reset all signals to initial position and start from new next rising edge of the

clock.
Pseu_rand: This is the LFSR (linear feedback shift register) output. It is activated for every 16
clock pulses. so a new pattern will be generated for every 16 clk pulses.
Y: this signal gives the output of gray code counter
Sig_clk: This is the clock gated signal given as an input clock for LFSR. So LFSR is triggered on
the Rising edge of this clock.
Pattern out : This signal is the output of the LP-Test pattern generator. By applying XOR
operation on Pseu_rand and Y, this output is obtained which is a single bit changing pattern.

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Other pattern generator is implemented in the similar manner as explained above except the
Initial seed in the lfsr is modified to generate the different patterns. The simulation results for 8
Bit LFSR, Gray code counter, Binary counter , multiplier are shown below.

Binary counter :

Linear feedback shift register :

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8 Bit ALU :

Test pattern Generator :

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CHAPTER-7
ADVANTAGES,DISADVANTAGES AND APPLICATIONS
ADVANTAGES:

Economical

Fault Coverage

Controllability

Obsevability

DIS ADVANTAGES:

Test pattern generation can be extremely time-consuming, particularly for sequential


circuits

A good deal if storage is required by the tester to hold the testpatterns.

A speed at which test can be applies is limited

APPLICATIONS:

Pattern Generators

Counters

Built-in Self-Test (BIST)

Encryption

Compression

Checksums

Pseudo-Random Bit Sequences (PRBS)

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CHAPTER:8
FUTURE SCOPE AND CONCLUSION

Future scope:

Concept of LFSR and Cellular automata can be combined in order to get better degree
of randomness and cover more number of faults with few number of patterns

Conclusion:
An efficient test pattern generator (TPG) method had been proposed to reduce the test power and
uses a modified pseudo-random pattern generator to produce seeds and then operates with the
single input changing generator and an exclusive-OR array, thus pseudo-random signal input
changing sequences are generated, which greatly minimize circuit switching activities and test
power. The experimental result shows 30.87% reduction in test power. Test Pattern generator
also reduces the instantaneous power violation compared to conventional LFSR

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CHAPTER 9
REFERENCES

Resources from New Wave Instruments and Xilinx


Digital Logic Design by Morris Mano
Balwinder Singh, Arun khosla and Sukhleen Bindra Power
Optimization of linear feedback shift register(LFSR) for low power
BIST, 2009 IEEE international Advance computing conference (IACC
009) Patiala, India 6-7 March 2009.

BOYE and Tian-Wang Li, A novel BIST scheme for low power
testing, 2010 IEEE.
www.Wikipedia.com
http://www.hindawi.com/journals/vlsi/2011/948926/

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