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D Is Inside
52 Isolation MOSFET-driver IC
Figure 1 The behavior of the RC topology is still simple when you replace R
with an active circuit that synthesizes a negative resistance.
R1
14.3k
VIN
R4
2k
11 T=14.4 SEC
13 X1 A
14
10
X
12
LT1214
X0
9
1/
MAX4053
3
C
0.001 F
R2
28.7k
VOUT
TO ADC
AMPLIFY/
TRACK
R3
28.7k
Figure 2 The divergent-exponential and negative time constants are the core
concepts of the DENT (divergent-exponential-negative-time-constant) DPGA
edn080821di42882 DIANE
topology.
50 Circuit indicates
ac-mains-fuse failure
gets improved power efficiency
at lighter loads
with hyperbolic taper
designideas
VIN/8 at 3T, and so forth. Less familiar, but just as simple, is the behavior
of the same RC topology when you
replace R with an active circuit that
synthesizes a negative resistance (Figure 1). Replacing R with 2R makes
the RC time constant negative: 2RC
and the waveform function yield the
divergent exponential, VIN3e1t/RC.
Then, instead of converging to zero,
the waveform diverges theoretically
to infinity, and V52VIN at t5T, 4VIN
at 2T, 8VIN at 3T, and so forth. Therefore, no matter how small the input
voltage might be, you can amplify it
as much as you desire to any voltage
by simply waiting the right amount of
time5t5log2(V/VIN)T after starting
the negative discharge.
The divergent-exponential and
negative time constants are the core
concepts of the DENT (divergentexponential-negative-time-constant)
DPGA topology (Figure 2). When
the amplify/track-control bit goes to
logic one, the two-times-noninverting
gain of the op-amp follower creates a
negative time constant: 2(R11RON)
(C1CSTRAY)5214.4 msec, where RON
is the on-resistance of the CMOS
switch, and CSTRAY is the parasitic capacitance surrounding C (Figure 3).
It also creates a diverging exponential: VOUT(t)5VIN32(t/10 msec11). Thus,
gain52(t/10 msec11). The 1-msec timing
resolution in the amplify-control bit
provides 1.07-to-150.6 dB533 steps/
decade gain-programming resolution.
Figure 4 graphs the voltage gain versus the time elapsed since the track/
amplify-logic transition.
Unlike monolithic PGAs, DENT
uses discrete components, such as op
SAMPLE AND
CONVERT
VOUT
T=R4C
T=R1C
TRACK
AMPLIFY
2VIN
AMPLIFY/TRACK
EDN080821DI4288FIG3
AMPLIFY
MIKE
Figure 4 This graph shows the voltage gain versus the time elapsed since the
track/amplify-logic transition.
amps and switches, so it can easily accommodate parameters such as I/Ovoltage spansnegative inputs and
10V amplitudesby choosing appropriate parts and power supplies. The
accuracy and repeatability of the timing of exponential generation, ADC
sampling, and RC-time-constant stability limit the practical performance
of the amplifier in gain-programming
accuracy and jitter. In the sample circuit, with T514.4 msec, 1 nsec of amplify-timing error or jitter equates to
TRACK
Figure 3 When the amplify/track-control bit goes to logic one, the two-timesnoninverting gain of the op-amp follower creates a negative time constant.
SAMPLE AND
CONVERT
designideas
age, and bridge diode D1 rectifies the ac
voltage. Resistor R1 limits inrush current when capacitor C1 is discharged.
Zener diode D2 and capacitor C2 form
a dc voltage to operate a buzzer- and
blinking-LED network. The blinking
LED flashes, and buzzer B1, which has
a built-in generator, sounds.
Like most other simple circuits, this
circuit also has a disadvantage: It is incompatible with some load-power and
ac-mains-voltage values. When a fuse
burns out, the load stays connected to
the ac mains, and the ac voltage divides between the circuit and the load.
When the load is highly resistive or the
ac-mains voltage is 110V rather than
220V, the circuits operating voltage
may be too low to drive the circuit. In
that case, decrease the value of capacitor C1 to 47 or 68 nF, after which the
circuits resistance rises. With the com-
FUSE
LOAD 60W
R2
1M
W
~220V
R1
56
1W
C1
0.15 F
400V
D1
W04M
D2
~10V
1W
D1
BLINKING
ponent values in Figure 1, the tested the circuit operates well because, with
edn080904di43341
DIANE
circuit operated with resistive
loads of higher
load-power values, the circuits
20 to 200W. With higher-power loads, load resistance is lower.EDN
C2
100 F
16V
B1
1206X
designideas
4
NC
TURNOFF
CIRCUIT
NC
IC2
3
ASSR-1219
3.9 F
IC3
AD1580
100 nF
D1
BZM85C15
2
RA
10k
1
GND1
VOA
VDD1
VISO
VADJ
GNDISO
GND1
4
INPUT
5V LOGIC
CONTROL
5
RF
100k
6
7
0V
D2
6
0V
EXTERNAL
SUPPLY
5V
RD
820
16
15
100 nF
10 F
13.5V INTERNAL
FLOATING
SUPPLY
14
IC1
ADuM5230
NC
VIA
NC
VIB
GNDB
VDDB
VDD1
VOB
8 GND1
13
12
11
10
9
NC
NC
NC
Figure 1 Connecting optical feedback by opto-MOSFET IC2 in the power-MOSFET-driver IC1 stabilizes the high-side
output voltage to 13.5V at values of loading current down to 3.7 mA. The power efficiency of the circuit increases for
a loading current of less than 7 mA.
In adjustable, frequency-selective RC networks, the reciprocal of an RC product, vC51/RC, determines the corner frequencies of the
R e fe r e nce s
IRFR/U024 HEXFET Power
MOSFET, International Rectifier,
www.irf.com/product-info/datasheets/
data/irfr024n.pdf.
2 ADuM5230, Isolated Half-Bridge
Driver with Integrated High-Side Supply, Analog Devices Inc, 2008, www.
analog.com/static/imported-files/
data_sheets/ADuM5230.pdf.
3 ASSR-1218, ASSR-1219 and
ASSR-1228, Form A, Solid State
Relay (Photo MOSFET) (60V/0.2A/
10V), Avago Technologies, July 18,
2007, www.avagotech.com/docs/
AV02-0173EN.
1
designideas
I1
4
ear taper potentiometer and a few
7.15k
other components.
Figure 1 shows a simple cir
CCW
LT1007
R1-0()
cuit
for
producing
a
ground-referR18
RP
R8
500k
enced
variable
resistance
having
R2
RP
10k
CW
the desired hyperbolic-control
(1-)RP
R9
characteristic. Analysis of this
10k
R6
circuit yields the following rela93.1k
LT1007
tionship between the control setFigure 1 This simple circuit synthesizes
R7
ting and the resistance from Node
R5
a grounded variable resistance with a
93.1k
7.15k
1 to ground: R1-0(a)5R1R2RP/
hyperbolic-control characteristic.
(R 1R 21R 1R P1aR 2R P)0<a<1.
I1
If you use this resistance in seR1
C1
C2
V1
ries or in parallel with a capaciVOUT
LT1007
0.1 F
0.1 F
tor, the resulting corner frequen- VIN
edn081002di43231 DIANE
R2
(PLACED IN 10-2
FOLDER)
cy will be a linear function of
392
RP
a: v C5(R 1R 21R 1R P1aR 2R P)/
RP
RP).
R2
To design this circuit for speFigure 3 The basic circuits of figures 1 and 2
cific
values of R1-0MIN and R1-0MAX,
have been used in the design of a bridged-T
R2
choose RP.R1-0MAX and then comR1
notch filter with a variable notch center freV2
pute R15R1-0MAX R1-0MIN/(R1-0MAX2
quency and a linear frequency scale.
I2
R 1-0MIN ) and R 2 5R P R 1-0MAX /
edn081002di43233
DIANE
(RP2R1-0MAX).
R1-2MIN and
R1-2MAX, choose
RP.R1-2MAX
Figure 2 You can realize a floating
You
can
extend
the
basic
cirand
then
compute
R
5R
R
/
1
1-2MAX 1-2MIN
variable resistance, with hyperbolic
cuit of Figure 1 to produce a float- (R1-2MAX2R1-2MIN) and R25RPR1-2MAX/
taper, with this circuit. Note that fixed
ing variable resistance with hyper- (RP2R1-2MAX). Note that the value of
resistors with the same number are
bolic taper (Figure 2). The value the R3 resistors does not directly affect
matchededn081002di43232
pairs.
DIANE
of the floating resistance between the value of R1-2(a). You should choose
(PLACED IN 10-2 FOLDER)
end. To make the frequency scale lin- nodes 1 and 2 is R 1-2(a)52R1R2RP/ resistors that are large enough to not
ear requires a control element with a (2R 1 R 2 1R 1 R P 12aR 2 R P )0<a<1, excessively load the op-amp outputs.
hyperbolic taperthat is, something and the minimum and maximum val
Figure 3 illustrates the application
in the form R(a)5RP/(A1aB). Such ues for R 1-2 are R 1-2MIN52R1R2RP/ of the circuits in figures 1 and 2 to
variable resistances are not general- (2R1R21R1RP12R2RP) and R1-2MAX5 the design of an adjustable bridgedly available from manufacturers, but 2R2RP/(2R21RP). To design the cir- T notch filter with a linear frequenyou can synthesize them using a lin- cuit of Figure 2 for specific values of cy scale. The filter has a notch center frequency that is adjustable from
1100
50 to 1000 Hz and a notch depth of
1000
220 dB. These requirements and the
900
choice of 0.1-mF capacitors for C1 and
800
C2 dictate that R1-0 varies from 375 to
700
7503V and that R1-2 varies from 6752
f N 600
to 135,047V. (A side benefit of using
(Hz)
500
this technique is that it frees the de400
signer from the restrictions of the lim300
ited number of standard end-to-end
200
resistance values that potentiometer
100
manufacturers offer.)
0
Figure 4 plots the Spice-simulated
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
notch center frequency for the cira
cuit of Figure 3 against the normalized
Figure 4 The Spice-simulated notch center frequency for the circuit of Figure 3
wiper position. The notch center freversus the normalized wiper position shows that the notch center frequency is
quency is a linear function of the cona linear function of the control position.
trol position.EDN
V1
R1
edn081002di43234
mike
designideas
Edited By Martin Rowe
and Fran Granville
VOUT
S1
switches and
A1
independent
VIN
control-logic
C1
15V
blocks, CL 1
15V
and CL 2 , for
switches S1, S2,
Figure 1 A basic sample-and-hold circuit comprises two op
and S 3 (Figamps, a switch, and a capacitor.
ure 2). The
VCONTROL
edn081002di43321
V1
V2
DIANE
CONTROL
LOGIC
CL1
CONTROL
LOGIC
CL2
V3
V4
V1
V3
VIN
A1
S1
A2
S3
C1
V2
S2
V4
Figure 2 To continue using switches with the same voltage range as that
of Figure 1, you must add two switches and two independent control-logic
blocks.
edn081002di43322
VOUT
D Is Inside
48 Inexpensive self-resetting cir-
dual-output current-controlled
conveyors
56 Perform timing for micro
two parts of the circuit may have independent power supplies. You apply
the same variable voltages to amplifiers A1 and A2 as you do to controllogic blocks CL1 and CL2, respectively. When S1 and S3 are closed, S2 is
open, and vice versa.
The resulting circuit keeps the voltages connected to the gate and substrate for the MOS transistors of each
switch within the desired 30V range
(Figure 3). (You derive this value from
the sum of absolute-voltage values:
|V1|1|V2| and |V3|5|V4|.) Voltages V1 and 2V2 connect to amplifier
A1, control-logic block CL1, and the
substrates of the transistors of switches
S1 and S2. Voltages V3 and 2V4 connect to amplifier A2, control-logic
block CL2, and the substrates of the
transistors of switch S3.
You create the changing voltages
of V1 and V2 using resistor dividers
R5 and R6 and R7 and R8, which connect to the 30 and the 230V power
supplies and the output of amplifier
follower A1 (Figure 3). Transistors
Q1 and Q2 create the change to the
power supply of amplifier A1. Volt-
DIANE
designideas
ages V1 and V2 also supply power to
control-logic block CL1 and the substrates of the transistors of switches S1
and S2. CL1 comprises transistors Q11,
Q12, Q15, and Q16. It creates a control
signal for gates Q5 and Q6 of switch S1
and the inverse signal for gates Q8 and
Q9 of S2.
Resistor dividers R9 and R10 and R11
and R12 connect to the 30 and the
230V power supplies, and the output
of amplifier follower A2 creates the
VCONTROL
Q11
Q12
R1
R2
Q13
Q14
30V
R9
30V
Q15
R5
Q1
R3
Q16
Q17
V3
R4
V1
R10
R6
VIN
A1
Q2
Q3
Q18
Q5
A2
Q7
Q6
Q10
R7
V2
Q8
Q9
C1
V4
VOUT
R11
Q4
R12
R8
30V
30V
Figure 3 You can create the changing voltages of V1 and V2 using resistor dividers R5 and R6 and R7 and R8.
DIANE
This linear current limiter is effective for applications in which the maximum load current, the supply voltage,
or both are relatively small. However,
the power that the circuits pass transistor, Q2, dissipates limits the circuits
applicability. For example, if the maximum load current is 200 mA and the
supply voltage, VS, is 24V, a short circuit across the load would dissipate almost 5W into Q2. Q2 must handle this
power with adequate margin, and additional heat-sinking may be necessary to keep its junction temperature
at a safe level. Using larger values of
designideas
maximum load current, supply
If a fault now causes the load
RS
Q2
voltage, or both exacerbates this
current to increase to a level at
problem. In many applications,
which the base-to-emitter voltage
IL
the cost, size, and weight of the
is approximately 0.7V, Q1 turns
VBE
components necessary to handle
on and its collector current rapVL
SUPPLY
Q1
the short-circuit power dissipaidly charges C1. The input voltVOLTAGE
RL
tion may be prohibitive.
age now quickly rises toward the
VS
However, by adding a few
Schmitt inverters upper threshRG
inexpensive components, you
old voltage, VTU, at which point
can adapt the circuit to proIC1s output goes low, turning off
vide effective current limiting
Q3 and Q2. The load current now
Figure 1 A conventional two-transistor current
with none of the power-disfalls to 0A and the base-to-emitlimiter prevents excessive current from reaching
sipation headaches. The reter voltage falls to 0V, thereby
the load.
sulting circuit functions as a
causing Q1 to turn off. C1 now
self-resetting circuit breaker
begins to discharge through R1
(Figure 2a). Again, Q1 and RS pro- assume that the load current is initial- and R2, and the input voltage slowvide a current-monitoring function ly low and the base-to-emitter voltage ly falls toward the Schmitt inverters
in which the sense voltage VSENSE5 is less than 0.7V. Under these condi- lower threshold voltage, VTL. At this
IL3RS. In this circuit, however, Q2 is tions, Q1 is off and timing capacitor C1 point, IC1s output again goes high, Q3
either fully on or fully off and never remains uncharged such that VIN, the and Q2 turn on, the circuit breaker rebiases into its linear region. Because voltage at the input of Schmitt inverter sets itself, and the process repeats unedn081016di43391
DIANE
Q1s base current is normally small, the IC1, is 0V.
Thus, IC1s output
is approxi- til you remove the fault.
voltage drop across base resistor RB is mately 5V, biasing Q3 on, which in turn
The circuits waveforms show the
also small, such that the base-to-emit- provides gate bias for Q2 through R4, al- relationship between the input voltter voltage is approximately equal to lowing current to flow from the supply age and the load voltage (Figure 2b).
the sense voltage.
voltage into the load through the sense Because load current flows into Q 2
To understand how the circuit works, resistor and Q2s on-resistance.
only during the on-time, the average
power it dissipates is directly proportional to the duty cycle: PAVGtON/
RS
(tON1tOFF), where PAVG is the averQ2
age power in watts, tON is the on-time,
VSENSE
R3
IL
and tOFF is the off-time. Provided that
RB
VBE
10k
C1, R1, and R2 set a large enough time
1k
Q1
constant, the off-time will normally
R4
RX
be much greater than the on-time,
VL
SUPPLY
10k
5V
RL
and the resulting power that Q2 disVOLTAGE
R
IC
1
1
D X C1
VS
sipates will be low. Like the linearQ3
current limiter, the sense resistor sets
CX
the circuit breakers current limit:
C2
R2
VIN
2N7002
100 nF
ILMAXIMUMP0.7V/RS (A).
0V
R1 and R2 form a potential divider
(a)
that ensures that the input voltage
can never exceed IC1s maximum inVTU
put voltage. Select values such that
VIN
the input voltage is 5V or less when
VTL
Q1 is fully on, where the voltage of
VS
C1 is roughly equal to the supply volttON
age. Also, choose values that are large
VL
enough to provide a large time contOFF
stant without requiring an excessively
large value of C1. The selection of tran0V
(b)
sistor Q1 isnt critical, but you should
select a device with good current gain
and make sure that its maximum colFigure 2 Adding a few components turns the current-limiting circuit into a
lector-to-emitter voltage is greater
pulser that reduces heat in the pass transistor, Q2 (a). The circuits waveforms
than the supply voltage. When choosshow the relationship between the input voltage and the load voltage (b).
ing a P-channel MOSFET for Q2, re-
edn081016di43392
DIANE
designideas
member that it must withstand the full
supply voltage when you bias it off, so
make sure that the maximum drain-tosource voltage is greater than the supply voltage. When choosing a value for
the sense resistor, ensure that the baseto-emitter voltage is less than 0.5V at
the maximum normal value of the load
current.
Loads such as filament bulbs, ca-
pacitive loads, and motors that exhibit a large inrush current can cause
the circuit breaker to trip on powerup. You can avoid these problems by
adding capacitor CX, diode DX, and
resistor RX. On power-up, CX is initially uncharged and pulls the input
voltage toward 0V through DX. This
action prevents the circuit breaker
from tripping until the inrush current
IB
VY
Second-generation current conveyors feature wide signal bandwidth, linearity, wide dynamic range,
simple circuitry, and low power consumption. Hence, designers employ
several implementations of current
mode in these devices for realizing various functions. A previous Design Idea
introduced a second-generation dualoutput current-controlled conveyor to
create oscillators (Reference 1). Unfortunately, these circuits arent available as ICs, but you build them from
discrete components. Figure 1 illustrates an active building block of such a
circuit, which the following equations
characterize: I Y50, V X5V Y1I XR X,
VX
IY
IX
IZ
IZ
Additionally, you can control the condition of oscillation using the conveyors bias currents.
Figure 3 shows the proposed sinusoid-oscillator circuit. You can
obtain the characteristic equation
for the circuits as follows: S 2C1C2
R X1 R X2 1 SC 2 R X2 2 SC 2 R X1 1 K5 0,
Q7
Q5
Q3
X
Q2
Q16
Q15
Q4
Q12
Q9
Q8
Q18
Q1
Y
IB
Q13
Q6
Q11
Q10
Q14
DIANE
Q17
Q19
designideas
where K is the voltage multiplier. Satis
fying Barkhausens criteriathat the
loop gain is unity or greater and that
the feedback signal arriving back at
the input is phase-shifted 3608the
required condition for oscillation is
RX15RX2, and the frequency of oscillation is f51/2p=k/(C1C2RX1RX2).
Clearly, you can use the gain buffer
to vary the frequency of oscillation,
which is the area in which this circuit
differs from the earlier Design Idea. You
can use both current and voltage to
control the voltage multiplier. The circuit lets you vary the voltage multiplier
by adjusting bias currents IB3 or IB4 (Figure 4). For voltage control over K, you
can use another circuit simply by using
a noninverting op amp and replacing
the resistors with MOSFETs working in
that triode region. That approach simulates voltage-controlled resistors.
The circuit in Figure 2 underwent
testing with a PR100N PNP transistor
and an NPN NP100N transistor of the
bipolar arrays ALA400 and a dc supply
of 63V (Reference 2).
The circuit requires only two current-controlled conveyors, two grounded capacitors, and a voltage multiplier;
it requires no floating capacitors and
no external resistors, which makes
the circuits power consumption lower
than that of RC oscillators. For a conventional bipolar-transconductance
operational amplifier, the transconductance, gm, is IB/2VT. Comparing
IB3
IB1
Y
C1
VIN
Z
Z
Y
X
IB2
Y
X
Z
Z
VOUT
X
4
C2
this figure
with the equivalent
value
edn081018di43503
DIANE
IN THE 10-16 FOLDER) of the biof I(PLACED
, the transconductance
B
polar-transconductance op amp is four
times less than that of a dual-output
current-controlled conveyor. Thus,
the power consumption of the current-controlled-conveyor-based circuit is about four times less per active
device than that of the op-amp-based
circuit. The sensitivity study shows
that SCK;RX1;RX2;C1;C252; c sensitivities are hence less than unity, which is
an attractive feature of this circuit. Remember that creating an accurate oscillator model requires modeling equations to be nonlinear, and meeting
the Barkhausen criteria is a necessary
Figure 4 This circuit lets you vary the voltage multiplier by adjusting bias currents I B3
or I B4.
edn081018di435014
DIANE
IN THE 10-16
FOLDER)
condition (PLACED
for oscillation.
Oscillator
circuits may latch up and never oscillate even if you satisfy the Barkhausen
criteria.EDN
R e fe r e nce s
1 Lahiri, Abhirup, Oscillator uses
dual-output current-controlled conveyors, EDN, Nov 13, 2008, pg 62,
www.edn.com/article/CA6611645.
2 Frey, DR, Log-domain filtering: an
approach to current-mode filtering,
Circuits, Devices and Systems, IEE
Proceedings G, 1993, Volume 140,
pg 406, http://ieeexplore.ieee.org/
Xplore/login.jsp?url5/iel1/2211/
6397/00250002.pdf?arnumber5
250002.
IB4
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
44 DDR-differential-clock source
R1
1M
1
3
damage
accuracy
5V
FROM DUT
VIN
12V
VTHR
5V
LM393
2
4
R1
10k
1
VOUT
0V
MICROCONTROLLER
(a)
12V
VIN
12V
5V
VTHR
VOUT
VOUT
5V
MICROCONTROLLER
R2
10k
0V
(b)
edn081016di43541
5V
DIANE
Figure 2 Another approach to signal conditioning is to use dual- or quadvoltage comparators (a). The 5V power-supply voltage acts as the positivethreshold voltage. The output is 5V for input signals lower than this level. If
the input signal exceeds 5V, the output voltage drops to 0V (b).
edn081016di43542
DIANE
designideas
proximately 1 MV between the gate
and ground. Also, the input voltage
should be more than the MOSFETs
gate-threshold voltage, VTHR, of 3V dc
but less than the maximum rated gateto-source voltage, VGS, of 20V dc. In
this figure, the output voltage never
exceeds the power-supply voltage, and
variations of the input voltage have no
effect on output as long as they happen
in the saturation region. A drawback
of this approach is that you must use as
many transistors as the number of testpoints in the DUT.
Another good option is to use any
dual- or quad-voltage comparator.
You can use an LM393 from National
Semiconductor (www.national.com)
because its inexpensive and widely
available. Figure 2 shows a simple configuration with few components. The
5V power-supply voltage acts as the
positive-threshold voltage. The output is 5V for input signals lower than
this level. If the input signal exceeds
5V, the output voltage drops to 0V. Resistor R1 connects an open collector of
the LM393 to the supply voltage.
Sometimes, a zero-output signal is
undesirable. A missing power-supply
voltage, a bad solder joint, or a broken wire in the test fixture could cause
this zero-output signal. Use a logic
high level when the signal under test
is present and logic low when its absent. At first glance, it seems that just
R2
200k
FROM DUT
VIN
12V
R3
200k
VTHR
2.5V
2
3
5V
R1
10k
LM393
(a)
12V
VIN
12V
VTHR
2.5V
VOUT
5V
5V
(b)
Figure 3 Use the voltage divider comprising R2 and R3 for the threshold
voltage.
switching the comparator pins of the common-mode range. The upper limit
input and the threshold voltages
pro- of common-mode
input voltage for the
edn081016di43543
DIANE
vides an acceptable approach. Howev- LM393 is 1.5V less than the powerer, that assumption is invalid because supply voltage, or 3.5V. Thus, you
the positive input voltage may exceed should use the voltage divider compristhe power-supply level only as long as ing R2 and R3 for the threshold voltage
the other voltage remains within the (Figure 3).EDN
MICROCONTROLLER
DDR-differential-clock source on
SOC drives two DDR-memory chips
VOUT
5V
designideas
R1
IC1
SOC
CLK
CLK
R2
CLK
R3
CLK
IC2
DDR CHIP
CLK
IC3
CLK DDR CHIP
R1
14.3k
VOUT
AMPLIFY/
TRACK
T=14.4 SEC
VIN
R4
2k
11
13 X1 A
14
X
12
X0
10
LT1214
9
MAX4053
C
0.001 F
VIN
R4
2k
2
1
R3
28.7k
MAX4053
X0
X
R2
28.7k
15
X1 A
10
Figure 1 The behavior of the RC topology is still simple when you replace the
resistors with an active circuit that synthesizes a negative resistance.
edn080821di42961
DIANE
designideas
output voltage, VOUT/VIN is a divergent exponential function of time:
gain52(t/10 msec11).
Building on the assets of that earlier
design, this new circuit features CMR
(common-mode rejection) that neither resistor-network matching nor
the CMR of the op amp limits. Straycapacitance issues impose the only limits, but you can minimize these issues
with careful circuit layout. The circuit
has rail-to-rail inputs, virtually unlimited programmable gain, and gain-set
resolution that only the resolution
of the amplify-interval timing limits. The circuit also has settling time
10 to 100 times faster than that of the
R e fe r e nce
Woodward, W Stephen, Digitally
programmable-gain amplifier uses
divergent-exponential curve, EDN,
Jan 8, 2009, pg 49, www.edn.com/
article/CA6625454.
Sealed-lead-acid batteries,
which find wide use in powerelectronics products, such as UPS
(uninterruptible-power supplies), inverters, and emergency lamps, supply
power to the load whenever utility
power is unavailable. When you restore utility power, a charger supplies
the power to the load and charges the
batteries (Figure 1).
You can add a diode to protect a load
from current resulting from a reverse-
BATTERY
CHARGER
LOAD
R2
1k
13V
BATTERY
R1
10k
2N2907A
CHARGING
PATH
edn081113di4371
Q2
R3
10k
CURRENT
SENSE
Q1
LOAD
PATH
BATTERY
TO
LOAD
V1
IRF150
edn081113di43712
DIANE
edn081205di43851
VINAC
1N4005
1N4005
470 F
VOUTDC
DIANE
edn081205di43852
DIANE
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
includes high-side gate drive with current limiting (Reference 1). However,
the hysteretic-control scheme of this
analog IC is likely to yield questionable
performance in some applications due
to variable switching frequency and
overshoot, as well as an inability to regulate feedback below the 1.24V reference. A traditional PID (proportionalintegral-differential)-control scheme
can get around these limitations but
adds considerable complexity.
The CLZD010 CLOZD (Caldwell-
12V
INPUT-VOLTAGE RANGE: 6 TO 28V
CURRENT LIMIT: 5 A48.7k/0.12=2A
NONDISSIPATION
CURRENT SENSE
1
2
GND
1.24V
NC
48.7k
ANALOG LM3485
ISNS
VIN
GATE
GND
FBK
PWM PULSE
TRAIN
IADJ
0.001 F
8
7
FDC5614P
6
5
SWITCHED
POWER
TEMPERATURE FEEDBACK
5V CONTROL POWER
5V
LP2950
PRECISION
LINEAR
REGULATOR
LM34
TEMPERATURE
SENSOR
DIGITAL CLZD010
2.2 F
5k
TEMPERATURESETPOINT
ADJUSTMENT
1
2
3
4
5
6
7
8
9
FBK
REF
SPT
HEN
LEN
STA
A
D
C
BIP
GND
PS0
PS1
PS2
PWM
DSP
C
O
PWM SETTING:
31.2 kHz
TIM
VDD
CS3
CS2
CS1
CS0
18
17
16
15
14
13
12
11
10
HEATER
LOAD
100 F
MBRS140T3
COMPENSATION
SETTING: 134 SEC
Figure 1 Combine the simple and robust closed-loop control of the digital CLZD010 with the current-limited high-side
gate drive of the analog LM3485 for the best of both worlds.
edn080918di43441
DIANE
designideas
loop-optimization-in-Z-domain) controller-chip IC from Flextek Electronics (www.flex-tek.com) both broadens
and simplifies control applications
though the embedded intelligence of
a digital device (Reference 2). A single time-domain compensator replaces
the three frequency-domain PID pa-
250
200
150
TEMPERATURE
(F)
100
OPEN LOOP
50
CLOZD*
0
10
TIME (MINUTES)
* CALDWELL-LOOP OPTIMIZATION IN Z DOMAIN
(a)
14
12
10
8
VOLTAGE (V) 6
edn080918di43442a
DIANE
OPEN LOOP
2
0
(b)
CLOZD*
0
5
6
TIME (MINUTES)
10
Figure 2 In the thermal-response example (a), the circuit takes about three
minutes for the open-loop temperature to reach roughly two-thirds of its final
value. The resultant closed-loop temperature quickly nears its final value due
to maximum drive; voltage then decreases to allow the temperature to settle at
the setpoint without overshoot (b).edn080918di43442b DIANE
designideas
IC1
3
VOUT L78L05BUTR VIN
5V 1
R1
1k
D3
GREEN
TEST
R6
6.2k
OPTIONAL
MULTIMETER
BH1
1.46V
R15
2k
R18
1.2k
1%
IC2B
1.33V
Q3
10
R13
1.6k
1%
R3
20k
OPTIONAL
SELF-TESTING
R17
510
1%
IC2C
13
1.2V
R20
330
1%
R22
4.7k
1%
12
R7
10k
R11
2k
B1
9V
6F22
BCW33
Q2
R12
100k
R21
680k
OP484ES
R19
3
1%
0.25W
Q1
IRLML5103
D4
GREEN
EXCELLENT
R9
1.5k
BC817-40
R14
1k
IC2A
R10
680k
BATTERY
UNDER TEST
5
R8
510
1%
ITEST=250 mA
C1
100 F
16V
R5
6.8k
VREF
0.825V
R2
1.5k
D2
BAS32L
R4
6.8k
1%
GND
2
D1
BAS32L
C2
330 nF
IC2D
4
14
D5
YELLOW
GOOD
R16
1.5k
D6
RED
POOR
R23
680k
Square-root-calculating circuits
find wide use in instrumenta-
designideas
ate. This Design Idea describes such a the identical transistors forming the root of the difference of input voltag 1
V and V
Equation
1
1 and
circuit, which uses only
MOSFETs
to MOS-resistive
es V1 and V2. If you ground V2, then
B
VO = circuit,
I O1A,
voltages.
the output; hence, the square-rooting Hence, you have devised a new allThe circuit uses the nested con- function is voltage-controllable.
MOSFET-based, voltage-controllable
Equation 2
nection of MOSFETs Q1 and Q2. Q2
The following equation gives the analog square-root calculator.
works in the saturation region as it is output voltage:
You can test the circuit using a vadiode-connected, forcing Q1 to work
riety of commercially available MOS 1
Equa
tion 2MOS1
1
in the
triode for
region.
Alldiother
FETs, such as the 2SK1228, which is
Equation
081002
4330
VO = 2
+
K(VAVB )(V1V2).
1
1
1
VO = 2
+cir-
K(VAVB )(V1V2).
IO1, is basically a MOS-resistive
Texas Instruments (www.ti.com). For
K1 K 2
K2
Equation 1
governcuit. The essential equation
the operation of the circuit to be in
ing the circuit operation is:
It is evident from this equation that accordance with the output-voltage
the output voltage, VO, is the square equation, the four MOSFETs you use
1
1
to create the MOS-resistive
VO =
I O1 ,
K
circuit should be identical
K
2
1
DIANE
designideas
UNI/BIP
VDD
PD
GAIN
AD7742
POWER-DOWN
LOGIC
VIN1
VIN2
VIN3
INPUT
MULTIPLEXER
X1/X2
VOLTAGE-TOFREQUENCY
MODULATOR
fOUT
FOUT=FFS VIN .
VREF
VIN4
A1
2.5V
REFERENCE
CLOCK
GENERATION
A0
5V
CLKIN
GND
5V
2.5V
10
12
CLOCK
SOURCE
12 MHz=4FFS
11
D2
SD2
Q2 9
A1
2k
2FFS
74AC74
CP2
CD2
Q2
5V
C
0.1 F
2k
A2
VDD
C
74AC74
3 CP
5
1
Q1
VSS CD1
1
F
VREF=2.5V OUT
FFS
13
14
D1
4
SD1
5V
5V
0 TO 100% FULL-SCALE
1
0.9
0.8
LINEAR
0.7
RESOLUTION
0 TO 4% FULL-SCALE
0.1
0.09
0.009
0.08
0.008
0.07
0.6
0.01
HIPPASIAN
0.06
0.007
0.05
0.005
0.4
0.04
0.004
0.03
0.003
HIPPASIAN
0.2
0.02
edn090219di4318fig1top
0.1
0
0.20
0.40 0.60
VIN/VFS
0.80
mike
0.01
0
LINEAR
HIPPASIAN
0.006
0.5
0.3
0 TO 0.04% FULL-SCALE
0.002
0.001
0
0
LINEAR
0.0001
Figure 1 This nonlinear, wide-dynamic-range voltage-to-frequency converter exhibits 25-times improvement in counting time over
other approaches.
R1
10k
To display the status of two digital outputs, you can simply connect an LED and its resistor on each
output. You must, however, interpret,
or decode, the displayed binary code.
In addition, when no LED lights, users
have no way of knowing whether it
means that both outputs are off, that
the power is off, or that a malfunction
has occurred. In some applications,
including industrial and medical settings, an indicator sending an ambiguous signal would be unacceptable. This
Design Idea describes a simple circuit
that resolves this problem by displaying four states on four LEDs (Figure
1). The operator need not understand
binary coding, and, if no or more than
one LED lights, it can mean only no
power or default.
The circuit works in the following
way: If both inputs A and B are low,
Q1 allows current to pass through D1
and resistor R2 to A; only D1 will light.
Symmetrically, if both inputs A and
B are high, Q2 passes, and the current
can pass from A through R4, Q2, and
D4; only D4 will light. If both inputs
are on different levels,
Table 1 LED-lighting possibilities
only D2 or D3 will light.
IN
LED
Table 1 shows the possibilities; all other displays
A
B
1
2
3
4
point to a default, such
0
0
1
0
0
0
as a bad connection, a
0
1
0
1
0
0
no-power condition, or a
malfunction.
1
0
0
0
1
0
A totem-pole output
1
1
0
0
0
1
that can sink and source
D2
R6
6.8k
D1
Q1
R2
220
R3
220
A
R4
220
D3
R5
10k
Q2
R7
6.8k
D4
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
44 Discrete-component buck
1
t F = NS + 32 = NS + S + 320 .
derstandable format, both in Celsius
5
80
8
10
(2)
and Fahrenheit. This Design Idea
N
9 5
1
presents an effective approach.
t = NS + 32 = NS + S + 320 .
Consider the TMP121Fsensor
from
5 80
8
10
Texas Instruments (www.ti.com).
It provides 13-bit data in a 16-bit The benefit of equations 1 and 2 is
frame with resolution of 0.06258C/ that you can perform the calculations
bit. Hence, the transfer function is with integer arithmetic only. They
tC50.06253NS, where tC is the tem- require divisions by powers of two,
perature in degrees which you can replace with shifts,
Celsius and N S is and division by 10, which you perVCC
EDNsensor
081016didata
4256 equations
the
form by introducing a decimal point
TMP121
68HC11
LCD
after you remove in the display.
SCLK
SCK
the three
meaningThe circuit underwent testing with
EDN21.6C
081016di 4256
equations
MISO
SO
less least-significant the popular 68HC11 microcontroller
CE
VCC
C
bits.
You can
OC2
Equation
1 easily from Motorola (www.motorola.com,
PA7
SS
rearrange the above Figure 1). Besides a sensor and a
equation to:
controller, it includes a unit-selecF
Equation 1
tion switch and a dot-matrix LCD.
NS 1
5
N
tC =
NS = S +The
. resolution is 0.18. The
display
80
2
8 of 1the
0 supporting firmware is an
(1) core
Figure 1 A small system uses a 68HC11 microconN 1
5
N
endless loop in which the 68HC11
troller to read a switch and a sensor, to convert
t C =data, NS = S + S .
uses an output-compare function to
80
8 10
2
and to display temperature.
Equation 2
generate a square-wave signal with a
Equation 2
edn081016di43561
DIANE
tF =
N march
9 5
10
designideas
period of 1 sec and a duty cycle of
50%. The OC2 signal connects to
the CE input of the sensor and controls its operation: When CE is high,
the sensor measures temperature. The
HC11 does nothing except display
M on the LCD. When CE becomes
low, the last measurement latches in
a shift register inside the sensor. The
HC11 deletes M from the display,
reads the switch and the sensor, manipulates the data, and displays the
temperature.
Equations 1 and 2 provide the
basis for two source codes. Listing 1,
available at www.edn.com/090305dia,
generates machine code of 981 bytes.
Listing 2, also available at www.edn.
com/090305dia, generates machine
code of 392 bytes. Despite the C-lan-
guage approach with integer arithmetic, it needs 2.5 times more memory to
do the job. The ratio is well above 10
if the C code goes with equations that
need floating-point arithmetic. The
benefit is clear: Modified equations
1 and 2 and assembly-language programming let you select a microcontroller with less memory and reduce
the price of your design.EDN
using only discrete components. It requires two bipolar transistors, a P-channel MOSFET, an inductor, a Schottky
diode, and a few resistors (Figure 1).
Dhananjay V Gadre, Netaji Subhas Institute of Technology, New Delhi, India
When you switch on the battery
HB (high-brightness)
voltage, the voltage across
S1
LEDs require a large
R1, the resistor in series with
amount of current to operate.
the HB LED, is 0V. Thus,
R2
When driving HB LEDs from a
transistor Q2 is off, and Q1 is
3.9k
IRF9540
voltage source, you can set the
in saturation. The saturated
R3
required current with a suitstate of Q1 switches on the
3.9k
able series resistor. If the volt- BATTERY
MOSFET, thereby applying
Q1
age source is a battery, then, as
the battery voltage to the
L1
the battery drains, the LEDs
LED through the inductor.
130 H
BC547
D2
Q2
intensity decreases. Also, a seAs the current through resis1N5819
ries resistance has the disadvantor R1 increases, it turns on
BC547
tage of power loss through the
Q2, which turns off Q1 and
D1
resistor. A better option is to
thus turns off the MOSFET.
use a suitable dc/dc converter.
During the MOSFETs off
R4
C1
R1
edn080918di43581
DIANE
designideas
intensity. Using a larger value for R1
reduces the intensity.
The SwitchCAD-III software,
which is available as a free download
from Linear Technology (www.linear.
com), simulated the circuit; the simulated MOSFET was an International
Rectifier (www.irf.com) IRF9Z24S
instead of an IRF9540 because the
model for IRF9540 is not available
in SwitchCAD-III. Figure 2 plots
5V
5V
40.61.6.005
3.3V
QE128
3.3V
3
4
10 F
100 nF
RESET
4.7k
47
4.7
31
VDD
100 nF
VREFH
100 nF
5
VREFL
ULN2003
PTB0
18
VSS
PTB1 17
MC9S08QE128
16
15
14
13
12
11
10
5V
Figure 1 You can drive a single-coil latching relay without an H-bridge circuit,
greatly simplifying hardware design and making the most of the low-power-consumption features inherent to latching relays in portable-system applications.
edn081113di43811
R e fe r e nce s
Saab, Alfredo H, and Steve Logan,
High-power LED drivers require
no external switches, EDN, July 19,
2007, pg 78, www.edn.com/article/
CA6459061.
2 Gadre, Dhananjay V, Buck
regulator controls white LED with
optical feedback, EDN, Oct 25,
2007, pg 72, www.edn.com/article/
CA6491146.
1
DIANE
designideas
must wire at least two open-drain buffers of the ULN2003 to both endings
of the relay coil to ensure enough current when the microcontroller pulls
down.
Listing 1, which is available in the
Web version of this Design Idea at
www.edn.com/090305dib, shows the
software procedure to latch the relay
NC
NC
Figure 1 This circuit works by inhibiting movement in one direction but allowing movement in the other direction when the motor retracts from its end
position.
edn080809di43351
low to turn off the ULN2003 opendrain buffer to ensure the lowest
power consumption. You must, however, take into account the set/reset
timing. Pull the microcontroller output low only after the required time
has elapsed. Waiting ensures that the
relay will properly latch to its intended position.EDN
DIANE
NO
NO
DIANE
NC
NC
edn080809di43353
DIANE
DIANE
DIANE
designideas
rent may be too high, or the switches may be closing switches or light
barriers.
If you use an H bridge to drive the
motor, you can achieve the same operation in a more versatile way. The
circuit in Figure 2 shortens one
Q3
GATE
DRIVE
OUT
Q4
PWM
LOGIC
Q5
GATE
DRIVE
VCC
OUT
Q6
3.3V
D1
MMBD4448
D2
MMBD4448
BTL-CLASS D-AMPLIFIER IC
PGND
D3
MMBD4448
D4
MMBD4448
TO SECOND
CHANNEL
C1
4.7 nF
R1
100k
R4
10k
Q2
R2
10k
MMBT2222
Q1
R3
10k
TO MICROCONTROLLER
MMBT2222
R5
100k
C2
10 F
Figure 1 Adding several components to the BTL-Class D-amplifier IC provides a clip-detection function. A peak detector,
comprising Q2, R5, and C2, is optional.
DIANE
designideas
the gate drivers transforms the low- R2, and R3 and the voltage drop across
power PWM signal into a high-volt- diodes D1 through D4 set this threshage, high-current PWM sequence. A old, which is 0.5V with respect to powBTL (bridge-tied-load) amplifier ba- er ground, PGND, for the given composically comprises two gate-drive cir- nent values. A positive-going pulse apcuits and two power stages, which the pears on the collector of Q1 whenever
same PWM signal drives. The signal the output voltage is below the threshdirectly drives one gate-drive circuit old with respect to power ground. This
and phase-inverts the other. In theo- pulse alerts the host microcontroller to
ry, a BTL amplifier can produce
four times more power into the
same load than a single-ended
amplifier.
Figure 1 illustrates the implementation of an external clipdetection circuit to a BTL-Class
D-amplifier IC. The voltage
swing on each output is symmetrical and is within the range
of voltage drop on the on-resistance of MOSFET Q6 to the
common-collector voltage, VCC,
minus the voltage drop on the
Figure 2 A positive-going pulse appears on the
on-resistance of MOSFET Q3.
collector of Q1 whenever the output voltage
When the output voltage reachis below the threshold with respect to power
es a certain threshold, Q1 turns
ground.
off. The component values of R1,
designideas
Edited By Martin Rowe
and Fran Granville
The most common switchingpower topology is a buck converter, which efficiently transforms
high voltages to low voltages. Figure
1 shows a typical buck converter in
which the N-channel MOSFET, Q1,
needs a floating-gate drive signal. The
floating-gate drive is part of the PWM
(pulse-width-modulation) controller
IC. Q1 can be either N or P channel,
depending on the controllers design.
Unfortunately, the ICs voltage rating
must be as high as the input voltage,
which places a limit on the maximum
voltage it can process.
D Is Inside
53 Isolated clock source acts as
test generator
58 Instrumentation amplifier
L1
rent will flow through D2 and C2
edn081113di43821 DIANE
D2
R1
VCC
12V
whenever Q2 is on, which lowers
5.11k
efficiency. D2 limits C2s voltage
to the value in the above equaQ3
C2
VOUT
tion. When Q3 is on, D2 becomes
PWM CONTROLLER
C1
D1
forward-biased if the voltage atPFET
VIN
VGATE
tempts to increase. This circuit
applies a 0V voltage between
Q2
Q1s gate and source when Q3 is
on, and it applies 1VCC when
NFET
Q2 is on.
designideas
voltage is high. Diode D2
tor R4 and an internal 2-kV
limits Q1s gate-to-source
resistor to generate a ramp
voltage to 12V regardwith a peak-to-peak voltage
less of the circuits input
of 50 mA3(2 kV15.11
voltage. Capacitor C2 is
kV)Q300 mV at the CS
transparent to Q1s gatepin, Pin 8. The COMP pin,
drive pulse, so the circuits
Pin 3, compares this sawgate-driving capability is
tooth to the output error
just as good as that of the
voltage at the COMP pin,
totem-pole circuit itself.
which generates the right
The level shifting, thereduty-ratio signal for Q1.
fore, imposes no limitaFigure 4 shows the cirtion on the size of the
cuits switching waveforms.
MOSFET that the circuit
Oscilloscope channel 1
can drive.
(bottom trace) shows the
Figure 3 shows a pracgate-drive signal that the
tical buck converter emLM5020-1 generates. ChanFigure 4 Voltage waveforms in the buck-converter circuit of
ploying this scheme. The
nel 2 (middle trace) shows
Figure 3 show clean voltages with short rise and fall times.
converters input voltage
the corresponding totemis 18 to 45V, and its output
pole output voltage. Chanvoltage is 12V at a 1.5A output current. ability in 12.7-kV R3 for 500 kHz; feed- nel 3 (top trace) shows the level-shiftThe converter uses National Semicon- back compensation in C7, C8, and R6; ed totem-pole output voltage between
ductors (www.national.com) LM5020- and output-voltage setting in R9 and the source and the gate of Q1. The
1 flyback/boost/forward/SEPIC (single- R10.
peak value of Q1s gate-to-source voltended-primary-inductance-converter)
The LM5020-1 provides current- age equals the input voltage, and its
PWM-controller IC.
mode control, but, in this circuit, it amplitude is about 8V, the value of the
The figure retains the component implements voltage-mode control. supply signal that the LM5020-1 interdesignators from the previous figures An internal sawtooth-current source nally generates. All the waveforms are
but adds functions such as input-volt- with a peak value of 50 mA, which clean and have short rise and fall times.
age filtering in C9; input-undervoltage adds slope compensation to a current The full-load efficiency of the circuit is
lockout in R2 and R7; soft-start capabil- signal, serves as a voltage ramp. This 86 and 83% at input voltages of 18 and
ity in C3; switching-frequency-setting current flows through 5.11-kV resis- 45V, respectively.EDN
IRFR9014
Q1
P2
VIN
18 TO 45V
C9
470 F
63V
R5
10k
R7
133k
D2
12V
R1
5.11k
9
8
7
6
IC1
VIN 1
LM5020-1
2
RT
VFB
3
CS
COMP
VCC 4
UVLO
5
GND
OUT
SS
C7
OPEN
R6
10k
C8
47 nF
C6
1 F
C2
0.1 F
Q3
MMBF2202
C3
100 pF
R3
12.7k
C4
1 nF
R4
5.11k
Q2
MMBF2201
P4
GND
12V AT 1.5A
R9
13.3k
C5
0.1 F
10
R2
11.8k
P3
L1
15 H
fS=500 kHz.
Figure 3 An alternative buck converter uses a low-side PWM IC to control MOSFET Q1.
C1
330 F
16V
D1
MBRS3100
R10
1k
P5
GND
IC1
78L05
9V
C2
100 nF
C6
100 nF
Q1
C3
R2
100k
3- TO 30-MHz
CRYSTAL
OSCILLATOR
Q3
2N2369
2N4423
Q2
1
R7
C9
22 nF
R3
2200
C4
R8
4.7
R5
220
2N2369
C1
33 pF
C7
100 F
C8
100 nF
C5
100 nF
R1
56k
IC2
8
7
6
4
R6
100
C10
22 nF
VCC
5V
CLOCK
5
HIGH-SPEED
OPTOCOUPLER
R4
560
TTL-LEVEL SHIFT
Figure 1 This circuit provides a cost-effective approach to implementing an isolated clock source using a high-speed optocoupler with low input-to-output capacitance.
edn081113di43721
DIANE
designideas
Class AB
inverting amp
uses two floatingamplifier cells
R6
100k
2W
15V
R7
100k
2W
Q1
R10 STW8N80
100
1W
D1
6.2V
7
6
C1
4.7 pF
R2
600k
1W
NC
IC2
6N136
R4
2k
Q2
R11
100
1W
STW8N80
5
VOUT
C2
R3
330k 2000 pF
VIN
R1
10k
R8
100k
2W
15V
1
3
6
IC1
LM7171
4
R5
2k
15V
R9
100k
2W
Q3
R12 STW8N80
100
1W
D2
6.2V
7
6
15V
NC
Q4
R13
100
1W
3
IC3
6N136
STW8N80
Figure 1 Transistors boost the output voltage and current of optoisolators, making an isolated amplifier output.
edn081030di43601
600V
DIANE
designideas
sistors R4 and R5 provide the necessary bias to guarantee that the output transistors are always on. Careful
trimming of R4 and R5 can remove the
output crossover distortion. Zener diodes D1 and D2 keep the optoisolator photodiodes back-biased at 6.2V.
Resistors R10, R11, R12, and R13 supply
DPGAs (digitally programmablegain amplifiers) amplify or attenuate analog signals, which maximizes
an ADCs dynamic range. Most monoW Stephen Woodward, Chapel Hill, NC
lithic DPGAs, such as the Linear Technology (www.linear.com) LTC6910 and
the National Semiconductor (www.
national.com) LPM8100, use a multiplying DAC in an op amps feedback
loop so that the DACs input code sets
the amplifiers closed-loop gain. Instead of using a monolithic DPGA, you
can use two op amps and three analog
switches to build a DPGA employing
negative time constants.
Youre no doubt familiar with the e2t/RC
convergent exponential in which a
capacitor in an RC circuit asymptotically discharges to zero. For input voltage, V5VIN/2 at t5T5loge(2)RC,
Figure 1 A negative time constant causes voltage to increase exponentially
V5VIN/4 at t52T, V5VIN/8 at t53T,
over time.
and so forth. Less familiar, but just as simR1
7.21k
ple, is the behavior of
GAIN-PROGRAMMING PWM
MICROthe same RC topolCONTROLLER
I1
S1
11
ogy when you replace
T=7.21 SEC
A
3
69 SEC=1/14.5 kHz
X1
R with an active cir4
3
5
VIN
X
A1
cuit that synthesizes
X0
1
PWM
AD8606
R4
VO=2VIN
2
I1
a negative resistance
200 1/3 MAX4053
5 SEC
C1
(Figure 1). If you ret
4
SEC
1 MAX4053
0.001 F
R2
R3
/3
AMPLIFY
place resistor R with
17.4k
7.21k 2
X0
9 S3 SAMPLE
2R, you create a posi13
15
X1 A
X
1
I3
tive RC time constant.
X1 A
I3
I2
X 14
Thus, you create a di12 X0
S2
I2
10
vergent exponential,
1 MAX4053
NOTE:
/3
C2
VINe1t/RC.
I1=I2=I3. THEREFORE, IF THE ON-RESISTANCES
750 pF
5
OF R1, R2, AND R3 ARE EQUAL, THEN
A
Instead of converg2
ON-RESISTANCE ERRORS CANCEL.
7
C3
AD8606
ing to zero, the wave750 pF
6
form theoretically diverges to infinity, and
C1
VOUT
C3=C2
2
V52VIN when t5T,
V54V IN at t52T,
V58VIN at t53T, and
Figure 2 Positive feedback from amplifier A1 causes C1 to increase in voltage, which exponenso forth. Therefore,
tially amplifies the input voltage.
you can amplify the in-
edn081030di43682
DIANE
designideas
put voltage by simply waiting the right
amount of time (t5log2(V/VIN)T) after
starting the negative discharge. The divergent exponential and the negative
time constant are the core concepts of
the circuit in Figure 2.
You can program the amplifiers gain
with a PWM (pulse-width-modulation) signal from a microcontroller or
another circuit. When the PWM signal goes to logic zero, sample-and-hold
capacitor C1 charges to VIN. When the
PWM signal cycles to logic one, op
amp A1 drives the R1C1 positive-feedback loop, creating a negative time
constant. The resulting divergent exponential rise of C1s charge continues
as long as the PWM signal remains at
logic one. That situation creates a net
voltage gain of:
VOUT(t)5VIN2(t/10 msec10.5).
the near-ubiquity
of programmabletimer/counter
hardware makes
it easy to digitally
generate a HIGHLY
repeatable PWMcontrol signal.
Thus, gain52(t/10 msec10.5) and log(gain)5
310.6 dB/msec. At the end of the amplification cycle, when PWM returns
to logic zero, amplifier A2 captures and
holds the amplified input voltage.
The logarithmic relationship between gain and timing provides excel-
Instrumentation amplifier
compensates system offset
from single supply
Luca Bruno, ITIS Hensemberger Monza, Lissone, Italy
Many integrated instrumentation amplifiers have architectures that permit offset compensation.
The reference terminals voltage, VREF,
RG
0.1%
R2
46.4k
0.1%
R1
23.2k
0.1%
IC1A
OPA2333
VA
5V
C1
100 nF
VREF
R3
46.4k
0.1%
R5
46.4k
0.1%
IC1B
OPA2333
VOUT
4
GND
VB
Figure 1 You can build an instrumentation amp operating from a single supply
that permits you to reset the system offset by applying a positive-correction
voltage to the VREF input.
of equal value but of opposite polarity. If the instrumentation amp operates from a dual-supply voltage, you
can easily provide both positive- and
negative-correction voltage. However, some instrumentation amps operate from a single supplyfor example,
in a battery-powered applicationto
amplify a signal source or a sensor that
introduces a positive offset voltage. A
sensor such as the AD590 from Analog Devices (www.analog.com), for
example, produces an output current
proportional to absolute temperature,
and you should calibrate it at the
lower reference temperature. In this
case, the output swing of the instrumentation amp decreases, especially
with high gain. To prevent this effect,
you must apply a negative-correction
voltage, which you generate from the
positive power supply. In precision
applications, the application of such a
voltage may cause a problem.
This Design Idea shows you how to
build an instrumentation amp operating from a single supply that permits
you to reset the system offset by applying a positive-correction voltage
to the VREF input. The circuit in Figure 1 employs the dual high-precision
OPA2333 op amp from Texas Instruments (www.ti.com). This op amp can
designideas
VO = 3 +
Equation 2
R 4 RR44 R 2 R 4REF
R2
pedance
connection
VO = VB 1 +VO = VB 1 + +
1
1 to preserve a
R 3 R 5 RG R3 RR35 RR
R3 RG
GG CMRR
good
(common-mode-rejec
tion
ratio);
otherwise,
R
R
R
R R R 4 R 2 4 R 2 4 R 4 R 4 4
R 4 you can use
R
+ 1VREF
. Vbuffer
1V+O = VB4 1 + + V4A 1 +2+12V
+ op-amp
1 + 1
1
an
A
REF
R 3R
R 3 R 5R G R 3 R
R53 RGRG R
G5depends
1RR3 G
R 5 on resistor-ratio
RR
1 RRGG R 3 which
G
R
mainly
matching. In this implementation, to
R 2 R 4 R 2 R4 R4 R4R4
R
VA 1 + + 1V+REF
.VREF 4 .
1
preserve an acceptable CMRR, you
2.8 k 92.8 k
. VA )1VREF .
VO = 3(+VB1VA )1V
( VREF
B1
RG
R G Equation 3
Equation 3
Equation 3
2R
RG
, =
CMRR
R
R
2R
RG
CMRR =
, =
CMRR
R
6
R
3+
2R
RG
,
R
6
R
3+
2R
RG
,
R
6
R
3+
RG
( VB1VA )1VREF .
Equation 3
2R
RG
CMRR =
,
R
6
R
3+
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
lights LEDs
IN
LT3080
VCONTROL
VOUT
OUT
SET
1 F
R
RSET
R
C
R/K
200
KC
C
2k
4.7 F
Figure 1 This oscillator generates a low-distortion sinusoidal signal with power-driving ability.
edn081127di43891 DIANE
(in 12-15 folder)
10
IN
LT3080
VCONTROL
VOUT
OUT
SET
6.3V,
150-mA
LIGHT BULB
47 nF
10 F
8.45k
4.7 F
2.21k
499k
10
220 nF
8.45k
121
47 nF
Figure 3 To automatically control the gain, you can replace the potentiometer
with a light bulb.
edn081127di43893 DIANE
(in 12-15 folder)
IN
LT3080
VCONTROL
VOUT
OUT
SET
100
100k
3.1V
47 nF
1 F
10 F
8.45k
20k
2.21k
499k
4.7 F
10
VN2222LL
220 nF
8.45k
47 nF
200
10 F
20k
Figure 4 You can automatically control the gain by replacing the potentiometer
with a variable-resistance MOSFET.
edn081127di43894 DIANE
(in 12-15 folder)
designideas
can use the simple circuit as a dc-biased ac source in applications requiring low distortion and power-driving
capability.EDN
Ack n owle d g m e nt
The authors wish to thank Tony Bonte,
Mitchell Lee, Jim Williams, and Todd
Owen for fruitful discussions.
LEDs
RSENSE
VIN
CIN
D1
1
VIN
VCC
MAX16820
2
PWM
DIMMING
3
CS
DRV
DIM
GND
designideas
the LED string is VF5D3VIN, where
D is an internal duty cycle that the
ICs switch-mode section produces; do
not confuse this duty cycle with that
at the Dim pin. You reference the driver signal to ground and limit it to the
power-supply voltage, VCC, at 5V. That
condition allows the use of low-voltage
ADCs or comparators, which the LED
drivers VCC output, a maximum of 10
mA, can power.
Figure 2 shows how to detect a
short-circuited LED with the aid of a
comparator. Filter R1C1 converts the ac
PWM signal at the driver to a dc voltage, VD, proportional to D3VCC. You
should sample VD when its value is
greater than perhaps 90% of its steadystate value; this sampling requires a
period of at least 2.3R1C1. Because the
comparators LE (latch enable) latches
the output when LE is low, LE should
assert not earlier than 2.3R1C1 after
the Dim pin goes high. R2, C2, and D2
ensure that LE deasserts immediately
after the Dim pin goes low. The value
of R2C2 is higher than that of R1C1,
so the comparator enables when the
input signal reaches at least 90% of its
steady-state value. D2 immediately discharges C2 after the Dim pin goes low,
which latches the output as soon as the
LEDs turn off.
Because the reference voltage is
lower than D3VIN, the comparator
output is normally low. If an LED fails
(a)
LEDs
RSENSE
VIN
CIN
D1
1
VIN
VCC
MAX16820
2
PWM
DIMMING
3
CS
DRV
DIM
GND
4
R1
C1
VD
REF
MAX9141
LED SHORT
LE
D2
R2
C2
Figure 2 Adding this comparator circuit to the Figure 1 circuit provides detection of shorted LEDs.
edn081127di44032 DIANE
shorted, its forward
voltage drops and
(IN 12-15 FOLDER)
causes the duty cycle at the driver to
drop. VD then drops below the reference, causing the comparators output
to go high, indicating a shorted LED.
Because the output latches when the
Dim pin goes low, the error signal remains asserted even when the LEDs are
off. Figure 3 shows the filtered Dim pin
and driver signals for normal operation
versus a shorted-LED condition.
For a system with an input voltage of
12V and three LEDs in series, in which
the forward voltage is approximately 3V
(b)
Figure 3 For a system with an input voltage of 12V and three LEDs in series,
in which the forward voltage is approximately 3V per LED (a), the filtered driver
signal (green) stabilizes at approximately D3VCC5(9V/12V)5V53.75V. The comparator latches when the filtered Dim signal (yellow) goes lower than 2.5V, so the
comparator begins interpreting the filtered driver signal after approximately 100
msec. Clearly, VD is higher than the threshold reference voltage (red) when the
comparator is active. After one of the LEDs shorts out (b), VD stabilizes at approximately (6V/12V)5V52.5V and no longer exceeds the threshold.
per LED (Figure 3a), the filtered driver signal (green) stabilizes at approximately D3VCC5(9V/12V)5V53.75V.
The comparator latches when the filtered Dim signal (yellow) goes lower
than 2.5V, so the comparator begins
interpreting the filtered driver signal
after approximately 100 msec. Clearly,
VD is higher than the threshold-reference voltage (red) when the comparator is active. After one of the LEDs
shorts out (Figure 3b), VD stabilizes at
approximately (6V/12V)5V52.5V and
no longer exceeds the threshold. That
condition causes the comparators output to go high, indicating that one of
the LEDs has become a short circuit.
The choice of filter constants R1C1
and R2C2 depends on several parameters. The cutoff frequency should be
low enough to properly filter the driver
signal yet small enough to allow the filtered signal to stabilize near the steadystate value achievable within the
shortest dimming pulse. You can easily
adjust this circuit to detect open-circuit LEDs. When an LED breaks and
stops conducting current, the drivers
duty cycle goes to 100% when the Dim
pin is high. If you then swap the comparator-input connections and put the
reference voltage slightly below VCC,
the comparator output goes high in response to an open LED.EDN
designideas
Single pin controls relay,
intermittent buzzer, and status LED
Kartik Joshi and Manik Chugh,
Netaji Subhas Institute of Technology, Delhi, India
Switching applications involving controlling devices or appliances using digital-I/O lines through a
relay often need to indicate the change
of state of the I/O line and, hence, the
connected device. This indication
12V
K1
D1
D2
IN4001
R9
1.5k
R7
1.5k
PA1
R10
1.5k
MVCC
Q3
2N2222
Q2
BC558A
R11
1.5k
BUZZER
B1
Q1
BC547A
R12
47
C6
1000 F
Figure 1 This circuit controls a device through a relay and an intermittent buzzer
with only one digital-I/O pin.
edn081030di43371 DIANE
Figure 2 A Spice simulation of the buzzer circuit replaces the buzzer with 50V
resistance and plots the current through the buzzer and the status of the I/O
line.
sign Idea discusses a circuit that controls a device through a relay and an
intermittent buzzer with only one digital-I/O pin.
Pin PA1 of the digital device controls
a relay, which switches an appliance on
and off (Figure 1). NPN transistor Q3
activates the relay coil when the I/O
line is in the high state. Status LED D1
connects in parallel to the relay coil
and turns on when the I/O line is high
and off when the line is low.
The buzzer remains on for a small
amount of time when the relay changes state. You accomplish this task by
employing a push-pull-inverter topology using complementary BJTs (bipolarjunction transistors) NPN Q1 and PNP
Q2. The output of this stage connects
to a bridge rectifier with a buzzer as a
load because buzzers usually are unidirectional. The bridge rectifier connects
in series both with resistor R12 to regulate the maximum current through the
buzzer and with capacitor C1 to ensure
that the buzzer fades off. When the
line is low, transistor Q2 is on, the capacitor charges to a positive voltage,
and the buzzer operates until the current through it is sufficient. When the
line goes high, transistor Q1 switches
on, the capacitor discharges to approximately 0V, and the buzzer operates again for a short duration. The
on-time of the buzzer depends on the
values of REQ, the series combination
of R12 and the buzzer resistance, and
C6. To change the time constant and
hence the on-time of the buzzer, you
should change the value of the capacitor rather than that of the resistor. You
can also design this circuit using only
one BJT instead of two, but the transistor would always draw some current
at steady state.
This topology is useful when no
separate I/O lines are available for
controlling the buzzer. You can also
employ this topology to indicate the
change of state of any input stage directly by connecting it to the given
circuit or through a buffer. Figure 2
shows a Spice simulation of the buzzer
circuit. This simulation replaces the
buzzer with 50V resistance and plots
the current through the buzzer along
with the status of the I/O line.EDN
designideas
Simple two-transistor circuit
lights LEDs
Barry A Tigner, Michigan State University, East Lansing, MI
R2
1k
L1
180 H
2N3906
Q1
R1
1M
C1
47 pF
B1
1.5V AA
Q2
LED1
2N3904
R e fe r e nce
Figure 1 This two-transistor circuit operates as a high-gain amplifier to light LEDs.
edn081215di44101 DIANE
PLACED IN THE 2-1 FOLDER
the feedback capacitor and the inputstage impedance. The circuit oscillates
at 91 kHz with a 48% duty cycle. You
can use almost any common NPN or
PNP transistors, as long as they have
moderate forward-current gain of 50 or
more and can handle 100-mA collector currents.
The LED connects across the output transistor because this approach
lets the inductive kickback voltage
add to the battery-supply voltage
and makes the LED brighter. This
circuit operates well from approximately 0.8 to 1.6V, which is the useful range of an alkaline battery. The
LED-light output decreases as the
supply voltage decreases from 1.6 to
0.8V.EDN
1 Bruno, Luca, Astable multivibrator lights LED from a single cell,
EDN, Aug 21, 2008, pg 53, www.
edn.com/article/CA6586223.
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
48 DAC and flip-flops form
V1
1V
R3
3.5k
R2
2k
R6
2k
RLOAD
2k
R11
3k
R13
10k
edn081205di43491
Equation 2
V1
1V
LOOP 1
R6
2k
R14
2k
R10
2k
R9
8k
R1
2k
R12
2k
V2
2V
V4
5V
(2k
)
I
(0)I
(0)I
+(4k)I
(2k)I
(0)I6 5V
1
2
3
4
5
(0)I
(2k)I2
(0)I 3 (2k)I 4 +(14k)I 5 (2k)I6 2V
1
(0)I2
(3k)I 3 (0)I 4 (2k)I 5 +(17k)I6 2V
(0)I1
R8
8k
R5
2k
R7
2k
constant-current source
must produce the same current through
52 Convert negative inputs
the load. The total resistance in the
to positive outputs
Thevenin circuit is RTOTAL5(V TH/
ILOAD)5(374.095 mV/60.301 mA)Q
ETo see all of EDN's Design
6.203 kV, where RTOTAL is the total reIdeas, visit www.edn.com/design
sistance. Therefore, the Thevenin resisideas.
tance is simply [(VTH/ILOAD)2RLOAD]5
(RTOTAL2RLOAD)56.203 kV22 kVQ
4.203 kV, where VTH is the Thevenin
voltage and ILOAD is the load current.
Without the aid of simulation, you
Figure
4 shows
the TheveninEquation
for di4349
(12-5-08 issue)can calculate VTHEVENIN and RTHEVENIN
equivalent circuit, and Figure 5 shows as follows. The array for the loop curthe Norton-equivalent circuit. Note rents in Figure 2, assuming a clockthat, because the net current through wise current flow in each loop, gives
Equation 1
the load flows to the left, the posi- the current through the load resistive Thevenin terminal is grounded. tance (Equation 1).
R3
3.5k
R2
2k
LOOP 2
RLOAD
2k
R8
8k
R5
2k
B
LOOP 3
R12
2k
R11
3k
(0)I 4
(0)I 5 1V
+(6k)I1 (2k)I2 (2k)I 3 PROBE
1
V
(2k)I +(4k)I
(
2
k)I
(0)I
(0)I 52V2 5V
1
2
3
4
7
10
(
0
)I
(0)I
(2k)I
+(15k)I
(3k)I
2k
0V
2k
1
2
3
4
5
V4
R
R
(0)I
13
(0)I2
R14
2k
Figure 2 The simulation for current through the load resistance yields
260.3 mA.
DIANE
edn081205di43492
DIANE
APRIL 23, 2009 | EDN 47
designideas
XMM1
RTHEVENIN
4.203k
R1
2k
PROBE 1
R3
3.5k
RLOAD
2k
VTHEVENIN
0.374095V
R8
8k
Equation 1
LOOP 1
R6
2k
R2
2k
R5
2k
LOOP 3
A
LOOP 4
R12
2k
R11
3k
B
V2
(0)I 3 (2k)I 4 2V
(0)I 5
(0)I6 1V
+(6k)I1 (2k)I2
R14
(2k)I +(9.5k)I
LOOP 2
LOOP 5
(0)I 4 R(2k)I
(0)I62k 0 V
R7(2k)I 3
1
2
5
10
2k
(0)I1 (2k)I
+(15k)I
(0)I 4
2k
(0)I 5
(3)I6 0 V
3
V4 2
R9
R13
.
5V
(0)I 3 +(4k)I
(0)I6 5V
8k
(2k)I1 (0)I2
4 (2k)I10k
5
(0)I
(2k)I2
(0)I 3 (2k)I 4 +(14k)I 5 (2k)I6 2V
1
(0)Isimulation
(0)Ifor
(3k)I 3 (0)I
(2k)I
Figure 3The
open-circuit
voltage
approximately
1
2 the
4 yields
5 +(17k)I6 2V
edn081205di43494
DIANE
PROBE 1
INORTON
8.9005A
RNORTON
4.203k
RLOAD
2k
2374 mV.
(2k)I 3
+(15k)I 4 (3k)I 5 0V
(0)I1 (0)I2
(0)I
(0)I2
(2k)I 3
(3k)I 4 +(14k)I 5 2V
1
(2)
rent pin (Pin 19). The AD5422s internal shift-register data moves into
the data register at every low-to-high
transition of the latch signal (Pin 7).
The device interprets this alternating
bit sequence as a control command
during the 23rd time you press and release the switch after IC1s power-up.
After that sequence, the SCLK signal
can remain idle (Figure 2).
Flip-flop FF1, configured as a familiar
divide-by-two counter, produces the
desired alternating sequence. Manually
pressing and releasing the pushbutton
switch, you cause the generation of an
SCLK signal. You must use a debounc-
designideas
er because the circuit requires a clean
logic signal for SCLK with level transitions that do not exceed a few 10s of
nanoseconds. FF2 acts as an asynchronous set/reset flip-flop that debounces
the signal from the button.
For the circuit to work properly,
the active low-to-high transition of
the latch signal must occur at least 13
nsec after the low-to-high transition of
SCLK. You can fulfill this requirement
MSB
D23
D15
D11
D7
D4
LSB
D2 D0
15V
100 nF
OUTPUTRANGE
SELECT
NC
10k
2
3
NOTE:
LSB ENTERS THE INTERNAL SHIFT REGISTER AS A LAST BIT.
4
5
6
7
8
9
10
11
12
AVSS
IC1
AD5422
AVDD
DVCC
VSENSE
FAULT
VSENSE
GND
CLEAR SELECT
VOUT
BOOST
CLEAR
IOUT
LATCH
NC
SCLK
CCOMP
SDIN
DVCC SELECT
SDO
AGND
GND
edn081127di43932 DIANE
(PLACED IN THE 12-15 FOLDER)
REFIN
REFOUT
RSET
24
23
22
21
20
NC
NC
NC
NC
19
18
17
16
NC
IOUT
RL
1200
NC
NC
15
14
13
NC
5V
14
13
12
11
10
VDD
S Q
CLK
IC2
SN74HC74
470k
R
D
FF1
47 nF
470k
S1
CLK
R
Q
FF2
GND
0V
Figure 1 After you press and release S1 23 times, the DAC produces a constant-4-mA-current output.
designideas
source, which is no more than a few
10s of microamperes, is harmless to the
precision of the reference source.
By connecting a high-precision,
100V resistor between the IOUT pin and
ground and generating 23 clock pulses,
You can obtain a precise, positive-output voltage from a negative-voltage supply with a boost converter and a linear regulator. The input
and output capabilities of the circuit in
Figure 1 depend on the allowable I/O
voltages of IC1 and IC2. In this case,
IC1 and IC2 convert a 25V input voltage to a 3.3V output voltage.
IC1 is a boost converter that accepts
22 H
SW
4.7 F
VCC
SHDN
FB
100k
IN
LX
IC1
MAX8574EUT
R e fe r e nce
3.3V
OUT
IC2
MAX8875EUK33
D1
CMDSH2-3
10 pF
R1
2.1M
R2
287k
1 F
SHDN
POK
GND
GND
1 F
POWER OK
1 F
5V
edn081205di43911 DIANE
(PLACED IN THE 12-15 FOLDER)
COMMON
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
32 Use an LED to sense and emit
light
L2
12V
of lithium-ion batteries
R2
10k
0.37-kW, 230V-AC
PUMP MOTOR
11
480V-AC, 16A
SOLID-STATE
RELAY
RDN 275/14
METAL-OXIDE
VARISTOR
R2
560k
L1
B
4
6
7
8
TANK
PIEZOELECTRIC
BUZZER
C
10
12V
R1
100k
C
0.01 F
edn081215di44041 DIANE
PLACED IN 2-5 FOLDER
FUSE
14
12V
230V AC
designideas
makes the output of Gate D go to a low
level, which stops the oscillator and
thus the piezoelectric buzzer.
The circuit uses HCF4093B Schmitttrigger-input NAND gates to square
the slow signals. The input resistor,
R1, has a value of 560 kV. Checking
the circuit with a glass of filtered water
shows an improved conductivity for
ground water. Raising the value of the
input resistor to a higher value is also
not objectionable after you account
for pickup and the voltage drop across
the resistor due to the input leakage
current.
The solid-state relay may have backto-back connected SCRs (silicon-controlled rectifiers), random turn-on,
and snubber circuitry to handle the
motor load (Reference 2). Choose an
SSR with a voltage rating that is double the working voltage and five to 10
times the current rating of the motor
for withstanding dV/dt and the surge
current. You should also use fast-blow
fuses or semiconductor fuses with less
than the I2t rating of the SSR, where
I is the current and t is the duration
of current flow in seconds. Choose appropriate SSRs for different ratings of
pump motors.
R e fe r e nce s
Solid-state relay applications,
Western Reserve Controls, www.
wrcakron.com/applications/SSR_
applications.pdf.
2 Single-phase SSRs, ERI Solid
State Relays, 2007, www.electronic
relaysindia.com/prod_001sjk_3.html.
1
12V
L2
12V
14
11
D
R2
10k
0.37-kW, 230V-AC
PUMP MOTOR
FUSE
M
R2
560k
L1
480V-AC, 16A
SOLID-STATE
RELAY
6
7
RDN 275/14
METAL-OXIDE
VARISTOR
230V AC
TANK
12V
PIEZOELECTRIC
BUZZER
C
10
12V
R1
100k
C
0.01 F
edn081215di44042 DIANE
PLACED IN 2-5 FOLDER
designideas
Use an LED to sense and emit light
VCC
COUNT 4
UP COUNTER
CLOCK
Q[3..0]
STATE 2
4-BIT ADDER
CIN
DATAA[3..0]
PWM[3..0]
DATAB[3..0]
CNT_EN
A
RESULT[3..0]
A+B
B
ACLR
STATE 0
NAND2
CATHODE
COUNT 4
OUTPUT
INTENSITY[7..4]
INSTA
STATE 2
OR2
LED
NOT
INSTB
BIDIR
ALT_
IOBUF
INSTC NOT
PIN 1
INPUT
BUFFER
COUNT 8
UP COUNTER
OSCILLATOR 1
CLOCK
STATE 1
INSTD
OR2
ANODE
AND2
CNT_EN
COUNT 8
STATE 0
NOT
INSTE
CLRN
LIGHT-INTENSITY MEASUREMENT
INSTG
STATE 1
COUNT 12
INPUT
UP COUNTER
CLOCK
Q[11..0]
COUT
COUNT 12
SHIFT 8
CLOCK
ENABLE
RESET
COUNT
FREQ
PWM
ASET 1
STATE 0
STATE 1
STATE 2
SHIFTOUT
SHIFTIN
INPUT
RESET
WAIT
LEFT SHIFT
8-Hz
OSCILLATOR
Q[7..0]
STATE[7..0]
ASET
STATE MACHINE
Figure 1 This simple MAX IIZ circuit uses an LED as an emitter and a sensor.
COUT
ACLR
INSTF
DFF
PRN
INTENSITY[7..0]
Q[7..0]
DFF
32-kHz
OSCILLATOR
COUT
ADDER
STATES
3 TO 7
designideas
cles exiting the light sensor. The circuit senses the light by biasing the LED
and current-limiting resistor such that
the cathode lead of the LED is at logic
one. The anode connects to a relaxation oscillator that starts with anode
at logic zero. The LED pulls up the
anode in proportion to the amount of
light hitting the LED. The reverse-biased LED acts as a solar cell with output current proportional to light. Once
the slow-rising anode signal reaches
the threshold of the input buffer, the
Pin 1 signal becomes a zero, and the D
flip-flop, DFF, toggles to zero and drives
the anode signal to zero, making Pin 1
a logic one and tristating the input buffer on the next clock cycle, allowing
the anode signal to rise again.
The frequency of Oscillator 1 is proportional to light intensity, with typical frequency for bright light of approximately 2000 Hz. The Oscillator
1 signal drives the clock of Count 8.
Count 8 resets in State 0 and then is
enabled in State 1 for 125 msec. In
bright light, Count 8 might count to
250 at the end of the measurement,
and, in low light, it might count to
only 16. The counters COUT signal
feeds back to the enable so that the
count will saturate at a count of 255
and prevent high-intensity light from
wrapping the counter back to zero and
taking a false measurement.
designideas
Equations for DI4439 PLACED IN THE MARCH 5 FOLDER
15V
and diodes provide bias to Q1 and Q2
VDD
to eliminate
distortion.
ICIN
Equations crossover
for DI4439
PLACED
THE
MARCH
5
FOLDER
2
VIC1
provides error
correction
Equation
1 and accounts
VIN
IC
R1
VOUTIC1
1
for deltas in the base-to-emitter voltAD620BN
V
IC1
Equations
for
DI
4439
PLACED
IN
THE
MARCH
5
FOLDER
Equation
1 THE
1 52FOLDER
VREFIC1
15V
tion to the output voltage, feeds into
IC1 typical
IC
2 accuracy
achieves
a
0.01%
dc
Equations
for
DI
4439
PLACED
IN
THE
MARCH
Equation
2 V1 A
Equation
.
+
V
= 610V
+ VREF
+V
VI+REF
. 1 span
OUT
IC1 and
C1
1 A
across
input
1.5%
TIC1 = VIC1VIC
ICIC
1 a1
IC1
VIC2
IC
IC
1
VOUTIC2
typical
ac
accuracy
at
1
kHz
with
an
C1 A IC1 + VREFIC1 .V
AD620BN V
+
V A
V
= VOUT
= +V
+to-current
VREFIC
Equation
IC2
VEquation
+ 2VREF
. 2 . converter
REF
output
voltage
of1 =65V
2IC
IC1 OUT
IC
C1IC2VIC1 ICA2IC1 IC
IC1
23 Ip-p.
+
+
+
V
=V
=
V A + V
.
R1
5k
Q1
)(
( (
VOUT RL
IOUT
D2
1N4148
Q2
R2
5k
2N2904
) )
15V
)
( ( ) )
( ) + VREF ,
V
A
,
(
)
)
IC
1
V
=
=
V
A
+
.
)
(
)
IC
1
2
V
T = VOUT =V(REF
IC
1
IC
REF
( IC2IC2 ) IC2 REF
IC1
OUT
+ V 3A
+ V
+
A IC=2 +
VREF =+, A
+
VEquation
V
)
(
)
IC
1
IC1
IC2VEquation
VIN ,4V
VREF+ =V0+. V
VEquation
ICV2 = 1);A
5 0; A
= VOUT
=IC( 1VIC1
IC1 =
) AIC2 + VREF ,
OUT
IC1 ( IC2
where
Equation
4
+
+
ion
4
Equation
VOUT = VOUT
= ( V3IC1V ) A IC1 + ( VIC2V ) A IC2 + VREF ,
+ =V ,V
= 0; A IC1 = A IC2 = 1; VREF = 0.
VIC
IN
1
Equation
5 =4V + + V + V
+ = V Equation
V
)+, = 0. ) AIC2 + VREF ,
VOUT
= 0;+REF
AIC
= VIN , V =V0V
; IC
A1IC=1V=IN
A, IC
. IC
IC11 ==(0A
IC22 = 1; VREF
2 ==1(;VVIC
OUT
OUT
1V ) A IC1 + ( VIC2V
C1
2N2222
D1
1N4148
15V
=V
= VICIC12 VIC
Aapproximately
VIC2 A IC2
V
equal
REFICV
OUT
IC12is
ICREF
1 + ICV
1 OUT
ICOUT
2
2 IC2
IC1IC2
3 =2 +
Equation
+ Equation
+
to
the
emitter
current
=
V
V
A
+
V
.
V
VOUTIC 2 =VV
V
A
+
V
.
V
A2ICIC12 +ICV2REFIC
REF
OUT
2 . REFedn090305di44391
V
2IC1ICIC
REF
OUT
2 2 IC1 IC
IC 2
DIANE
ICICIC
211= ICV
IC1
IC2
IC 2
IC1
IC1
IC1
IC2
IC 2
IC1
IC1
IC1
IC1
IC 2
IC2
IC1
IC1
IC1
IC1
IC 2
IC2
IC1
IC 2
IC1
IC2
IC 22
1 IC
IC 2
IC 2
or
DIANE
0.1
IC 2
IC 2
IC 2
IC2
ERROR
(%)
Equation
4 2 = 1Therefore,
A
; VREFIC 2 = +0.
IC1 = A IC
Equation
; A IC1 = A IC2 = 1; VREFIC 2 = 0.
VIC1 +=5 VIN , V+IC1 = 0
0.01
VOUT =Equation
+
V
V
IC1
6 IC2VIC2 ,
Equation
5
ion+ 5 = V , Equation
4
V
=
0
;
A
=
A
=
1
;
V
=
0
.
VIC1
IN IC1
IC1
IC2
REFIC 2
edn090305di44392
IC2
IC 2
IC2
IC1
IC 2
IC 2
IC 2 IC 2
IC1
IC1
IC1
IC2
IC2
IC 2
IC1
IC1
IC
1
IC
2
IC2
IC1
IC1
IC1
IC 2
IC 2
IC 2
R LOAD =1 k
R LOAD =100
+ +
+ V ,
Equation
5VINV.IC
= VIC
2
+ = VVOUT
I OUT
=;1 A
,
V
=
0
=2A ICIC
VIC
IC
1
IN
IC
1
2 = 1; VREFIC 2 = 0.
1
= + +6 + R
+ +
+VVEquation
LV
,
V
V
=
,
IC
2
OUT
V
V
IC
1
IC
2
IC
2
TEquation
0.001
IC1 5 IC2
0.1
1
10
100
0.01
V
This circuitVIN
provides
a
wide
output
IC2 ,
IOUT (mA)
+
+
V=OUTas
VIC2is ,
I OUT
Equation
6 =. VIC1 +current
VIC2
range,
that
Equation
5as well
R L output
Equation
6
+
+
to the input voltion
6 = V +directly
VOUT
VIC2 ,
VIC2proportional
IC1
Figure 3 The circuit in Figure 2 provides a wide output range, output current
VIN
age and
high
and precision
I OUT
= linearity
.
that is directly proportional to the input voltage, and high linearity and precision.
R+ 6
(FigureV+IN
3).
EDN
Equation
V
VIOUT
VIC2 ,
. VLIC
= IN .
OUT ==VIC1 +
2
RL
EDN090205DI4439FIG3 MIKE
RL
Equation
6
VIN
I OUT =
.
RL
VINEquation 6
I OUT =
.
RL
situations occur. This fact doesnt
V
I OUT = IN .
mean, however, that all cells are bad.
RL
Lithium-ion batteries are sensitive to bad treatment. Fire, explosions, and other hazardous condition may occur when you charge the
cell below the margin that the manufacturer defines. Modern battery chargers can manage the hazardous conditions and deny operation when illegal
In most cases, you can replace the discharged battery and increase your devices lifetime. Figure 1 shows the circuit for testing battery packs.
When the supply voltage is lower
than 2.6V, no current drives the base
of the transistor. LED1 lights up, and
designideas
LED2 is off. When the voltdevice as a permanent display,
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
RSENSE
VIN
5
VIN
IRF520
LOAD
R1
100
10k
4.7 nF
IOUT
GND
VREF
0.25k 0.5k 1k
2.5k 5k 10k
0.125k
1.25k
4
9
2
0
100 TO
900 mA
3
6
1
2
2
0
12.5k
RLOAD
TLC271
ZXCT1010
VOUT
4
10 TO
90 mA
2
0
1
2
7
6
4
1 TO
9 mA
Figure 1 Passing current through a MOSFET and regulating it with a currentsense monitor bypasses the BCD switches, letting you increase load current.
edn090423di44401 DIANE
(PLACED IN THE MAY 1 FOLDER)
stepper motors
best-fit calculator
54 Automatically turn
designideas
the cuprum materials 35-micron-thick
layer. The BCD switches are in paral
lel and connect from 125V to 100 kV
to adjust the output voltage on the
op amps negative input. The equa
tions to calculate resistor values are:
VSENSE5RSENSE3ILOAD, IOUT5RSENSE3
ILOAD/100, and R05VREF3100/(RSENSE3
ILOAD). If you choose a value of 0.1V
for the sense resistor and a value of
0.1V for the reference voltage, the
Multiplexed, programmable-gain,
track-and-hold amplifier
has instrumentation inputs
W Stephen Woodward, Chapel Hill, NC
R1
12.1k
VOUT
TO ADC
MAX4051
VIN
13
14
15
12
1
5
7
4
CH0
CH1
3
CH2 COM
CH3
11
A
CH4
10
B
CH5
9
C
CH6
8
EN
CH7
R4
2.21k
T=14.4 SEC
3
C1
0.001 F
LT1022A
2
R3
28.7k
R2
28.7k
GROUND
REFERENCE
MAX4051
VIN
13
14
15
12
1
5
7
4
CH0
CH1
CH2 COM
CH3
A 11
CH4
10
CH5
B
9
C
CH6
8
EN
CH7
JUMPER FOR
SINGLE-ENDED
CIRCUITRY
ADDRESS (0=AMPLIFY)
HOLD
OPTIONAL DIFFERENTIALINPUT CIRCUITRY
NOTES:
NEGATIVE TIME CONSTANT=T=(R1+R4+2RON)(C+CSTRAY).
VOUT =VIN[1+(R3/R2)E(t/T)] =VIN2(1+t/10 SEC).
edn081002di43061 DIANE
PLACED IN THE 10-16 FOLDER
designideas
only the resolution of the
SAMPLE AND
SAMPLE AND
HOLD
HOLD
CONVERT HOLD
CONVERT HOLD
amplify intervals timing
T=R4C
T=R4C
T=RC
T=RC
limits gain-set resolution
VOUT
AMPLIFY
T
ACQUIRE
AMPLIFY
ACQUIRE
(figures 2 and 3). This cir
cuit also has 610V output2VIN
amplitude capabilitytwo
to four times greater than
that of monolithic digitally MULTIPLEXER ADDRESS
ADDRESS=0
ADDRESS=N
ADDRESS=M
ADDRESS=0
programmable-gain instru
t=
mentation amplifiers.
LOG2(GAIN)1
HOLD
The inherent noise and
dc accuracy of the chosen
op amp, the accuracy and Figure 2 Only the resolution of the amplify intervals timing limits gain-set resolution.
repeatability of the timing
of exponential generation, ADC sam
64
pling resolution, and RC-time-con
60
stant stability are the main limits on
56
52
signal-processing performance and the
48
edn081002di43062 DIANE
amplifiers precisionfor example, its
44
PLACED IN THE 10-16 FOLDER
40
gain-programming accuracy, dc error,
GAIN 36
noise, and jitter. In the circuit, 1 nsec
32
of the amplify-interval timing error or
28
24
jitter equates to 0.007% of gain-pro
20
gramming error.EDN
16
N
12
8
4
0
R e fe r e nce
Woodward, W Stephen, Flying
capacitor and negative time constant
make digitally programmable-gain instrumentation amplifier, EDN, Feb 5,
2009, pg 48, www.edn.com/article/
CA6632372.
10
20
30
TIME (SEC)
40
50
Figure 3 This graph of input- and output-voltage gain shows the time elapsed
since the track/amplify-logic transition.
EDN090528DI4306FIG3
MIKE
The circuit in this Design Idea drives lowpower, unipolar stepper motors using only a
shift register, a few resistors, and low-power transis
tors. Adding an inexpensive 4053 analog switch al
lows bidirectional switching. Compared with other
simple stepper-motor-drive circuits, it has betterthan-half-step characteristics (Figure 1).
After power-up, all shift-register outputs are in a
zero state. Pin QP3 feeds back to the serial input
through an invertertransistor Q5 in Figure 2 and
analog-switch IC2 in Figure 3. The circuit generates
a sequence of four ones and then four zeros. You can
use this pattern to drive, for example, NPN tran
sistors with emitters that tie to ground and collec
tors that tie to the stepper-motor coils. However,
designideas
to achieve smoother drive character
istics, the shift-register outputs drive
four simple DACs, each comprising
two identical resistors.
5V
R1
4.7k
Q5
FEEDBACK
5V
R2
4.7k
BCR133
QS1
2
5V
STEP_CLOCK
QS2
QP0
1
STR
15
OE
3
CP
IC1
4094
QP1
QP2
QP3
QP4
Q1
R3
4.7k
9
10
BC846B
5V
R4
4.7k
4
5
Q2
R5
4.7k
6
7 FEEDBACK
BC846B
5V
R6
4.7k
14
QP5 13
12
QP6
11
QP7
Q3
R7
4.7k
BC846B
MOTOR
5V
R8
4.7k
COIL 1
LEFT TAP
Q4
R9
4.7k
COIL 1
COIL 2
RIGHT TAP LEFT TAP
COIL 2
RIGHT TAP
BC846B
Figure 2 This circuit drives low-power, unipolar stepper motors using only shift-register IC1 and a few resistors and
transistors.
IC2A
4053
15
IN1
OUT
IN0 2
CTL
10
5V
EN
edn090305di44141
DIANE
R20
(SAVED 4.7k
IN 3-19 FOLDER)
6
FEEDBACK
QS1
QS2
5V
STEP_CLOCK
D
1
STR
15
OE
3
CP
QP0
IC1
4094
QP1
QP2
QP3
QP4
9
10
4
5
6
7 FEEDBACK
14
QP5 13
12
QP6
11
QP7
5V
R21
4.7k
R22
4.7k
R23
4.7k
Q1
BC846B
13
12
R24
4.7k
IN1
R27
4.7k
IC2B
4053
OUT
14
Q2
IN0
EN
6
R25
4.7k
R26
4.7k
5V
BC846B
CTL
11
5V
TO MOTOR
Q3
BC846B
5V
IN1
IC2C
4053
OUT
IN0
EN
6
CTL
9
4
Q4
BC846B
DIRECTION
Figure 3 This circuit enhances the one in Figure 2 by adding an inexpensive 4053 analog switch, allowing bidirectional
switching.
50 EDN | may 28, 2009
edn090305di44142
DIANE
designideas
Excel spreadsheet yields RLC best-fit calculator
Alexander Bell, PhD, Infosoft International Inc, New York, NY
Parameter
Description
Required
Target value
Yes
ParSer
Yes
ESeries
ExtSearch
designideas
Automatically turn
secondary lamp on or off
Vladimir Oleynik, Moscow, Russia
T1
1
NC
2
SPARE
LOAD
NO
COM
SPARE-LOAD
POWER SUPPLY
Figure 1 A transformer and a relay are all you need to control a secondary load
should the main load fail.
edn081205di43881
(single-pole/double-throw) commuta
tion of 240V ac under a 40A load.
Using an SPDT relay adds flexibility
in controlling the spare load. It lets you
switch a load on or off with no need for
additional electronic components. In
the figure, a spare lamp turns on when
the main lamp burns out because the
secondary load connects to the relays
NC contact.
Select a transformer whose second
ary winding (Winding 1 in the figure)
has a low-rated voltage that provides
sufficient current for the main load
the lamp. Match the relays rated coil
voltage to the ac-mains voltage and
frequency specifications.EDN
DIANE
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
When dealing with logic operations over BCD (binary-codeddecimal) numbers, you often need a
10-line-to-one-line data selector/multiplexer. In the past, you could use
the famous 16-line-to-one-line 74150
multiplexer IC. Nowadays, however,
when you look at the Web sites of the
renowned semiconductor houses for
the 150 and similar 16-to-one multiplexers, such as the 250, the 850, or the
851, you find that vendors have labeled
them obsolete or no longer available.
On the other hand, the eight-line-toone-line multiplexers not only have
survived but also are parts of advanced
logic families, such as HC (high-speed
CMOS) and AC (advanced CMOS).
The circuit in Figure 1, a 10-lineto-one-line data selector/multiplexer,
comprises two eight-to-one multiplex-
OUT
Y2
Y
ADDRESS
INPUTS
A
B
C
D
G
A
IC1
CD74AC151
B
C
D0 D1 D2 D3 D4 D5 D6 D7
D0
D7
W2
Y
G
A
IC2
CD74AC151
B
C
D0 D1 D2 D3 D4 D5 D6 D7
D8 D9
DATA INPUTS
Figure 1 The maximum worst-case propagation delay of this 10-line-to-one-line data selector/multiplexer is 27 nsec,
whereas the typical value is only 6.8 nsec. The circuit can also serve as a 12-to-one multiplexer.
designideas
IC2. The output signal of IC1 passes
through one of these data inputs to
the main output, Y2. If necessary, you
can also use the W2 inverting output.
Although the propagation delay from
D0 through D7 to Y2 output is twice
that from D8 and D9 to Y2, it is still
and some buffering registers. The algorithm runs at eight times the serialdata-stream speed, without a known
phase relationship between both. It
clocks the data into the shift register,
Jef Thon and Bob Puers, ESAT-MICAS,
which implies that, after eight clock
Katholieke Universiteit Leuven, Leuven, Belgium
cycles, the shift register will contain a
Serial-data links embed clocks edge detection, a 7-to-1 multiplexer rising edge; a falling edge; or, when the
in their data streams, and those with decoding for multiplexing the input data remains the same, no edge.
clocks must be recovered at the receiv- right-shift-register bit to the output, The multiplexer does not take into acer end. This Design Idea decount cases in which the shift
CLK OUT
scribes a data/clock-recovery
register contains no edges or
CLK
CLK/8
GATING
algorithm for an NRZ (nonmore than one edge.
return-to-zero), 1.5-Mbps daThe edge location is checked
ta stream in a Xilinx (www.
in the shift register using the
DATA OUT
xilinx.com) Spartan XC3S200
XOR-port array, which compares
7-TO-1 MULTIPLEXER/XOR
DECODER/COUNTER-BACKUP
FPGA. The algorithm emshift-register bit 0 with bit 1, bit 1
REGISTERS
ploys a modified data-recovery
with bit 2, and so on. Depending
application note (Reference
on the output of the XOR array,
CLK IN
1). The application note uses
showing where the edge occurs,
b0 b1 b2 b3 b4 b5 b6 b7
DATA IN
the DCM (digital-clock mana certain bit of the shift register
ager) on the Xilinx Spartan
multiplexes to the output. This
and Virtex models, but this
action ensures that the output
application uses a simplified
clock always toggles around the
algorithm that compares the
middle of the output-data bits.
data edges, if any, with interWhen there are slight differnally generated clock edges,
ences in clock speed and serialdynamically changing the
input-data speedfor example,
data-input-to-data-output dein the case of clock jitter or
lay. The simplified algorithm
clock tolerancesthe data-inallows integration in smaller
put phase continuously changes
CPLDs or FPGAs that lack a
with regard to the output-clock
DCM (Figure 1).
phase as the algorithm tries to
The algorithm uses a 3-bit,
track the input-data phase. In
free-running counter to generthis case, the multiplexer has an
ate the output clock, an 8-bit
overflow, which happens when
Figure 1 A clock-recovery circuit in an FPGA recovshift register to sample the seshift-register bit 7 multiplexes
ers data in a 1.5-Mbps data stream.
rial data, seven XOR ports for
to the output, the next bit is
edn081215di44161 DIANE
PLACED IN THE 2-5 FOLDER
designideas
shift-register bit 1, or vice versa.
If bit 7 is output firstthat is, the
signal edge_select is 0100 0000and
the next selected bit is bit 1, with an
edge_select of 0000 0001, a sudden
phase jump in output data occurs. This
phase jump is 2360837/8, or 23158.
Because the next input-data bit already
had shifted in completely in the shift
register, you need to employ a doubleoutput clock once, so that the register
5V
R3
100
R2
1k
1
D1
1N4148
14
VDD
Q
P2
50k
D2
1N4148
5
IC1C
74HC14
3
IC1B
74HC14
Q2
DURATION
Q1
DELAY
CW 100%
R1
470
LED
CW 100% 2N2222
P1
50k
C1
0.05 F
R3
6.8k
CLK IC2
CD4013
2
4
Q
R
MAIN CLOCK
GROUND
LED2
WHITE
BOOST
LED1
GREEN
IC1A
74HC14
LED
C2
0.02 F
2N2222
designideas
tion could have used
the trusty old 555 timer,
DELAY
the delay and duration
5
duty-cycle controls interact, which is an awk4
ward situation.
The circuit in Figure VOLTAGE 3
1 shows the main-clock
(V)
input; the delay and du2
ration potentiometers,
1
P1 and P2; and the HBLED output. The cir-0
cuit also includes an on0
1
2
3
4
1 mSEC/DIV
board general-purpose
LED for bench testing
Figure 2 With a main-clock input of 650 Hz, the delay is approximately 250 msec, with P1 at
to indicate an input sig10%, and the duration is approximately 600 msec, with P2 at 75%. The top trace (blue) reprenal, although, when the
sents the strobe delay, the lower trace (green) represents Q1s base duration, and the 5V trace
circuit is operating at
(red) represents the main clock.
high speeds, this LED is
useless. The main-clock
input is a 5V pulse of
approximately 30 msec
DELAY
coming from the fuel5
pump index. Delay potentiometer P1 adjusts
4
the on-time delay of the
LED from about 40 msec VOLTAGE 3
(V)
to 2 msec, and duration
potentiometer P2 adjusts
2
the LED-on, or flash,
1
time with a range of approximately 15 msec to
0
0
1
2
3
4
15 msec.
1 mSEC/DIV
The circuit applies
a 5V pulse, the main
Figure 3 An adjustment change of delay occurs with the same duration as in Figure 2. The top
clock, to diode D1 and
trace (blue) represents the strobe delay, the lower trace (green) represents Q1s base duration,
capacitor C1 to form a
and the 5V trace (red) represents the main clock.
peak-hold circuit. C 1
then discharges at a rate
that P1 sets. Schmitt trigger IC1A moni- output of IC2 to low. Because IC2 re- start of another in the chamber during
tors C1s voltage, and, when it reaches quires an active-high signal, you can the same flash period without encounthe low threshold of IC1A, it outputs a omit IC1B and IC1C, but you should use tering an error. The circuit also has a
high level to IC2s clock input, setting a Schmitt trigger following an RC cir- boost switch for a momentary intensity
the Q output high. With IC2s Q out- cuit for repeatability, especially on slow increase; otherwise, R3 normally limits
put high, the Darlington-transistor pair capacitor-charge/discharge times.
the current to approximately 40 mA.
comprising Q1 and Q2 turns on, drivFigure 2 shows the results of the cir- When you press the boost switch, the
ing the output to the HB LED low at cuit running with a main-clock input Darlington pair, two 2N2222 transisthe output, lighting the LED. At this of 650 Hz and a delay of approximately tors with current of approximately 400
time, capacitor C2 charges at a rate 250 msec, with P1 at 10%, and a dura- mA, still limits the current, but longthat P2 sets. When this voltage reaches tion of approximately 600 msec, with term use of the switch will shorten the
the upper threshold of IC1B, IC1Cs out- P2 at 75%. Figure 3 shows an adjusted LEDs life. You should tailor the values
put switches to high, resetting flip-flop change of delay with the same dura- of C1, C2, P1, and P2 to the application.
IC2s output back to low and turning off tion setting as in Figure 2. The new Calculations will vary depending on
the HB LED. The circuit is now ready flash period overlaps the following the logic family you use, but, generally,
for another round. Diode D2 ensures fluid burst. You could, depending on T50.73R3C, where T is the time in
a complete discharge of capacitor C2 the injector nozzle, see the end of one seconds, R is the resistance, and C is
for repeatability when you reset the Q fuel burst of calibration fluid and the the capacitance.EDN
designideas
Cancel sensor-wiring error
with bias-current modulation
W Stephen Woodward, Chapel Hill, NC
Diode temperature sensors are compact, stable, robust, sensitive, and inexpensive, and, unlike thermocouples,
they require no reference junction. All
of these benefits help explain the dura-
1.8
1.6
1.4
1.2
VOLTAGE 1
(V)
0.8
0.6
0.4
0.2
0
100
200
300
TEMPERATURE (K)
400
1M*
14
12
EDN090611DI4425FIG1
MIKE
13
1M*
IB1
15V
ONE SECTION
LTC1043
IB2
11
LTC1043
OSCILLATOR 16
RW2
A1
C2
1 F
7
0.01 F
10k*
CRYO-CON
S400BB
VOUT
TEMPERATURE
SENSOR
1 F
10k*
RW1
15V
*FILM RESISTOR
NOTES: CIRCLED NUMBERS ARE
LTC1043 PIN NUMBERS.
RW=RW2+RW1= TOTAL WIRING
RESISTANCE.
IB1= 2IB2.
A2
C1
1 F
Figure 2 This circuit cancels the wiring-resistance error inherent in diode temperature sensors and requires only two conductors in the sensor cable.
designideas
Hz by connecting the external 0.01mF capacitor to Pin 16. The resulting
toggling of the excitation ballast resistance between 1M and 1M11M52M
creates the 2-to-1 current modulation
and an ac-signal component proportional to wiring resistance: IBRW.
The other side of the LTC1043 synchronously rectifies the IBRW ac component, storing the IB1RW5VC1 phase
on C1 and the IB2RW5VC2 phase on C2.
Op amp A2 buffers VC1 and inputs it
to the resistor network and A1, which
subtracts it from the average sensor sig-
1
6
but setting the outputs to low generates
OUT
GP0
GP3
C3
the negative half of the waveform.
2
2.2 nF
R3
VSS
VDD 5
R6
IC1
This scheme produces a sampled
49.9k
12k
PIC10F200T
1%
sine
waveform with 12 samples per
3
4
GP1
GP2
cycle. In addition to the desired freC2
R2
3.9 nF
quency component, f0, this waveform
57.6k
1%
contains higher-frequency components
at (12k11)f0 and (12k21)f0, k51,2,3,
R1
100k
and so forth. The lowpass filter com1%
prising IC2B, R7, R8,
C3, and C4 easily filters out these undeFigure 1 This microcontroller-based cirsired components of
cuit generates Bell 202-compatible FSK
smaller amplitude.
modulation.
Listing 1, which is
available with the
FSK (frequency-shift keying) is
Web version of this
a type of signal modulation for
Design Idea at www.
transmitting digital data over an analog
edn.com/090611dia,
communication link. An FSK moduis the assembly-prolator comprises a digitally controlled
gram code that imsine-wave generator whose frequency
plements the Bell 202
Figure
2
The
FSK
modulators
output
changes
freedn090514di44451 DIANE
shifts between two
predetermined
freFSK standard. When
(PLACED
IN THE 5-28 FOLDER)
quency based on a digital input.
quencies in response to the two logic
the control input
levels of the digital data. The circuit outputs GP0, GP1, and GP2 of micro- Data In is high, the output frequency is
in Figure 1 generates a sine wave by controller IC1 produce nonoverlapping 1200 Hz; when the control is low, the
continuously sampling a single sine pulse trains. When you set either out- output frequency is 2200 Hz. The trancycle. The output of IC2A is propor- put high or low, the others are off sition from one frequency to the other
tional to the currents through R1, R2, that is, at high impedance. When you occurs in a manner that retains phase
and R3. These resistors connect togeth- set an output high, the voltage across continuity. Figure 2 shows the FSKer at one end to the inverting input of the resistor that connects to it is VCC/2. modulator output (CH1) in response
IC2A, which is biased at VCC/2. The When you set the output low, the volt- to a modulating signal (CH2).EDN
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
cycle
output current
refrigerator door
Figure 1 With just one LabView virtual instrument, you can control start and stop frequencies, sample rate, and the overall
duration of the sweep.
designideas
est frequency. When setting the sample
rate, you need to take into account the
overall frequency span you are sweeping and the duration of the sweep itself.
It is also helpful to compare the results
and performance of the LabView dataacquisition-system implementation of
the swept sine wave with those of an
AWG (arbitrary-waveform generator).
You use two methods of comparison.
First, you compare the output of both
the data-acquisition and the AWG
swept sine wave on a spectrum analyzer. Second, you run them both through
an audio-amplifier/speaker system and
simply listen to the output. This method is useful in determining sweep rate,
duration, and stop and start frequencies. This type of comparison is valid
only if the frequencies involved are
in the audible range. The LabView VI
employs simple array manipulation and
uses a for loop. The input duration
is in seconds, the sample frequency is
in samples per second, and the starting and ending frequencies are in hertz.
Dividing the sample rate immediately
converts the start and end frequencies
to cycles per sample. A maximum/minimum block takes the normalized ending and starting frequencies as its inputs
and uses the maximum output of the
input pair. You use this method to determine whether your design meets the
designideas
pares the standard multiplexing method with Charlieplexing (Reference 3).
Using Charlieplexing, the maximum
duty cycle for a 20-LED display is only
5%. The poor duty-cycle figure is due
not to the method, however, but rather to the driving capability of the microprocessor and the parasitic-leakage
paths. A single pin cannot usually sink
the current a number of LEDs require
to effectively light up, so these designs
often require one source pin and one
sink pin to light only one LED at any
time. However, adding a transistor or
two resistors allows you to circumvent
these issues.
If you rearrange the LEDs in the familiar cross-point array and add a transistor to each column to carry the common current, youll see the duty cycle
of the Charlieplexing method does not
differ much from standard multiplexing
(Figure 1). For a 20-LED, five-column
matrix, each LED remains on for 20% of
the time compared with 25% for standard multiplexing, but now using only
5V
5V
5V
5V
470
Q5 BC337
470
Q4 BC337
470
Q3 BC337
470
Q2 BC337
470
Q1 BC337
D12
P1
P2
P3
P4
P5
D13
D14
D15
D23
D24
D25
D34
D35
100
D21
100
D31
D32
D41
D42
D43
D51
D52
D53
100
D45
100
D54
100
DIANE
designideas
Serial port tests digital circuits
A PCs serial port provides signal lines that you can use to
read voltage levels of digital circuits.
You can use the port to test digital
TTL (transistor-to-transistor-logic)level circuits. You just need to convert
the TTL levels to RS-232 voltages, and
you can add a multiplexer to increase
the number of signals that the serial
port can sense.
The circuit in Figure 1 uses a
MAX232 IC from Maxim (www.
maxim-ic.com) to convert RS-232
voltage levels to TTL levels (Reference
1). A 74HC4051 from Texas Instruments (www.ti.com) lets you select any
of four digital inputs and route them to
the serial port (Reference 2). Listing
1, which is available with the online
version of this Design Idea at www.edn.
com/090625dia, lets you control the
RTS (ready-to-send) and DTR (dataterminal-ready) pins in the serial port
that selects the signal under test. The
CTS (clear-to-send) pin then reads the
signal under test into the PC.
The four digital-input signals, A0
through A3, from your device under
test connect to the first four inputs, X0
through X3, of the multiplexer. Only
one of those signals can pass through to
the X output, Pin 3, at a time. By setting the appropriate binary code on the
serial ports RTS and DTR lines, you
can select the signal to pass through
the multiplexer (Table 1).
The PC software, running on Windows XP, sequentially sets those binary
combinations on the ports RTS and
DTR lines and reads the digital signal
on the CTS line. The software then
reads the status of the selected bit and
displays it when you press the checkstatus button (Figure 2). The code is
written in Microsoft C# 2008, but it
RTS bit
DTR bit
A0
A1
A2
A3
R e fe r e nce s
MAX220-MAX249 15V-Powered,
Multichannel RS-232 Drivers/Receivers, Maxim, January 2006, http://
datasheets.maxim-ic.com/en/ds/
MAX220-MAX249.pdf.
2 CD54/74HC4051, CD54/
74HCT4051, CD54/74HC4052,
CD74HCT4052, CD54/74HC4053,
CD74HCT4053 High-Speed CMOS
Logic Analog Multiplexers/Demultiplexers, Texas Instruments, 2004,
http://focus.ti.com/lit/ds/symlink/
cd74hct4053.pdf.
1
DIGITAL INPUTS
5V
16
16
1
C1
1 F
PC COM PORT
DB9
1
2
3
4
5
6
7
8
9
C2
1 F
RTS
CTS
DTR
C3
1 F
C4
1 F
MAX232
5
12
13
14
8
5V
A3 A2 A1 A0
11
9
15
13
14
15
12
1
5
2
4
X0
X1
X2
X3
X4
X5
3
X
X6
X7
74HC4051
11
S0
10 S1
9 S2
6
E
7
VEE
8
Figure 1 This circuit lets you pass up to four TTL-level signals to an RS-232
port to read their status.
edn090305di44201 DIANE
(PLACED IN THE 4-23 FOLDER)
Figure 2 A main window of the running application shows that input lines A0
A2 have high logic levels and A3 has a low logic level.
designideas
DAC calibrates
4- to 20-mA output current
Ronald Moradkhan and Steven Lau,
Maxim Integrated Products, Sunnyvale, CA
CSA
10V
R3
15
10V
C4
0.1 F
R4
15
C3
0.1 F
RS
RS
VCC
IC3
MAX4376T OUT
Q1
IRFL4105
R5
2k
0.1 F
GND
5V
IC1
IN
OUT
C1
0.1 F
VREF
3V
INPUT
R1
10.2k
GND
INPUT
IC4
MAX420
OUTPUT
V
VCONTROL
R2
255k
C2
0.1 F
SPI CONTROL
VDD REF FB
IC2
MAX5304
LOAD
CCXTD
0.1 F
CCXTD
0.1 F
OUT
GND
ilar one I recently read about (Reference 1). A few years ago, I built the
designideas
tance is greater than 30 kV. Usually,
the dark resistance is greater than 200
kV, and current consumption at this
state is less than 40 mA. Oscillatorcounter IC1 starts counting when PC1s
16
9
V1
9V
R1
20k
C1
10 nF
R2
270k
10
11
12
VDD
OUT2
OUT1
Q13
IC1
4060
CLK
Q5
RES
D1
1N914
VSS
PC1
Figure 1 This gadget, placed inside a refrigerator, sounds an alarm when the refrigerator
door is open for more than 20 seconds.
edn090611di45191 DIANE
(PLACED IN THE 6-25 FOLDER)
R e fe r e nce
1 Babu, TA, Alarm
Sounds When Refrigerator
Door Remains Open Too
Long, Electronic Design,
March 26, 2009, pg 46,
http://electronicdesign.
com/Articles/ArticleID/
20806/20806.html.
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
Based on a seven-LED set, you select three consecutive LEDs; the second-tier settings will define the three
LEDs intensities (Figure 1). The remaining displays are maintained at a
base-tier-intensity setting. Using four
pushbutton switches, the Microchip
(www.microchip.com) 16F505 rotates,
distributes, and provides PWM (pulsewidth-modulation) control of these
two power tiers across the seven LEDs.
Two of the buttons increase or decrease
intensity, or they group or ungroup the
tier-intensity settings; the other two
buttons rotate the resulting second-tier
display clockwise or counterclockwise.
The implementation uses just a few
parts, exploiting the controller to pro-
amplifier
testing
5V
1
10k
10k
200
10
200
9
D
11
PIC16F505
200
200
6
5
13
12
200
200
14
200
GREEN
LED
WHITE LEDs
LTW-2S3D7
470
MODE
OPTICALILLUMINATION
RING
mode. When you group the tiers together, their intensity-setting indexing is common, but their register limits
remain independent. You can download Listing 1, the assembly code for
the circuit, from the online version
of this Design Idea at www.edn.com/
090709dia.
The controller provides a PWM period of approximately 7.5 msec to all
the LEDs. It also controls each LEDs
duty cycle, according to the registered
No function
No function
No function
nominal in this circuit. These numbers are respectable, but you can improve them. First, incorporate a digitally controlled variable resistor, such
Jason Andrews, Maxim Integrated Products Inc, Dallas, TX
as a DS1859, into the regulator circuit
A variable resistor that inte- ther a preset 3.3V or any user-defined of Figure 1 by placing it in parallel
grates a programmable, tem- output within its operating range.
with R2 (Figure 2). A temperatureperature-indexed look-up table can
For most regulator circuits, the out- indexed look-up table in an internal
compensate for the temperature drift put voltage varies slightly with tem- nonvolatile memory controls the 50of a voltage regulator. In this case, the perature, from 97.6 to 101.5% of kV digital resistor, allowing you to
look-up table can change
program a different rethe resistance every 28C
sistance value for each
VCC
over a range of 240 to
28C window.
11028C, thereby nullYou can program the
ing any regulator-output
look-up table to prochanges that would othvide any resistance-verLOAD
OUT
IN
erwise occur because of
sus-temperature profile.
C2
temperature. A typical 10 F
In this example, the
GND
GND
R1
MAX604
regulator circuit comprislook-up table flattens
C
GND
GND
es a regulating element, a
the regulators normal
3
10 F
feedback-resistor divider,
curve over temperaSET
OFF
and capacitors to provide
ture. These look-up tafiltering and regulation
bles, therefore, provide
R2
against transients and
a positive resistance
LOAD
load-switching conditions
slope with respect to
(Figure 1). The ratio of
temperature. The resisthe two feedback-divider
tor has 256 programmaresistors sets the regulable resistance settings
Figure 1 A typical voltage regulator lets you set the regulated
tor-output voltage. The
of 0 to 255 decimal,
output level by adjusting the R1/R2 divider.
regulator can generate eiand each one accounts
designideas
VCC
VCC
4.7k
4.7k
DS1859
SDA
VCC
SCL
H1
OUT1
L1
IN1
H0
OUT2
L0
IN2
MON3
WPEN
MON2
GND
MON1
C1
0.1 F
C2
10 F
GND
LOAD
OUT
IN
MAX604
GND
GND
GND
OFF
SET
R1
C
3
10 F
R2
LOAD
Figure 2 Connecting one-half of a dual variable resistor in parallel with R2 to the circuit in Figure 1 lets you temperaturecompensate the regulated output voltage.
for approximately 192V. In this example, the look-up table was programmed with a setting of 143 decimal at 2408C. The settings were incremented by one for every 4 to 68C
change in temperature, resulting in a
value of 152 decimal for ambient and
158 decimal for 1858C.
As illustrated in Figure 3, the result of this regulated performance over
temperature is a drastic increase in
precision: The variation from 245 to
1858C is now only 62 mV. For comparison, note the response of the standard regulator circuit in Figure 1 (the
black curve). The digital-resistor IC
of Figure 2 includes three ADC inputs for monitoring external voltages.
An alternative, the DS1847 dual variable resistor, offers similar performance
without the ADC monitors and at
lower cost.EDN
3.4
3.38
UNCOMPENSATED
3.36
3.34
OUTPUT
3.32
VOLTAGE edn090514di44702 DIANE
(V)
(PLACED
IN THE 5-28 FOLDER)
3.3
3.28
3.26
3.24
45 35 25 15 5
15
25
35
45
55
65
75
85
Figure 3 These curves compare regulated outputs versus temperature for the
Figure 1 circuit (black) and the compensated Figure 2 circuit (pink).
TEMPERATURE (C)
necting system power when a temperature exceeds a safe limit. The circuit
in Figure 1 uses a hot-swap switch to
monitor overvoltage, undervoltage,
and overcurrent conditions. When the
ambient temperature exceeds a preset
threshold, a carefully placed temperature sensor, IC1, forces the hot-swap
controller, IC2, to disconnect system
power. You can use multiple tempera-
designideas
Q1
SI7850
5V DC
IN FROM
AC/DC
ADAPTER
CIN
10 F
4
C1
0.1 F
1
2
IC1
LM26
HYST
OS
R1
10k
1%
5
3
VTEMP 3
GND
R2
2.15k
1%
CN
0.1 F
1
2
V
HYST
ICN
LM26
OS
VIN
1
SENSE
CL
100 F
VPGOOD
10
GATE
9
OUT
UVLO
PGD
R3
2.87k
1%
4
RSENSE
0.01
1%
C2
0.1 F
OVLO
PROTECTED
5V
OUT TO
SYSTEM
IC2
LM25069
TO C POWERGOOD INPUT
PWR 7
RPWR
31.6k
1%
GND
VTEMP 3
RPG
100k
1%
6
TIMER
CT
0.47 F
GND
Figure 1 Carefully placed low-cost temperature sensors disconnect system power when an overtemperature thermal event
occurs.
outputs on each channel. If the amplifier drives separate speakers, you can
use an attenuator circuit (Figure 1). A
problem arises, however, with grounded headphones: Stereo headphones use
three-pole plugs with which the negative side of each speaker connects to a
common ground. Thus, you may think
that you cant directly connect head-
designideas
RIGHT
R3
R4
R1
R6
RIGHT
SPEAKER
R2
LEFT
R4
R5
RIGHT
HEADPHONES
LEFT
SPEAKER
R2
R3
LEFT
LEFT
R5
R1
R6
RIGHT
edn090611di45061 DIANE
(PLACED IN THE 6-11 FOLDER)
OUTL
OUTL
OUTR
OUTR
0.47 F
edn090611di45062 DIANE
0.47 F
(PLACED IN THE 6-11 FOLDER)
phones to a Class D amplifier without nels drivers. Resistors R3 and R2 conusing a transformer.
nect to the left output terminal. ReTo solve the problem, look at the sistors R4 and R1 connect to the right
output waveform of the MAX9704 output terminal. The inactive chanas it swings (Figure 2). Each channel
nels output
edn090611di45063
DIANE voltage must be the same
(PLACED
6-1 FOLDER)
output alternates between high
andIN THE
voltage,
which means that R4, R1, and
low. You can take advantage of the R6 connect to the same voltage when
fact that the channels arent on at the the left-channel output is active. R3,
same time by configuring your circuit R1, and R5 connect to the same voltlike the one in Figure 3.
age when the right-channel output is
Figure 4 shows the circuit details. active. The values of R1 and R2 affect
Because the MAX9704 alternates the how much crosstalk you get between
outputs of each channel, the R3/R6 channels. The values in Figure 4 procombination doesnt affect the chan- vide sufficient channel separation.EDN
10
9
16
INL OUTL
INL OUTL 31
INR OUTL
15
INR OUTL
IC1
0.47 F
MAX9704
0.47 F
OUTR
AGND
J1
32
OUTR
OUTR
OUTR
LEFT
SPEAKER
30
29
J2
28
27
RIGHT
SPEAKER
26
25
R1
100
R2 R3
100 470
R4 R5
470 470
R6
470
J3
T
R
S
Figure 4 With the resistors in place, you can connect headphones to the MAX9704 amplifier.
HEADPHONES
designideas
Circuit eases power-sequence testing
C3 is 33 mF and R3 is 11 kV for a
400-msec delay between powering the
two supplies. The timer triggers with a
negative pulse at Pin 2 of IC1. It produces a positive pulse at Pin 3 of IC1.
The output becomes inverted at IC2A
before passing to IC6s Pin 11. IC5 and
IC6 are the latched circuits. The set
pin, S, connects to the 5V supply, and
the reset pin, R, connects through resistors R2 and R10 and capacitors C4 and
C7 to ensure that the Q output is high
during the initial power-up stage. Regulators IC3 and IC4 are initially off.
When analog switch S2 is in the on
position, the sequence of the 1.5V
power supply starts first, and the 3.3V
supply follows. To start the power-sequence testing, press and release trigger switch S1 to momentarily produce
IC2B
74LSU4N
VIN
5V
1
R1
10k
IC2A
74LS04
2 TR
4
2
S1
DT6
4
C2
0.01 F
C1
0.01 F
Q 3
7
IC1
DIS
LM555N
5
6
CV
THR
R2
40k
2
1 GND
V+ 8
R3
10k
R10
10k
C4
0.01 F
3
2
11
C3
33 F
C IC
6
D 7474N 8
13
R
12
C7
0.01 F
C IC
5
D 7474N 6
1
R
10
VIN
13
12
11
16
14
15
S2
MABSA
VOUT1
1.5V
R4
10k
5
1
IC3
1
3
4
EN TPS75501 V
OUT
2
GND 3
1.5V
R5
C5
30k
47 F
VIN
5
1
IC4
4
EN TPS75501
V
GND 3 3.3V OUT
C6
47 F
R6
50k
2
R7
30k
D1
RED
R8
1k
VOUT2
3.3V
3
D2
GREEN
R9
Figure 1 A configurable sequencing circuit uses a 555 timer to delay one power supply.
edn090514di44861 DIANE
(PLACED IN THE 6-11 FOLDER)
designideas
a low pulse. This pulse triggers the
555 timer, IC1, which produces a positive pulse. This pulse in turn produces a delay before enabling IC4s power
3.3V supply. When you press and release S1, another signal goes to inverter IC2B before passing to the latch pin,
Pin 3 of IC5. There is no delay for the
1.5V regulator that connects to this
pin. It enables IC3s 1.5V power sup-
ply. Because IC3s enable pin immediately receives the enable signal, it
produces the 1.5V without delay. IC4s
enable pin, which receives a signal after the delay by the 555 timer, later
produces the 3.3V, thus achieving
the power sequence. The 1.5V power
supply comes first when you press S1,
and the 3.3V power supply comes on
only after the 555
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
automatic-reset function
The classical flyback capacitor charger operates in CCM (continuous-conduction mode). Flat-topped, short-duration current pulses on the transformers secondary charge the storage capacitors (Reference 3). Unfortunately,
this charging strategy requires complex
control circuitry to limit both the secondary current and the capacitor voltage. Most circuits use a specialized
PWM (pulse-width-modulation)-controller IC, which increases the overall
cost of the charger. Another disadvantage of the CCM is the small portion
of energy that accumulates during the
on-time of MOSFET conduction:
only threeforcomponents
Equations
DI4484 (in 5 23 folder )
ETo see all of EDN's Design
Ideas, visit www.edn.com/
designideas.
Equation
1
W =
1
(L P I2P L P I2P
),
PK
OFFSET
2
where IP2
signifies the initial nonzero primary current at the beginning
OFFSET
Equation 2
OPTIONAL RESISTORCAPACITOR-DIODE
SNUBBER
380V DC
R1
C3
D1
STTH512
1
W =
T1
D3
L P I2P .
PK
C1
2000 F
15V
C8
22 F
450V
R3
56k
R4
13k
R5
51k
2
3
R7
51k
C6
330 nF
INV
IC1
L6565
COMP
VCC 8
GD
VFF
GND
4 CS
ZCD
7
6
Q1
STP4N150N
C7
470 pF
D4
STTH512
R6
10
R9
10k
C4
2000 F
R8
1k
R10
0.5
1W
400V
C2
2000 F
C5
2000 F
400V
of the on-time
interval.
Equations
for DI4484 (in 5 23 folder )
Only this limited portion of energy transfers from the primary to the
secondary sides and enters the storEquation
1
age capacitor.
Therefore,
you can
considerably increase the amount of
energy transferable to the capacitive
1
2
load if the
converter
W
= (L Pcan
I2Poperate
L P Iin
),
POFFSET
PK mode).
2
BCM (boundary-conduction
The secondary current becomes zero,
the power MOSFET turns on, and
the primary current builds from zero.
Thus, a bigger
portion
of energy acEquation
2
cumulates during every consecutive
on-time interval:
W =
1
L P I2P .
PK
2
Figure 2 When the secondary current reaches 0A, the MOSFET turns on, and
the primary current increases from 0A.
Figure 3 The output-capacitor voltage reaches its full level in about 3 seconds.
designideas
initial starting timer sets the switching frequency to 2.5 kHz at the start
of charging. The output voltage across
the storage capacitors increases to a
point at which the switching frequency becomes variable because of the demagnetization of the transformer core.
Figure 2 shows that, as soon as the secondary current (Channel 2) becomes
0A, the power MOSFET turns on, and
the drain-to-source voltage decreases
(Channel 1). At that time, the primary current again increases (Channel
4). At the output voltage close to full
charge, the switching frequency is approximately 100 kHz. Figure 3 shows
the total voltage of 750V across C1, C2,
C4, and C5 within a 3-second charging
time.
The waveforms in figures 2 and
VPS
9V
R1
1.5k
IC1
3
D2
R3
300k
6
R4
1.5k
C1
100 F
RESET
S1
S2
PLAYER 1
S3
LED1
PLAYER 2
SN+1
LED2
LEDN
PLAYER N
D1
3.9V
R2
5k
Figure 1 This circuit lets you indicate which game player presses a button first.
GREEN
LED
14
4
C
2
6.8 F
7 IC1
CD4093B
VPS
9.7V
VA
9.2V
VPS
9.7V
6.2V
VC1
VA
3.7V
0
T1
PLAYER N
PRESSED
T2
RESET
PRESSED
TIME
T1
PLAYER N
PRESSED
T2
AUTO
RESET
TIME
You can also add an auto-reset feature ure 3), C1 has enough voltage to force rent in any optoisolator LED. As a reedn090611di44522
DIANEIC s Pin 4 low. R and C determine
edn090611di44523
DIANE
to the circuit. When
Point A drops to
sult, the circuit
automatically resets,
3
1
(PLACED IN THE 6-25 FOLDER) 1
(PLACED IN THE 6-25 FOLDER)
3.7V (time T1 in Figure 3), the inputs the charging time. A pulse of current and the green LED lights. IC1s Pin 3
at IC1, pins 1 and 2, go low, and the flows through C2, which forces the goes low, which discharges C2 through
output at Pin 3 goes high, charging C1. voltage at Point A to nearly 2V. That R2, resetting the circuit to its original
After about 30 seconds (time T2 in Fig- action momentarily interrupts the cur- state.EDN
The circuit in Figure 1 provides an isolated control voltage, such as 0 to 10V. In the low part
of the range, 0V to approximately 2V,
the controlled device is off. Therefore, the upper part of the range must
be as linear as possible. You can meet
this requirement using a linear optocoupler, such as Vishays (www.vishay.
com) IL300 or Avago Technologies
(www.avagotech.com) HCNR200 or
HCNR201.
These optocouplers each comprise
an LED and a photodiode on the transmitting side and an identical photodiode on the receiving side. Because of
this construction, the emitted light
from the LED should cause the same
current to flow in both photodiodes.
The current through the photodiode
on the receiving side, feedforward cur-
VC
R2
220
IR1
R1
150k
V1
A
IFB
C1
10 nF
3
IC1
IL300 4
IFF
IC1
IL300
Q2
IB1
1
VBE1
BC857
K2
Q1
BC847 2
K1
1
ILED
IC1
IL300
R4
18k
6
5
VBE3
IB3
Q3
R3
150k
BC857
V2
Figure 1 Optocoupler IC1 isolates the control circuits input and output.
edn090611di44711 DIANE
(PLACED IN THE 6-25 FOLDER)
1 K2
I
=FF
(V1.V2BE1)
; K 212 >> 1.
1 K2
K 2I FF
=Equation
I FB I
I FF = (V1VBE1)
; K 212 >> 1
R1 K1
K1 =
, LED
R
Equation 7
1 K1
I FF
I LED
Equation
1
K
K2 =
.
K3 = 2 .
I LED
K1
I FF
K2 = 3 7 .
Equation
Equation
I LED
Equation 7
I FB 2
K
KEquation
,
K3 = 2 .
1=
I
K1
LED
Equation 3
Equation 8
V1VBEK1 2
KEquation
= =. I 3 + I .
K
I R3 K1 FB B1
K3 = 2 .
Equation
2 1.
K 2 = FF
K1
Equation 8
V1VBE1
I
V2 = (I FF + I B 3) R 3 + VBE 3 .
= I FB + I B1.LED
R1
V1VBE1
I FF Equation
8 = I FB + I B1.
K 2 = Equa
. tion
R4
V2 = (I FF + I B 3) R 3 +Equation
VBE 3 . 8
I LED 3 1
Equation
Equation
9
Equation 4
V2 == (I1FF
I LED
2 +
I B13.) R 3 + VBE 3 .
Equation
4
V2 = (I FF + I B 3) R 3 + VBE 3 .
Equation
Equation 9
V1VBE31
1
= I FB + I B1.
I FF = (V1VBE1) I B1 K 3 .
I LED = 12 I B1. R1
R
1
Equation
59 I .
V1VBEEquation
Equation
9
1 =IILED+ =
1 2
B1
I
.
1
FB
B1
I = (V1VBE1) I B1 K 3 .
R1
Figure 3 AnFF
XY plot of the circuits
R1 inputand output
Equation 5
Equation 4
Equation
10 is high
Figure 2 The output voltage (upper trace) turns off when
voltages
shows
linearity
once
the
input voltage
1 1 K 212
Equations
for
DI
4471
(
Saved
int
o
the
June
25
folder
)
Equation
5
I
=
(
V
V
)
Equation 10
= 1K
I B12. )
Equations
4471
(Saved
theI June
folder
sidesforofDI
the
signal
path. int
The circuit
When
the product
feedback
gain K1
(V25
VBE1))
2 2 1of
.
FF =in
1
R3
R3
R
K
+
1
V
=
V
K
+
V
V
K3 + R
1
1
1
2
Equation
1
this DesignEquations
Idea uses power
gains
b and
2
1
3 BE 3
BE1
K 212
1
for DIfrom
4471 signal
(Saved and
int oItransistor
the =June
25IB=1folder
) V b2)is much
12I
. (V1
R
R
LED
.
1
1
FF you
1
Equation
6 110
voltage VEquation
to supply1 a feedback loop in greater than
one,
canBE
cancel
Equation
R1outK112 + 1
1
EquationR10
Equation
1
Equation 5gains, yielding a char
R3
Equation
the1transmitting
side similar
to the way the transistors
V2 = V1
K 3 + VBE 3VBE1 3 K 3 + R 3(I B 3I B1K 3).
Equation
6 Equation
some circuits in aIF4-B to 20-mA loop
get acteristic
that5 is linear:
R1
R1
(10)
Equation
1
K
= loop
,forcurrent.
Equation 11
1 the
Equations
DI4471 Both
(Saved int o the June 25 folder)
power from
K
1
2
I
.
R
R
Equation
6
I FLED
I
=
(
V
V
)
;
K
>>
1
3
3
BI FB
FFV = V
1
BE1
R
K1 + KV
V 2 1 2 K 3 + R 3(I B 3I BR1K
).
K1K=operate
, in reverse-biased,
2
I photodiodes
B ,
12 .BE1 R
V2 = V1 3 3K 3 + VBE 3VBE1 3 K 3 +
I FF = (V1
VBE11)R1 3 R1 2BE1K3(6)
1 I=LED ,
K1 = Fphotoconductive
1
mode.
The
currents
I
K
1
R1
R1
1121
R1 K 2K
LED
2 ; )K 1
I LED
Equation
2. + 1
11
= (V1VBEI1FF) = (V1
VBE
I B
1 2 1 2 >> 1.
V1.
through them
toIFFinciIn the first V
term
10, the
2 Kin
3 Equation
Equation
1,
R1 K112 + 1
K1 =are Fproportional
R1 K1
Equation
2
1 K 2 ratio of resistors R and R is approxiI LED feedback gain K1
dent-light flux, which
I FF = (7V1VBE1)
; K 212 >> 1.
3
1
Equation
R
Equation
11
Equation
2
and forwardEquation
gain K2 describe.
TheEquation
ratio of 6feedback gain K1 1andK1 mately 1-to-1.Equation
You must11
be careful with
2
V2 K 3 V1.
Equation 2
forward
gain K is transfer gain K3. Be- the transfer gain, K3, which is the reaEquation
7 Equation 6 2
FB ,
IIFF
(1) cause
K
=
K
and K2 are similar, K3 is ap- son that K3 remains in Equation 11.
1
Equation
2
K2 = I
.
1
K 2 reality, K may deLED
proximately
V=Equation
K.3 V71. 3
LED
IIFF
K 3one.
2 In
I FF.
1K K 2
V2 K 3 V1.
(11)
K
=
Iwhere
K1 )less
2
K
=
.
FF
LEDs current, and
viate,IFF
but=it(Vchanges
or2K122 >> 1.
1 than
V
2; KK
2 I LED
1; K
K2 =
. ILED is the
1
BE
I FF = (V1VBE1) 1
>>
1
.
I
2
1
2
K
R1K K1
LED
2
I LED
alone:
When
K
is
one,
voltages
V
and
R
K3 =
.
1
1
3
BE1
I
Equation
K 2 = FF 32.
(2)K1
V
cancel
each
other
to
some
degree.
Equation
K
BE3
I LED
K 3 = 82 .
(7) Therefore, Equation 11 omits the secEquation
K1
Equation
3
Equation
3
Equation
Equation7 7
of the circuit
begins with
ond term in Equation 10. Base curEquation A3 description
I
a sum of theVdc
currents
at
Node
A.
Equation
6 subtracts the base-to-emit- rent IB3 depends on resistor R4 and the
Equation
8
FF
V
K12 = BE1 =
Equation
3. I FB + I B1.
ter voltageVfrom
input voltage. Al- output load. When you can set both
(Ithe
2 =Equation
FF + I B 38) R 3 + VBE 3 .
R1I LED
V1
V
K 2Kbase-to-emitter
BE
1
though
the
voltage is base currents to be equal, the last term
V
V
(3)
=
I
+
I
.
1
BE1 =
K3 =
V1VBE1
FBI FB +
B1I B1.
K 3 =K1 .2 .it is desirable to remove would cancel out, too. The values of re= I FB + I BR
not
constant,
1.1R1
V
=
(
I
+
I
)
R
+
V
.
K
2
FF
B3
3 1 BE 3
R1
V1VBE1
it. You accomplish
this task using the sistor R2 and capacitor C1 must be small
Equation
3= I FB + I B1.
Equation
9 + I ) R + V .
Equa
t
ion
4
V2 in
= (Ithe
The gains of both
FF receiving
B3
3 cir- BE 3enough so that transistors Q1 and Q2
R1 transistors amplify emitter follower
Equation
8
current IEqua
into
the
base
of
Q
.
The
cuit.
The
output
voltage,
V
,
is
a
sum dont saturate. C1 enhances stability.
t
ion
4
B1 Equation 4
1Equation 9
Equation
8 R and the2 base-toEquation
4
amplified
current then flows through of voltage
across
Figure 2 shows the necessary voltage
3
V1V=BE
Q. 9
for the circuit to begin operation. The
1
112= I I B1+. I .
the LED. IEqua
emitter voltage
of
LED tion
Equation
3
FB
B1
4
I
=
(
V
V
)
K
1 3.
B1
3.
V2 = (I FFFF+ I B3) 1R 3 +BE
VBE
R1
output
voltage (upper trace) has flatR1
I LED
=
I
.
1 2
B1
(4)
V2 = (1I FF + I B3) R 3 + VBE 3 . (8) ness at its lowest voltages as opposed
I LED = 12 I B1. I LED = 12 I B1.
I FF = (V1VBE1) I B1 K 3 .
to the input voltage (lower trace).
R1
Equation
1
I LED = 152 I B1.
9
tion 4 4 yield the out- You Equation
Equations Equa
1 through
can use
aIFF
different
= 10
(V1equation
VBE1) to
I B1Figure
K 3 .3 shows the two signals linearEquation
Equation
5 5
R1
. I = (V V ) 1 I K .
test
circuit uses an IL300, which has
FF
1
I
FF
1
BE
1
B
1
3
LED
1 2
B1 R1 K112 + 1
of 0.851 to 0.955. The meaR 3 R110
12
1 1 K 2K
V =Equation
(9) Ra3gain
V
K
+
V
V
K
I FFI 1= (=V1(
V
)
.
2
1
2
1
2
1
3
BE
3
BE
1
3
BE
1
V
V
)
.
2
1
2
R11) I B1 K 3 . Rsurement
I FF = (V1VBE1) FF 1 BE1 .R1R K1K
12 + 1+ 1 I FF = (V1VBE
meets the requirements of
1
1
1
1
2
R1 K112 + 1 1
rearrange
R 3 R1 8 and
V
K
+
R
(
I
I
K
).
BE 310 BE1
IEquation
.3Equation
3
3 B 3 B1 3
FF = (V1
Equation
65VBE1) R 2K 1 Ras:
R1R
simplifications.
EDN
11
R
1
1 1 2+
3
V2 = V11
K 3 + VBE 3VBE1 3 K 3 + R 3(I B 3I B1K 3).
1
Equation
Equation
6
Equation 6
R1
R1
Equation 6
Equation 10
1 K K 212
R3
R3
1
= ((V
V1
VBE1)) Equation
2
11 . V2 =1.V1 K 3 + VBE 3VBE1 K 3 + R 3(IB 3IB1K 3).
FF =
IIEquation
FF
1 6VBE
1
R1
R1
R K1; 1K
22+112 >>
V
)
1
BE1 1)
2 1 2
1. R
R
I FF = (V1VBE1) FF (V21
; KV2BE
12R>>
.1K ; K 212 >>
1R11K
V2 = V1 3 K 3 + VBE 3VBE1 3 K 3 + R 3(I B 3I B1K 3).
1
R K
designideas
edn090625di44671 DIANE
(PLACED IN THE 6-25 FOLDER)
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
44 Set your lights to music
edn090611di45211 DIANE
(PLACED IN THE 6-25 FOLDER)
designideas
470 pF
5V
5V
180
475k
2.5V
2.49k
IR11-21C
IR LED
PD15-22C
470 pF
OUT
MAX4230
470 pF
OSCILLATOR
50k
1 F
100k
1M
2
IR TRANSMITTER
PEAK DETECTOR
5V
2.5V
IR
RECEIVER
AMPLIFIER AND
DEMODULATOR
Figure 2 An IR transceiver detects the presence of an object and provides an approximate distance from the transceiver.
designideas
C4
100 pF
VCC
Q7
R5
10k
IC4
74HC4060
RS
Q9
Q4
MR GND
C3
100 pF
OE
B PB1
MR
SH_CP
RTC
R4
22k
VCC
Q7
Q6
Q5
Q4
ST_CP
Q3
DS
Q2
IC5
74HC595 Q1
Q0
CTC
VCC
IC6
74C901
B PB2
C
GND
C2
100 pF
B PB3
VCC
IC2
74HC132
Q7
R3
10k
D2
1N4148
C5
220 pF
GND
R2
10k
VCC
Q7
Q6
MR
Q5
SH_CP
Q4
ST_CP
Q3
DS
Q2
IC5
74HC595 Q1
Q0
OE
5V
VL
VDD
1
2
C1
10 F
0
REF
3 RGND GND
B PB5
C
B PB6
E
EMI
FILTER
A
DOUT
AIN
AIN
GND
C6
10 F
IC1
MAX1276
10
9
SCLK CNVST
12
B PB4
GND
D1
1N4148
6
1
V
SD CC D1
ISOLATION
BARRIER
D3
T1
IN5817
IC7
MAX253
R1
10k
FS
D2
8
GND1 GND2
D4
2
7
1CT:1CT IN5817
A2
POWER BLOCK
R6
18.5
C7
0.1 F
C8
22 F
Q1
G
R7
7.8
A1
NOTE:
TRIAC IS MOUNTED
TO INSULATED HEAT SINK.
C
(a)
(b)
Figure 1 Driven by a 0 to 2.048V music signal at pins 12 and 1 of IC1, this circuit activates the six ac outlets according
to the music amplitude, in a logarithmic thermometer-code format (a). The power block (b) represents each of the power
blocks, PB1 through PB6.
designideas
register through the NAND gates in
IC2 and thereby inserts into the shift
register the value present at its input.
At the end of a conversion, the voltage
stored on C5 forces to one all the bits
following the first one that exhibits a
value of one.
At the completion of each conversion, a negative pulse applied to the
ST_CP inputs of both 74HC595 ICs
transfers these shift-register contents
to a parallel-output register, IC6. The
same pulse discharges the storage capacitor through diode D2, leaving the
circuit ready for the next conversion
scan. The parallel-register outputs then
serve as drivers for the 12-bit logarithmic column, with the MSB driving the
top outlet.
This circuit operates at lethal voltages and requires proper handling. Note
that the transformer must withstand a
line level of 120V ac. It operates with
incandescent light bulbs; you should
not use any other type of light bulb.
Even though the outlets are standard
120V-ac outputs for use with commercial incandescent lights, fast switching
in the TRIACs makes them unsuitable
for driving other types of loads, such
as appliances, electronics, or ac adapters. Transformer T1 is a TGM-350NA
from Halo Electronics Inc (www.halo
electronics.com), and TRIAC Q1 is
a T1235-T from STMicroelectronics (www.st.com). For a video of this
circuit in action, go to www.edn.com/
090806dia.EDN
rent-sense amplifier, IC1, to limit inrush current below the specified maximum, allowing the device to use more
capacitance when necessary.
The LTC6102 usually translates the
Daniel Morris, Group IV Technology, Renton, WA
voltage across a current-sense resistor
The USB (Universal Serial Bus) age drop at the device as inrush cur- to a larger ground-referenced voltage
specification requires a connect- rent charges its capacitance. Occasion- in an output resistor. The part features
ed USB device to present a load to the ally, a bus-powered device needs more an amplifier with low offset voltage,
host or hub of no greater than 10 mF than 10-mF bypass capacitance to pro- letting you use low-value sense resisin parallel with 44V, including the ef- vide an adequate reservoir for current tors. In the usual circuit configurafects of any bypass capacitance visible spikes. The circuit in this Design Idea tion, output current flows through an
through the devices voltage regula- repurposes a Linear Technology (www. onboard FET whose source connector. This limit avoids excessive volt- linear.com) LTC6102 precision cur- tion connects to a force pin separate
from the amplifier inUSB
R1
put pin to minimize erVBUS
0.02
rors across trace and pin
resistances.
Q1
R7
SI2323DS
This circuit grounds
R2
R3
10k
C2
402
402
the LTC6102s output
1 nF
1
8
pin and uses the onboard FET as a source
follower to drive the
7
5
C1
gate of an external
C3
200 F
LOAD
current-limiting FET
100 nF
6
(Figure 1). The feed3
2
R5
R4
back loop around the
249k
1M
LTC6102 maintains
Q2
equal voltages at the
HIGH-POWER
BSS123
positive and negative
ENABLE
IC1
4
LTC6102
inputs of the amplifier,
R6
pins 8 and 1 of IC1. Re10k
USB
sistor divider R2/R4 sets
GND
the positive input of
Figure 1 This circuit limits USB-device current both at connection and after configuration.
the amplifier, IC1s Pin
designideas
8, approximately 2 mV below the 5V
USB-voltage rail. With Q1 initially
off at device connection, the negative
amplifier input, IC1s Pin 1, is higher
than the positive input, causing the
amplifiers output to go low. As the
amplifiers output drops, the onboard
FET follows, pulling the gate of Q1 low
and turning it on. Current increases in
Q1 until the voltage drop across sense
resistor R1 matches the drop across
resistor R2.
Resistor R3 and capacitor C2 com-
pensate the feedback loop against oscillation and slow the turn-on of Q1,
preventing an initial current spike
when the device connects to the bus.
Capacitor C3 bypasses a regulator on
IC1. Resistor R7 meets the allowed
maximum 1-mA current through the
FET on IC1. Q1 turns on at a gate voltage low enough that it does not exceed
the input range of 4V positive voltage
to IC1s Pin 7 to Pin 2.
Instead of the large capacitive load
of C1, the circuit presents a resis-
0V
11
Experiments have confirmed
A2
10
100 nF
of 0V and for the precise referNC
A
ence dc voltage of 0.8188V. At
3
a frequency of 60 MHz, the dc
4
9
V
S
PD
component of the output voltage remains at about 4 mV for
VS
100 nF
7
8
5 6
an input voltage of 0V and rises
OUT
to approximately 175 mV for an
input voltage of 0.8188V. This
result is still remarkable because
1.2V
the ADG772 is a BBM (breakFigure 1 Video amplifiers and a switch pulse-modulate analog waveforms.
before-make) type of multiplex-
designideas
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
41 Handheld DMM copes
MT1
LOAD
R1
4.7k
LED1
bracket-pulse generator
44 Power-miserly voltage
LED2
MT1
edn090625di44951 DIANE
(PLACED IN THE 6-25 FOLDER)
LOAD
120V AC
120V AC
edn090625di44952 DIANE
(PLACED IN THE 6-25 FOLDER)
LOAD
MT2
R2
30k
R1
100
R3
4.7k
LED1
LED2
LOAD
C1
0.047 F
120V AC
120V AC
Figure 3 For an inductive load, add a neon lamp to minimize leakage current.
edn090625di44953 DIANE
(PLACED IN THE 6-25 FOLDER)
designideas
TRIAC UNDER TEST
LOAD
MT2
G
MT1
NEON
LAMP
606-A1C R3
4.7k
5V
OPTOCOUPLER
PS2501-2
R2
30k
R1
100
LOAD
MICROCONTROLLER
PA0
PA1
C1
0.047 F
R4
10k
120V AC
120V AC
R5
10k
MT2
G
MT1
NEON
LAMP
606-A1C R3
4.7k
5V
OPTOCOUPLER
PS2501-2
8
R2
30k
R1
100
edn090625di44954 DIANE
(PLACED IN THE 6-25 FOLDER)R6
100k
7
1 4
5
LOAD
C1
0.047 F
MICROCONTROLLER
ADC0
ADC1
R4
10k
120V AC
120V AC
R7
100k
R5
10k
C2
C3
2.2 F
2.2 F
it passes all four tests. You should perform another triac test during manufacturing to ensure that there is no
problem with the subassembly board
and that the triac works properly. This
test saves time and labor in case you
detect a problem after assembling the
entire product. You perform this test
with the triac soldered into place on
the board. You use the nominal power-supply voltage of 120/220V ac. The
test should have minimal influence on
the DUT and should use minimal time
and labor. This test uses the triac tester in place of a load. The connection
from the tester to the DUT can vary,
and be sure to take some safety measures when connecting 120/220V ac.
You use a different test fixture for
triacs that drive a resistive load, such
as an incandescent lamp or a heater
(Figure 2). Each LED checks conductivity in one direction. When the tri-
lel with the triac (Figure 3). Unfortunately, the snubber circuit introduces
a small current leakage into the test
circuit even when the triac is closed.
The circuit in Figure 3 shows you how
TABLEedn090625di44955
1 TEST FOR TRIACS
DIANE
(PLACED IN THE
6-25 FOLDER)
Step no.
Operations
LED status
Result
Off
OK
On
Off
Stays on
OK
Off
OK
On
Off
On
OK
and more complicated software. Interfacing the triac under test with the microcontroller creates no problem if the
triacs MT1 pin is grounded. In most
cases, MT1 and MT2 are isolated from
the ground. When this scenario occurs,
you can use an optocoupler, such as the
PS2501-2 from California Eastern Laboratories (www.cel.com, Figure 4). It
comprises two optically coupled isolators containing LEDs and NPN phototransistors with a maximum voltage
of 80V.
If the triac output comprises a sequence of pulses, such as a PWM
(pulse-width-modulated) signal for
motor-speed or lamp-brightness control, then use a lowpass RC filter before the microcontrollers ADC inputs
(Figure 5). The time constant of this
filter, t5R63C2, depends on the PWM
POWER-SUPPLY TERMINAL
C1
100 nF
LOGIC SIGNAL
R1
100
7
2
PRE
8
VDD
DMM
5
Q
IC1
SN74AUC1G74
FLIP-FLOP
1
3
CLK
Q
GND
CLR
6
4
D
GND
LOGIC CIRCUIT UNDER TEST
signal period and duty cycle. The measurement in the chain of tests should
start no earlier than 325t. Using the
microcontrollers ADC requires additional firmware. To avoid this requirement, you can compare the voltage after the filter with a reference voltage
with a comparator, such as the LM393
from National Semiconductor (www.
national.com), to produce a logic-high
level for the microcontrollers input.
Reference 1 describes an alternative
approach with minimal external components for the expense of the firmware complication.EDN
R e fe r e nce
Raynus, Abel, Microcontroller
detects pulses, EDN, July 24,
2008, pg 58, www.edn.com/article/
CA6578137.
1
1
=
= 5 MHz.
2TW 2 107
designideas
circuit. Therefore, you can run
the logic at any industry-standard supply voltage of 1.2, 1.5,
1.8, or 2.5V. In testing 3.3V
logic, use an external 2.5V
source to supply IC1. The internal protective diodes at Pin
1 of IC1, along with resistor
R1, reduce the voltage swing
at Pin 1 to an acceptable level
in such a case.
A square-wave signal is at
the output of the binary divider (Figure 2). The DMM
no longer sees nanosecond
pulses at its measuring termi-
nal. You have only to multiply the displayed frequency value by two to obtain
the correct frequency. Due
to relatively low values of
R1 and of the input capacitance, approximately 2.5
pF, at the clock input of the
flip-flop, you need not worry
about frequency compensation. The time constant of
R13CIN is merely 0.25 nsec.
The width of pulseseither
low or highat the input of
the circuit can decrease to
1 nsec.EDN
edn090723di44132 DIANE
(PLACED IN THE 8-6 FOLDER)
VCC VCC
RV
RT
13
12
VARIABLE
FREQUENCY
IC2F
CT CD4584
VCC
INPUT
10
OR
D1
1N4148
RV D
2
1N4148
R3
IC1B
10k
CD4052
12
X0
14
X1
13
X
15
X2
11
X3
R1
10k
VARIABLE
DUTY CYCLE
C1
100 pF
16
VCC
IC1A
CD4052
2 9
IC2A
CD4584
VCC
Y0
B
INH VEE VSS
6
RT
13
IC1C
CD4052
Y1
Y2
Y3
R4
10k
NONOVERLAPPING
10
IC2E
CD4584
IC2B
CD4584
1
5
2
4
R6
10k
R7
10k
IC2C
CD4584
OVERLAPPING
Figure 1 You can build a simple pulse generator with just two commonly available ICs.
11
12
IC2F
CT CD4584
IC2D
CD4584
edn090723di44091 DIANE
(PLACED IN THE 8-1 FOLDER)
designideas
which is independent of frequency or
duty cycle, using the time constant of
R1 and C1. Depending on output-device
characteristics and switching frequency,
output buffers may require an additional stage, or you can replace them with
MOSFET-gate-driver devices. Supply voltage is not critical but should
be high enough to guarantee that output devices fully turn on. In general, a
higher supply voltage allows for higherspeed operation. The MC14xxx series
of ICs is the same as the CD4xxx series.
If you need higher-frequency operation
Pin 10
(Input
A)
Sequence
Phase A
Dead time
Phase B
Dead time
designideas
Edited By Martin Rowe
and Fran Granville
CLOCK OUT
CLOCK OUT
CMOS
LATCH
C2
R
TH
TL
TH=R2C2 ln(VDD/VDDVTH).
TL=R1C1 ln(VDD/VDDVTH).
R2
D2
1N4148
(a)
D1
1N4148
R1
VDD
C1
S
VDD
C2
CLOCK OUT
CLOCK OUT
CMOS
LATCH
TH
TL
TH=R2C2 ln(VDD/VTH).
TL=R1C1 ln(VDD/VTH).
R2
(b)
D2
1N4148
48 High-performance adder
R1
D1
1N4148
C1
D Is Inside
TRIGGER IN
PULSE OUT
PULSE OUT
CMOS
LATCH
C1
R
TW
R1
TW
TW=R1C1 ln(VDD/VDDVTH).
D1
1N4148
(a)
TRIGGER IN
VDD
C1
PULSE OUT
Q
CMOS
LATCH
TW
PULSE OUT
Q
R1
TW
TW=R1C1 ln(VDD/VTH).
D1
1N4148
(b)
Figure 2 The leading edge of the trigger pulse depends on active-high (a) or
active-low (b) inputs.
edn090820di45372 DIANE
(PLACED IN 9-3 FOLDER)
LEDs find their way into applications that range from highend video displays to low-end lighting applications. Designers often need
only some of the functions of a dedicated LED driver but cant afford the cost
C1
1500 pF
8
4
VCC
IC1
555
10-kHz CLOCK
VCC
C4
0.1 F
RESET OUT
7 DISCH
6
THRES
2
5
TRIG CONT
1
GND
ON/OFF CONTROL
ON/OFF
C3
0.1 F
R3
178
IC2
TLC5917
16
3
4
13
2
14
15
1
VDD
CLK
LE(ED1)
(ED2)OE
SDI
SDO
R-EXT
GND
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
5
6
7
8
9
10
11
12
HIGH-POWER
LED
OUTPUTS CONNECT
IN PARALLEL
FOR 842-mA
LED CURRENT
Figure 1 A 555 timer provides the necessary pulses for configuring an LED driver.
designideas
of the microprocessor to control them.
Microprocessors typically control dedicated LED drivers, enabling features
such as analog or PWM (pulse-width
modulation) for LED-current control,
independent control of each LED, and
reading LED status and faults. If your
design requires a constant-current
LED, such as those in LED lighting
or luminaires, then you may not need
these advanced features. In these applications, a 555 timer can replace the
microprocessor and still allow accurate
control of LED current independently
of input voltage, temperature, and LED
forward-voltage drops.
IC 2, a TLC5917 dedicated LED
driver, controls eight independent
constant-current sinks (Figure 1). It
normally requires a microprocessor to
drive four digital-input signals. The
command OE (output enable) enables
and disables the IC. Data on the SDI
(serial-data-input) pin clocks into the
ICs input shift registers on the rising
edge of the clock. The data in the shift
registers transfers into internal on/off
latches on the falling edge of the LE
(latch).
Either the TLC5917 outputs can
drive eight independent LEDs, or you
can parallel its outputs to increase the
current to drive one higher-power
LED. Its internal current-setting registers have default values at startup. These values, along with external current-setting resistor R3, set the
LED current. In this application, R3
sets each outputs current to 105 mA:
18.75V/R3518.75A/178V. Connecting all outputs in parallel yields 842
mA of LED current.
Figure 2 The LED current (lower trace) ramps up and down in eight steps.
off until an operator manually reactivated the timer. The timer had to reside between the main 110/220V-ac
line and the load. And, as with any
other consumer product, it had to be
cost-effective. You can achieve these
designideas
D1
R1
4.7k 1N4003
C
C1
908QT2
D1
2
100 F
22 F
VT90N1 photoresistor
1N4733
IC1
16V
PA0 7
2
from PerkinElmer (www.
ADC3
LED
optoelectronics.perkin
4
RST
elmer.com) has a dark reRESET
8
sistance of 200 kV, which
drops in light to 10 kV or
Figure 1 This circuit uses an eight-pin microcontroller and a logic switch to provide a smart
less. The LED indicates the
photoresistor.
status of the timer: It is on
when the timer is ready for
work and waits for darkness. It blinks
during the delay, and it is off when
POWER
DARK
RESET
the timer waits for reactivation (FigON
LOAD IS ON
ure 2). The W934GD5V LED from
TIME
LOAD
Kingbright (www.kingbright.com) has
a built-in resistor that minimizes the
ON
ON
number of necessary components. To
TIME
LED
reactivate the timer, press the pushbutedn090723di45201 DIANE
(PLACED IN THE 8-6 FOLDER)
ton reset switch. All time delays are set
ONE HOUR THREE HOURS
in firmware, and you can easily change
them.EDN
BLACK
R2
1k
LOAD
Figure 2 The LED is on when the timer is ready for work and waits for darkness.
It blinks during the delay, and it is off when the timer waits for reactivation.
R e fe r e nce
Raynus, Abel, AC line powers
microcontroller-based fan-speed regulator, EDN, Nov 9, 2006, pg 128,
www.edn.com/article/CA6387025.
1
SINE-WAVE
OUT
OP27
op-amp adder in Figure
high-bandwidth op amps.
OUTPUT
10V P-P, 1-kHz
edn090820di45401 DIANE
(PLACED IN THE 9-3 FOLDER)
designideas
and distortion. You can
increase input impedance
and improve commonmode rejection by using
instrumentation amplifiers. The output voltage
of an instrumentation
amplifier is proportional
to the voltage difference
between the positive and
the negative inputs. You
can amplify this signal
by connecting a resistor,
RGAIN, to the RG pins (Figure 2). The output voltage is generated between
the reference pin and the
output pin. This arrangement allows you to use the
reference pin to cascade
multiple signals together
in an adder configuration.
You can set each instru-
mentation amplifier to a
different gain.
This system has several
10V P-P, 1-kHz
advantages
over the simR
G
SINE WAVE
G
ple op-amp adder. For exIN
ample, each input has ex
SINE-WAVE
OUT
tremely high input impedAD8221
OUTPUT
ance and has independent
IN
common-mode rejection,
REFERENCE
which the instrumentation amp connected to
that channel determines.
10V P-P, 1-kHz
The higher the channel
RG
SINE WAVE
RG
gain, the higher the comIN
mon-mode rejection, and
OUT
the smaller the resulting
AD8221
error. You can also easily
IN
designideas
Flip-flop IC3 helps to change the sets IC1s reset time-out to be longer 1.32V input-threshold voltage of IC5
standby/on state with each press of the than IC2s reset time-out. The thresh- guarantees the standby position at first
control button. At the end of IC4s pro- old voltage of IC2, 2.9V, is also lower power-on because the factory-preset
gramming cycle, a low-to-high edge at than that of IC1, 4.6V. The worst-case output for IC4 is only 1.2V.EDN
IC3s clock input sets
the flip-flop to its op5.5 TO 72V
VIN
posite state, thanks
IC1
MAIN
5V
MAX6766TTLD2
POWER
to the feedback from
SUPPLY
OUT
IN
the inverter. IC 2s
UVLO
R1
TIMEOUT
C3
C1
reset triggers this
100k
ENABLE
10 F
1 F
C2
GND
RESET
action at power-up
0.47 F
to ensure that the
Q1B
switch is ready to
NTZD5110N
5V
5V
R3
R2
5.1k
change state. Tran100k
sistor Q1B and IC1s
C4
C5
0.1 F
0.1 F
reset output prevent
Q1A
NTZD5110N
IC2
IC4
the programming of
MAX6468XS29D3
DS4305R
IC3
incorrect states by
Q2
STANDBY/ON
VCC
IC5
VCC VOUT
74LVC1G79
BSS123L
74LVC1G14
blocking IC4s adjust
ADJ
RESET
MR
CLK
Q
VIN
VOUT
input during startGND
D
GND
up and power-fail
R4
conditions.
D1
510
You must block the
STANDBY
effect of IC2s powerup or -down reset
pulse on IC4s adjust
Figure 1 The circuit remembers its standby or on state if power fails with no operator present.
input; C2 therefore
edn090820di45431 DIANE
(PLACED IN 9-3 FOLDER)
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
running at 100 Hz and 1 MHz, respectively. At power-up, capacitor C1 remains the same, which forces RST on
SIGNAL IN
R6
1k
IC4B
HC08
R7
1k
R3
1k
CLOCK
IC1A
HC14
IC1B
HC14
D4
BZD23-4V7
D1
D1N4148
SENSE
IC4C
R4
HC08 3.3k
DETECT
R5
6.8k
R2
1k
1
CLK
RST
Q0
Q1
Q2
IC2
4024
D2
D1N4148
2
Q3
Q4
Q5
Q6
D3
D1N4148
D SET Q
IC3A
4013
QN
RST
C1
1 nF
POWER
RESET
32
5V
V1
R1
1k
IC4A
HC08
Figure 1 IC2 combines with three diodes to produce a stream of 36 pulses before resetting.
designideas
5
4
VOLTAGE 3
(V)
2
1
0
50
100
150
200
TIME (mSEC)
250
300
350
400
50 mSEC/DIV
Figure 2 Operating at 100 Hz, the circuit signals include the clock-sine-wave signal (red), the sense-square-wave signal
(green), and the detect signal (blue), which indicates the missing pulse.
EDN090917DI4503FIG2
MIKE
4
VOLTAGE
(V)
3
2
1
0
10
15
20
TIME (SEC)
25
30
35
40
5 SEC/DIV
Figure 3 The pulse train at a clock frequency of 1 MHz still shows the missing 36th pulse along with the power-reset
signal (blue).
IC3A low. That action puts the D flip- in. Diodes D1, D2, and D3 pull up to
MIKEform an AND gate
flop into a known state. As C1 chargesEDN090917DI4503FIG3
5V through R2 and
through R1, the voltage at the power to select the desired count. Counreset falls, letting clock pulses set IC3As ter IC2s outputs are binary, so, for a
outputs. You must keep the small val- 36-tooth sprocket with one missing
ue for the C1/R1 combination if you tooth, outputs Q0, Q1, and Q5 coruse a high input frequency with a low respond to 112132535.
count rate. As Figure 3 shows, the deYou can produce any count as high
sired count must exceed the duration as 128 by adding the appropriate diof the power reset. The values in Fig- odes on the Q outputs on IC2. In othure 1 provide a time of approximate- er words, you need to generate one
ly 0.6631 kV (the value of R1)31 nF missing pulse of 36 to simulate the
(the value of C1), or 0.66 msec, leav- 36-tooth sprocket. Thus, you select a
ing a minimum count of approximately count of 35; the circuit automatically
three at 1 MHz.
adds a count of one due to the oneFor the clock signal, the circuit clock delay of the counter. Because
uses a sine-wave signal with an am- you reset IC2 at power-up, all outputs
plitude of 5 to 10V from the system. are low, keeping the D input of IC3A
The clock signal goes through R3 to low, with a count of zero.
D4 and IC1A to produce a 5V squarewave signal. The signal goes to counthe circuit autoter IC2 and to one input of AND gate
IC4B. With the other input of IC4B matically adds a
coming from IC3As QN output, which count of one due
is high from power reset at start-up,
the input-pulse train passes through to the one-clock
IC4B, which simulates sprocket teeth delay of the
at the sensor. Resistors R 6 and R 7
halve the clock-signal amplitude just counter.
to make the graphics clear at signal
EDN090917DI4507FIG1
MIKE
designideas
ta-I/O lines to emulate the SPI clock,
SS, and MOSI. The software driver for
the I/O cards then has the responsibility of translating the data to be sent
into an SPI-compatible bit stream.
Listing 1, which is available at www.
edn.com/090917dia, contains the algo-
Leens,1Frederic, An Introduction
Equation
1024D IEEE Into IC and SPI Protocols,
R WA (D) =
R AB ,
strumentation
&
Measurement,
1024D1024
R
= No. 1, February
R AB , 2009,
Volume
WA (D)12,
1024
pg 8, www.imm.ieee-ims.org/docs/
ColumnsFebruary2009.pdf.
Equation 2
Equations for DI4530 (placed in 8 220SPI
folder
) Guide V04.01, Freescale
Block
Equation
2
Semiconductor,
JulyD2004, www.
R WB
freescale.com/files/microcontrollers/
Equations for DI4530 (placed in 8 20
folder
) (D) = 1024 R AB .
Figure 2 An MSO screen shows the SPI transactions using the digital-I/O lines.
D
doc/ref_manual/S12SPIV4.pdf.
Equation 1
R
R AB .
WB (D) =
1024
1
Equation 1 1024D
R WA (D) =
R AB ,
1024
1024D
R WA (D) =
R AB ,
1024
Equation 2
Equation
2 D Slovakia
Marin tofka, Slovak University of Technology,
Bratislava,
R WB (D) =
R AB .
AV = 1 +
R WB
Equation 4
Equation 3
Equation 3
R WA data
1024sheet proTheApotentiometers
=
.
V = 1+
R
vides the R
ground-referred
WB
1024 Dparasitic caWA
A
=
.
V = 1 + at the
pacitances
R WB A,
D B, and W termi-
If you
C AW
(X assume
= ) 2that
.4 pFthe
. five segments
The capacitance
Equation 7 per segment of the
five segments of the potentiometer is
Equation
C AW (X =5 ) 2.4 pF.
Equation 7
C SEGM 5C AB (X = ) 6 pF,
C AW (X = ) 2.4 pF.
Equation 6
C SEGM 5C AB (X = ) 6 pF,
Equation 8
Equation 8
n6
Equuation 6
C AB (X = ) C AW (X = ) 1.2 pF.
C AB (XEqu
= uation
) 6C AW (X = ) 1.2 pF.
= ) C AW (X =Equation
) C1.2 7pF
(X. = ) C
AB
n 7
AW (X
= ) 1.2 pF.
Equation 7
C SEGM 5C AB (X = ) 6 pF,
Equation
1 5C
C
(7X = ) 6 pF,
where
X5 2 denotes
the midscale of
SEGM
AB
the
resistive
DAC.
5C AB (X = ) 6Equation
pF, C 8 5C (X = ) 6 pF,
SEGMdistributed
AB RC line of
The five-step
theEquation
potentiometer
has
a
time constant
8
R
INPUT,
of SEGM = AB C SEGM = R AB C AB =DIGITAL
24 NSEC
AD5293
AD8677
5 OR 3.3V
15V
VLOGIC
RESET
n 8
5 8
Equation
R
SEGM = AB C SEGM = R AB C AB = 24 NSEC, Y
10
5
R AB
11
R AB
=
C SEGM = R AB C AB ==24
NSEC
C,SEGM = R AB SPI
C AB = 24 NSEC,12
Equation
9
SEGM
5
5
13
where
RAB is9 20 kV. The ground-reEquation
Wwiper
R WB
CW .
14
ferred
capacitance,
CW, of 40 pF
NC
EXT_CAP
n9
is much higher
than
the
intercapaci7
9
W REquation
WB C W .
WB C W .
W R WB C W .
1 F
VDD
SDIN
47 pF
NC
SCLK
SYNC
SDO
W 4
CW
RDY
GND VSS
100 nF
NC
8
OUT
5
CB
ANALOG INPUT
100 nF
15V
DIANE
(PLACED IN which
9-3 FOLDER)
dard SPI (serial-peripheral interface).
equals 0110, and you put the
After power-on, you must initially neu- desired C2 and C1 values at data potralize the write-in protection of the sitions D2 and D1. After performing
resistive DAC. You have to first pro- these steps, you change the wiper posigram the control bit C1 to the value of tion in which the control bit is C3, C2,
one, whereas it is zero by default. You C1, and C0, which equals 0001, and the
achieve this task by clocking in the data bits, D9 to D0, represent the gain
word containing C3, C2, C1, and C0, as 1024/D.EDN
100 nF
CA
VCC
IC1
4N35
1
1 T1
13
7
R1
1k
R2
1k
DOUTS2
4
IC2
4N35
R4
10k
DOUTS1
12 TO 12V
AT 30 mA
R3
10k
6
5
4
S1
1
D1
1N4004
D2
1N4004
S2
1
edn090903di45311 september
DIANE
(PLACED IN THE 9-17 FOLDER)
designideas
VCC
IC1
4N35
1
1 T1
13
7
R4
10k
DOUTS1
R1
1k
12 TO 12V
AT 30 mA
R3
10k
IC2
4N35
R2
1k
DOUTS2
VCC
S1
1
D1
1N4004
D2
1N4004
S2
1
IC3
4N35
1
S3
1
R5
1k
R6
1k
R7
10k
R8
10k
DOUTS3
DOUTS4
4
IC4
4N35
6
5
D3
1N4004
D4
1N4004
S4
1
Figure 2 By adding a third wire, you can connect four pushbutton switches.
edn090903di45312 DIANE
(PLACED IN THE 9-17 FOLDER)
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
44 Capacitance meter uses PLL
50 Resistor compensates
OTHER I/O
INTERFACES
nous serial port to generate PWM signals and convert them to a slow-movANALOG
ing analog signal (Figure 1). Many
OUTPUT
microcontroller-based stand-alone
MICROCONTROLLER
PULSE-WIDTH
electronic units dont use the synchroDEMODULATOR
nous serial port. Thus, you can use the
RC-LOWPASS-FILTER
NETWORK
microcontrollers baud-rate generator
and parallel-to-serial-converter blocks
to generate bit patterns to form a 256Figure 1 You can use an on-chip unused synchronous serial port to generate
bit PWM pattern. You can then filter
PWM signals and convert them to a slow-moving analog signal.
the PWM output with an RC filter to
extract an analog signal (Reference 1).
The synchronous communication is devoid of
the start and stop bits
edn090820di45451 DIANE
(PLACED IN THE 9-3 FOLDER)
of asynchronous mode,
256-BIT PWM CYCLE1
so the bit pattern can
TOTAL BYTES=20 ON-STATE BYTES+TRANSITION BYTE+11 OFF-STATE BYTES=32
generate long periods of
high or low level.
20 ON-STATE BYTES WITH VALUE 0FF2
TRANSITION BYTE3
OFF-STATE BYTES 0004
You can generate raw
00011111B
data with a decimal
value of 165 using this
concept (Figure 2). A
PWM-conversion cycle consists of generating 256 bitsthat is,
1
RAW DATA=165; ON-STATE=5V; OFF-STATE=0V.
2
NUMBER OF ON-STATE BYTES=165/8=20 (INTEGER DIVISION).
32 bytes. The number
REMAINDER=165(820)=165160=5.
of on bits corresponds
3
TRANSITION BYTE=00011111B=01F (NOTICE FIVE ONES FROM LSB SIDE).
4
to the value of the raw
NUMBER OF OFF-STATE BYTES=TOTAL 32 BYTESONE TRANSITION BYTE
20 ON-STATE BYTES=32120=11 BYTES.
data to convert into
ANALOG OUTPUT AFTER LOWPASS FILTER=(165/256)5=3.22V.
PWM. Hence, for 165
bits as the raw data,
Figure 2 You can generate raw data with a decimal value of 165 using this concept.
165 bits are on and 91
PWM OUTPUT ON
SYNCHRONOUS
TRANSMIT DATA
designideas
COMPUTE VALUES FOR VARIABLES FOR PWM GENERATION
ON-BYTE COUNT=RAW DATA/8
REMAINDER=RAW DATA8(ON-BYTE COUNT)
FORM TRANSITION BYTE BASED ON REMAINDER VALUE1
OFF-BYTE COUNT=31ON-BYTE COUNT2
Figure 3 You can tailor the PWM frequency to your application by selecting
a crystal, PLL, and baud rate.
bits are off. To generate a 165-bit onperiod, the first 20 bytesthat is, 160
bitstransmit as 03ff on-state bytes.
The trick lies in judiciously compos-
designideas
with the AD8033 op amp and IC3, a
74HC4606A PLL. The comparator
has a typical propagation delay of only
4.3 nsec. It has built-in hysteresis and
needs only a 5V supply. It is also available only in surface-mount packages.
The capacitance meter generates
two signals; one of them lags the other by 608. A 3-bit, self-correcting, divide-by-six twisted-ring counter comprising IC6, IC7, and IC13B provides the
lagging signal. The lagging signal connects to the COMP input of the PLL
(Pin 3), and the other signal is applied
to an RC circuit, which provides a 608
phase lag before it gets to the SIG input of the PLL (Pin 14). The PLL adjusts the frequency of its VCO (voltage-controlled oscillator) so that the
two input signals are in phase. The
resulting period of the VCOs output
signal (Pin 4) is proportional to the
measured capacitance.
On the low-capacitance range, signals with frequency FO are applied to
the PLL. On the high-capacitance
range, the frequency is FO/1000. IC8
through IC 10 provide the division,
and S2, IC4B through IC4D, IC5D, IC5E,
and the associated components provide the high-capacitance/low-capacitance range switching. The VCO of
the PLL runs at 6FO. The circuit divides this signal by three to provide
an output with a period thats proportional to the measured capacitance.
It provides the correct digits when
you measure with a frequency counter that you set to measure the period. You can calculate FO or FO/1000
from 0.1505/RXCX, where RX is R6, R8,
R9, or R10, depending on the selected
range.
The 74HC4046A PLL can exhibit
several problems. For example, it may
not start when you apply power, or
it may hang with the VCO running
with the VCO-input pin (Pin 9) stuck
high or low. The start-up circuitry,
The 74HC4046A
PLL may not start
when you apply
power.
from Pin 1 of IC3. The one-shot then
issues a 1.5-sec pulse that causes IC12B
to produce a 0.5-sec pulse that causes
either a positive pulse at the inhibit
pin or a low pulse at the VCOs input pin, depending upon whether the
PLL is low or high. After the 0.5-sec
pulse ends, the pulse from IC12A continues for 1 sec, giving the PLL time
to lock. LED D7 indicates phase lock.
If the PLL phase locks, all is well. If
it does not, the IC12A/IC12B one-shots
continue issuing pulses. Experiments
determined these methods for recovering from the anomalous states. Its
possible that the circuit wont always
recover, but these methods have been
effective on the test unit.
The circuit applies the 6FO signal,
divided by three, to buffer IC5Fs Pin
5. This action provides an output frequency whose period is proportional
to the value of the measured capacitance. The output provides the correct
digits without regard to the location of
the decimal point. To determine the
value of the unknown capacitance,
observe the setting of S1 and S2.
You can calibrate the circuit by us-
1 to 10 pF
10 to 100 pF
100 to 1000 pF
1000 to 10,000 pF
0.01 to 0.1 mF
0.1 to 1 mF
1 to 10 mF
Capacitance
5.24,
10.04
10.04, 23.22,
47.6, 102.68
102.68,
469.32, 1022.1
1022.1, 5226.9,
10,140
0.01014,
0.10052
0.10052,
1.034
1.034,
10.07
Measurement
error (%)
18.85,
2.89
6.37, 14.78,
13.68, 10.61
10.86, 12.5,
10.7
10.89, 11.28, 0
0.89, 0.88
2.27,
10.87
2.03,
1.24
designideas
R5
C5
270k
4.7 pF
1%
R6
301k
1%
1 TO 10 pF
R7
C6
270k
4.7 pF
1%
5V
C4
0.1 F
C2
39 pF
R3
4.7k
C3
39 pF
R4
4.7k
S1
R8
30.1k
1%
Q2
FO OR 2N3906
FO/1000
AT 0
2N3904
Q1
IC13A
74HC04
6
5
8V
C7
1 F
C8
0.001 F
1
IC1
AD8033
1
9
PE
10
15
Q0
14
Q1
13
Q2
12
Q3
11
Q3
5V
HIGH
LOW
CAPACITANCE
IC5E
CAPACITANCE
S2
74HC04
11
10
R
26
18k
C16
0.1 F
R27
47k
C9
100 pF
R14
82k
IC13D
IC13E
74HC04 74HC04
13
12 9
8
C13
47 pF
R22
1k
C14
R24
0.22 F 4.7k
10
2N3904
IC13F
74HC04
Q4
R25
4.7k
D3
1N914
CLR
1
12
10
PRE
9
D IC Q
7B
74HC74 8
11
CLK Q
CLR
13
AMIDON FB 101
FERRITE BEAD L1
R13
1.5k
5
D IC Q
7A
74HC74 6
3
CLK Q
MR
CP
2 J
3
K
4
D0
5
D1
6 D2
7 D3
4
PRE
6
ADCMP601
1
IC2
3
5
2
4
CX
IC13C
74HC04
6FO OR 6FO/1000 4
3
5V
IC6
74HC195
C10
0.1 F
5
4
5V
R11
510
R12
500
11
R21
2.2k
5V
C17
0.01 F
IC5D
IC4C
IC4D
74HC04 74HC00
9
8 5
74HC00
6 13
4
11
IC4B
12
74HC00
2
3
1
6FO/1000
6FO
IC8
74HC192
14
MR
5
CPU
4
CPD
11
PL
15
1
10
9
D0
D1
D2
D3
12
TCU
13
TCD
3
Q0
Q1 2
6
Q2
7
Q3
IC9
74HC192
14
MR
5
CPU
4
CPD
11
PL
15
1
10
9
D0
D1
D2
D3
12
TCU
13
TCD
3
Q0
Q1 2
6
Q2
7
Q3
Figure 1 A capacitance meter connects to a frequency counter measuring pulse width to provide a capacitance measurement.
ed
(PL
5V
IC3
74HC4046A
5V
VCC 16
PLL
2
PC1
PC2 13
SIG
1
PCP
3
COMP PC3 15
14
FO OR FO/1000
AT 60
C1
1300 pF
5%
5V
R23
82k
R1
3.4k
1%
R2
1M
D2
1N914
R18
1k
VCO
6
C1A
VCO 4
7
C
OUT
11 1B
R1
12
DEM 10
R2
OUT
9
VCOIN
5
INH
8
VSS
IC5A
74HC04
2N3904
R15
22k
D1
1N914
9
Q3
C12
0.22 F
R17
100k
R16
56k
R19
2k
10
IC4A
74HC00
5V
R20
4.7k
D5
1N914
C11
0.47 F
IC5B
74HC04
1
2
D4
1N914
D6
1N914
5V
C15
0.22 F
6FO
R30
10k
5V
5V
IC10
74HC192
14
MR
5
CPU
4
CPD
11
PL
D0
D1
D2
D3
12
TCU
13
TCD
3
Q0
Q1 2
6
Q2
Q3 7
dn090820di45441 DIANE
LACED IN THE 9-17 FOLDER)
R31
220k
IC5C
74HC04
12
13
R29
2.2k
R28
2.2k
15
1
10
9
R32
220k
C18
0.01 F
TC
LOCK
INDICATOR
2 RX/CX
C20
20 F
10%
1 CX
D7
S
T
5 B
C19
100 pF
HLMP-1321
IC12A
74HC4538
4 A
IC11
74HC163
1
R
9
PE
7
CEP
10
CET
2 CP
DIVIDE BY 3
3
D0
Q0
4
D1
Q1
5
D2
Q2
6 D3
Q3
R33
220k
R34
330
6
3 R
IC12B
74HC4538
14 RX/CX
C21
6.8 F
10%
14
13
12
11
15 CX
12 A
15
11 B
S
T
R
Q
Q
10
9
13 R
6FO
C22
20 F
10%
IC5F
74HC04
5
6
designideas
(continued from page 47)
trinsic capacitance of the test circuit is
2.8 pF. Using this correction, the values you obtain on the lowest two ranges are accurate to approximately 62%,
or 61 pF.
You must observe capacitor polarity
when measuring electrolytic capacitors. Connect the negative end of the
capacitor to the grounded terminal.
Also, the circuit provides no overvoltage or ESD (electrostatic-discharge)
Resistor compensates
for instrumentation-amp gain drift
R e fe r e nce
Equation 1
sheet (Reference 1) is
49, 400
GAIN = 1for
+ DI4523
. (placed in the 9 3 folder
Equations
RG
2 RA
49, 400
(1 + ) BeGAIN
11+ 20-kV
. resistors.
GAIN
= 1 +chip
Equation
1R G resistors are
1of+
this Design Idea, you can compensate cause all
of
these
R
20
,
000
(1 + )
Equation
G
1 they
2 RA
49, 400 (1 + )
Equation
49,resistors
400= 21 +R
GAIN
zero-drift
1 +
= (Figure
Equation
2A , 1), then
10,2000 R G
20, 000 (1 + )
REquation
G
2 RA
49, 400 (1 + )
Equation 2
GAIN = 1 + 49, 400 (1 +
1 )+
16
15
14
13
,
2
R
A
R
20
,
000
(
1
+
GAIN
=
1
+
1
+
49,G400 (1 +
)
2 R A
RG
GAIN34= 1 +
Equation
1 + 20, 000 (1 +
AD8295
Equation
49, 400 (1 +
2 R A RG
)
20, 000 (1 +
GAIN
=
1
+
1
+
,
IN 1
12 A2 OUT
R
20
,
000
(
1
+
G 49, 400
A2
A ,
Equation=349R
, 400
INSTRUMENTATION
=
;
where RD
is
the
drift
of
the
internal
G
2
Equation
3
RG
10, 000
AMP
GAI
Equation
3N11
matched
resistors.
If
RA
49, 400
Equation 3
R,
49,=400
RG
R
10
G49, 400 ,=000R A ,
11
A ,
R G 45= 10, 000
Equation
Equation
RA
49, 400
RG
10, 000
10
=
,
drift of the gain
RG
10, 000 then the first-order
R1
3
49
, 400
A1
Equation
4, 000
cancels,
the
gain splits
equally
GAIN
11 . beRRGand
;
20k
A== 10
Equation
GAIN411
tween theEquation
instrumentation
amplifier
4
IN 4
R2
9
49, 400
and A1. Solving
for RG and RA yields
Equation 4
RG =
;
20k
491
, 1400
R GGAI
= 6N
;
49
,
400
Equation
5
6
8
7
Equation
R G = 5 GAIN11;
49
,
400
GAI
N
1
1
RA
VS
RG =
;
49, 400 (1 + )) 2 R A
GAIN11
Equation
RGAIN
,5000
A = 10=
1 + GAIN11 .
=
RG
Equation
5
20, 000 (1 + )
For gainEquation
greater 5than 100, the amOUT
GAIN
11 . than
A = 10, 000becomes
Equation 5
plifierRresistance
greater
R A =610, 000 GAIN11 .
Equation
90 kV, which
be problematic.
Figure 1 In this configuration, the first-order drift of the gain cancels, and the
R A =can
10, 000
GAIN11 .In
this 1
case,
you can use A1 in an invertgain splits equally between the instrumentation amplifier and A1. R = 10, 000 GAIN
1
.
A
21 2 R A
ing configuration
with
, 400a (gain
1 + ))of
Equation 6 49
GAIN
= 1 + 6
=
Equation
RG
6
20, 000 (1 + )
edn090903di45231 DIANE
Equation
(PLACED IN THE 9-3 FOLDER)
49, 400 (1 + )) 2 R
Equation 6
GAIN = 1 + 49, 400 (1 +)) 2A R =
A
R
20
,
000
(
1
+
)
GAIN
= 1 + 49,G400 (1 +
)) 2 R A
50 EDN | OCTOBER 8, 2009
RG
20, 000 (1 + )
GAIN = 1 +
49
49, 400 (1 + )) 2 R
, 400
R G 1 20
000 (1 + )
A
GAIN = 1 +
+
.
=
A2IN A2IN
VS
((
))
N11
R A = 10, 000
GAIN11 .
GAIN11 .
(Figure
2). With
an amplifier resisEquation
6
tance of 10 kV,
A2IN A2IN
VS
49, 400 (1 + )) 2 R A
1
49, 400 16
GAIN = 1 +
+
.
=
R
20
,
000
(
1
+
)
(
1
+
)
RG
G
AD8295
1
49, 400 (1 + )) 2 R A
49, 400
+
.
=
RG
20
,
000
(
1
+
)
(
1
+
)
RG
R e fe r e nce
AD8295: Precision Instrumentation
Amplifier with Signal Processing Amplifiers, Analog Devices, www.analog.
com/en/amplifiers-and-comparators/
instrumentation-amplifiers/ad8295/
products/product.html.
14
IN 1
13
A2
INSTRUMENTATION
AMP
RG
12 A2 OUT
11
10
R1
20k
A1
15
designideas
(
)
Equation 5
IN 4
R2
20k
5
7
RA
VS
OUT
Figure 2 For gain greater than 100, the amplifier resistance becomes greater
than 90 kV, in which case you can use A1 in an inverting configuration with a
gain of 21.
edn090903di45232 DIANE
(PLACED IN THE 9-3 FOLDER)
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
45 Class B amplifier has
automatic bias
ues, and the process repeats. The timing depends on both the RC time constant and the hysteresis resulting from
the spread between the two threshold
values (Figure 2). Unfortunately, although inverter manufacturers specify the hysteresis voltages in their data
sheets, the devices have a fairly large
range. In addition, they likely have
some temperature dependence. These
uncertainties make it difficult to design
the circuit to have a predictable oscillating frequency.
A simple inverter, without the hys-
Resistance (kV)
Timing capacitance
(pF)
Hysteresis
capacitance
(pF)
Hysteresis
voltage
(V)
Total
time
period
(nsec)
10
470
100
0.88
3462
10
470
220
1.59
6850
10
12,000
12,000
2.5
333,526
0.3
220
220
2.5
221
12,000
12,000
2.5
34,086
R
10k
VC
HYSTERESIS RANGE
A1
VOUT
UPPER THRESHOLD
LOWER THRESHOLD
CT
100 pF
3.24
3.33
3.42
3.51
3.6
3.64
3.78
3.8
TIME (SEC)
designideas
parts determine (Figure 3).
Thus, the relaxation time constant is
Whenever Stage 1 crosses its thresh- R(CT1CH) and the relaxation voltage
old, the extra Stage 2 injects an addi- is either VCT5(VTHRESH1VHYST2VLOW)
tional charge through a feedback ca- exp(2t/R(CT1CH)) or VCT5(VHIGH
pacitor to make the timing capacitors 2 ( V T H R E S H 2 V H Y S T ) ) e x p ( 2 t /
voltage jump past the threshold. The R(CT1CH)), depending on which halfRC charging current reverses direction cycle is occurring. You calculate the time
to get back to the threshold voltage. from VTHRESH1VHYST back to VTHRESH as
When it gets there, the hysteresis-in- t152R(CT1CH)ln((VTHRESH2VLOW)/
jection circuit again jumps the voltage (V THRESH1V HYST2V LOW)). For the
past the target so that the RC timing other half-cycle, t 252R(C T1C H)
circuit must again reverse the charg- l n ( ( V H I G H 2 V T H R E S H ) / ( V H I G H 2
ing current to seek the threshold volt- VTHRESH1VHYST)).
age (Figure 4). This process continues
You should add the total propagation
endlessly at a fairly predictable rate. time (tPLH1tPHL) through stages 1 and
In the equations, CT is the timing ca- 2 to the total period. Unless you want
pacitor, CH is the hysteresis capacitor, the circuit to operate at its maximum
VTHRESH is the threshold voltage, VLOW frequency, these propagation times beis the low output voltage, and VHIGH is come insignificant. The period prethe high output voltage.
CH
You can view the hysteresis-over100 pF
shoot voltage, VHYST, as the result
of a capacitive voltage divider that
R
VCH
timing capacitor CT and hystere10k
sis capacitor CH form. When Stage
1 toggles Stage 2, its output jumps
VCT
VSTAGE1
VSTAGE2
from a low value to a high value or
from a high value to a low value by
an amount of V HIGH2V LOW, and
STAGE 1
STAGE 2
CT
the voltage of the timing capacitor
470 pF
jumps by VHYST5(VHIGH2VLOW)(CH/
(CH1CT)). Second, the voltage of the
timing capacitor relaxes back toward
Figure 3 The addition of a positiveStage 1s output voltage by drawing
feedback stage provides hysteresis to a
current through both the timing casimple inverter stage.
pacitor and the hysteresis capacitor.
diction then depends only on passivecomponent values and their tolerances, temperature, and aging coefficients.
The series combination of CT and CH,
however, presents a capacitive load to
Stage 2. This load affects Stage 2s rise
and fall times, the sum of which you
must add to the total period, T.
In the case of CMOS parts, such as the
74VHC04 from Fairchild Semiconductor (www.fairchildsemi.com), rise and
fall times depend on the output resistance of the part as well as on the external components. If you model the Stage
2 output as an RC circuit, you can estimate the 10 to 90% exponential rise and
fall times as tRISE25tFALL252.2RO(CTCH/
(CT1CH))1tO, where tRISE2 is the rise
time, tFALL2 is the fall time, RO is the out
put resistance of the part30V for
the 74VHC04and tO is the no-load
rise timein this case, 4.5 nsec for
the VHC04. Thus, the total period is
t11t212(tPLH1tPHL)1tRISE21tFALL2.
Also note that the timing depends
on inverter output voltages and the
location of the threshold voltage
within that range. For example, a
CMOS part whose outputs are close
to the power rails is more predictable
than a TTL (transistor-transistor-logic) part, and a 74HC part with a midpoint threshold voltage has a more
symmetric output than an HCT part
whose threshold voltage is offset for
TTL interfacing.
edn090903di45262 DIANE
(PLACED IN THE 9-3 FOLDER)
Figure 4 Hysteresis results from a charge burst from Stage 2 that jumps the timing-capacitor voltage past the switching threshold
by a known, fixed amount.
VCC
R1
Q3
Q1
C2
C3
R2
R3
VBIAS
IC1
C1
Q4
Q2
Figure 1 A bias current flows in the transistors that prevents Q1 and Q2 from
being off simultaneously.
designideas
VCC
VCC
VCC
R1
R1
Q3
Q1
Q3
C2
C3
R2
C3
C1
Q4
IC1
R2
VBIAS
Q2
R3
IC1
(a)
Q1
C2
R3
VBIAS
VCC
C1
Q4
Q2
(b)
Figure 2 On a positive half-cycle, current flows from Q1 through C1 to a load (a). On a negative half-cycle, current flows
through Q2 (b).
edn090820di45362
DIANE
12V
(PLACED IN 9-3 FOLDER)
R1
1.5k
2N2907A
Q3
IN
C3
1 F
C2
100 F
R3
20k
R2
20k
2N2222A
Q1
C1
470 F
12V
R4
20k
2
2V
2N2907A
IC1
TLV271
3
Q4
OUT
Q2
2N2222A
0.25
edn090820di45363 DIANE
(PLACED IN 9-3 FOLDER)
0.2
0.15
DISTORTION
(%)
0.1
0.05
0
10
100
1000
FREQUENCY (Hz)
10,000
MIKE
100,000
designideas
Cable tester uses LEDs to find faults
Pavel dek, Apri, Ronov pod Radhotem,
Czech Republic
4
16 LEDs
74HC04
INVERTER
74HC154
FOUR- TO
16-LINE
DECODER/
DEMULTIPLEXER
CABLE UNDER
TEST
74HC04
INVERTER
74HC154
FOUR- TO
16-LINE
DECODER/
DEMULTIPLEXER
74HC04
INVERTER
pulse to the coils is sufficient for operating the relay. Many relays can operate with a continuous coil current, and
some dual-coil relays have internal
contacts that interrupt the coil current
after it completes a state change. Continuous coil voltages can drive such
relays if energy efficiency is not a big
concern.
The need to differentially drive the
coils results in crowded drive circuits
for dual-coil relays. Drivers usually in-
designideas
clude logic elements to make sure to
energize only one coil at a time. The
design in Figure1 uses only two MOSFETs to drive a dual-coil RF relay. The
Agilent Technologies (www.agilent.
com) N1810UL RF switch has dual
24V coils and internal current-interrupting contacts.
When logic input is high, Q1 conducts and changes the relay state by
activating L1. The states of the current-interrupting contacts also change.
Meanwhile, Q2 is off because Q1 pulls
down its gate, which avoids fighting
between the coils. If you then apply a
low signal to the logic input, Q1 turns
off and keeps the L1 coil inactive. Because R1 pulls up Q2s gate, Q2 turns on
and energizes L2. The 1N4007 diodes
prevent inductive kickback. The idea
is applicable to dual-coil relays with
continuously rated coils or with current-interrupting contacts. In the absence of current-interruption contacts,
L1 can serve as a pullup, and R1 therefore becomes redundant.EDN
VDD
24V DC
L1
L2
R1
10k
N1810UL
1N4007
1N4007
VDD
LOGIC
INPUT
Q1
BS107
Q2
BS107
edn091022di44901 DIANE
(PLACED IN THE 10-22 FOLDER)
designideas
Edited By Martin Rowe
and Fran Granville
Negative-to-negative switch-mode
converter offers high current and
high efficiency
D Is Inside
46 ADC for programmable logic
inexpensive controller
ETo see all of EDNs Design
Ideas, visit www.edn.com/design
ideas.
0V
3.86V
R4
5.76k
R5
1.96k
C6
220 F
C5
10 F
D1
EC31QS03L
L1
2.2 H
NEC/TOKIN
MPLC0730
Q1
FDMS8690
8
EXT
9
VCC
10 SHDN
C1
47 F
IC1
MAX668
C2
10 F
PGND
1 LDO
4
REF
FB
FREQ
C3
1 F
CS+
C4
0.22 F
GND
R2
100k
500 kHz
5
MAX4322
IC2
4
1
R6
5.76k
R1
10
3.6V
C7
0.1 F
R7
1.96k
3.6V
4A
5.2V
3.95V
OR 1.25V
ABOVE
5.2V
3.86V
6
R3
0.02
7
R8
2k
5
3
C8
0.47 F
5.2V INPUT
Figure 1 A switch-mode converter generates a regulated negative supply voltage from a more-negative input voltage.
designideas
which is also the node from which current is delivered to the load.
The circuit converts a 25.2V supply voltage to 23.6V. The boost converter, IC1, regulates its output voltage to maintain its feedback voltage
at 23.95V1.25V above 25.2V. Resistor R8 and capacitor C8 form a lowpass filter that stabilizes the voltage at
FB. You must then select the R4/R6 and
R5/R7 pairs to produce the desired out-
LED1
LED2
LED8
CPLD/FPGA/MICROCONTROLLER
Figure 1 This circuit charges a capacitor through a resistor while measuring the
time to charge the capacitor to a certain voltage.
edn090903di45291
DIANE
designideas
Equation 1
charging and the timing. For an
FPGA or a PLD, you can perform a discharge by setting the
t
I/O as an output pin and forc
R
ing a zero at that pin. You can
VTH = VDD 1e C
V
charge the capacitor by setting
COUNTERVALUE =fCLK R C ln 1 TH .
1
eter. Meanwhile, the internal coun- true analog-to-digital measurements.
VTH = VDD 1e RC
VTH By
replacing the pullup resistor with
ter starts. When
the capacitor
voltage
COUNTERVALUE
=fCLK
R C ln
1
.
V
reaches the input threshold voltage,
a
DD
T=
fCLK
R C
the 8-bit value. In this application, a linear change in the charging time,
DD 1e
VTH
.
VDD charges a 22-nF capaci- conversion.EDN
1-kV
resistor
UNTERVALUE
V
tor. The input clock of the PLD is
NTERVALUE
=fCLK R C ln 1 TH .
fCLK
1.8432 MHz. The input threshold is R e f e r e n c e s
Equation 2 VDD
1.5V at a supply of 3.3V. This arrange- 1 Eggers, Torsten, and Thomas
If you assume that the capacitor ment allows a measurement range be- Schmidt, AN10187 Low-cost A/Dvalue, the input threshold voltage,
C tween a counter value of 25 and 270, Conversion with Philips LPC Microt DISCMIN
= VTHRESHOLD
fair- equivalent
.
2
and the
clock frequency
remain
to a resolution of almost controllers, Philips Semiconductors,
I SHORT
ly constant over the operating range, 8 bits. Figure 3 shows the capacitor Oct 4, 2002, www.nxp.com/acrobat_
the charging time is linearly depend- charging/discharging waveform.
download/applicationnotes/
ent on C
the value of the resistor. If you
Every ICs I/O pin has a certain bias AN10187_1.pdf.
.
N = VTHRESHOLD
replace
the resistor
with a potentiom- sink or source current, causing a volt- 2 Using an I/O Port Pin as an
I SHORT
eter, a counter value depends on the age drop over the charging resistor. A/D Converter Input, Holtek, www.
.
potentiometer position. The applica- This situation limits the charge volt- holtek.com.tw/english/tech/appnote/
T
tion uses a Xilinx (www.xilinx.com) age to VDD2RCHARGE3IBIAS. In other uc/pdf/ha0128e.pdf.
XC9500 XL CPLD (Figure 2). The words, if the charging resistance is 3 AVR400: Low Cost A/D ConvertI/O, which VHDL (very-high-speed- too large, the capacitor doesnt charge er, Atmel, www.atmel.com/dyn/
IC hardware-description language) above the input-pin threshold volt- resources/prod_documents/
declares as a tristate buffer, first shorts age, stopping the circuits operation. doc0942.pdf.
the capacitor. Hardware limits the Similar applications for microcontrol- 4 Quiring, Keith, Implementing An
output short-circuit current of the lers or PLDs (references 1 through Ultralow-Power Thermostat With
I/O pins to 610 mA, so the capaci- 5) include adding multiple inputs to Slope A/D Conversion, Texas Instrutors shorting should last long enough a single I/O pin and using a different ments, Jan 2006, http://focus.ti.com/
to guarantee a full discharge. You can pullup-resistor value for each input. lit/an/slaa129b/slaa129b.pdf.
calculate the minimum shorting time By discriminating the charging times 5 CoolRunner-II Low Cost, Low
using the capacitor value, short-cir- for each resistor, the PLD can decide Power Thermometer for Embedded
cuit current, and discharge voltage, which resistor or combination of resis- Designs, Xilinx, Nov 29, 2004, www.
assuming that the threshold voltage tors the user has actuated.
xilinx.com/support/documentation/
must discharge from the capacitor:
Another application for microcon- application_notes/xapp438.pdf.
designideas
Use two phases to cut current
and improve EMI
designideas
5 TO 20V
INPUT
T2A
DRQ127-4R7
1 D
MAX
2
66.5k
10 nF
6.8k
10 nF
100 nF
12.4k
VOUT
107k
24
3V8
SENSE1 23
SLOPE
3 BLANK
4
PHASEMODE
5
IC1
LTC3862
10
7 I
TH
8
FB
9
SGND
10
CLKOUT
11
SYNC
12
PLLFLTR
D1
PDS1040
24.9k
RUN 21
INTVCC 19
CS1
20 F
HAT2169
10 nF
0.006k
66 F
84.5k
VIN 20
FREQ
6 SS
SENSE1 22
1 nF
T2B
DRQ127-4R7
132 F
12V
6A OUTPUT
1 F
4.7 F
0.006k
G1 18
COUT2
150 F
PGND 17
HAT2169
G2 16
CS2
20 F
NC 15
SENSE2 14
SENSE2 13
D2
PDS1040
10 nF
10
T1A
DRQ127-4R7
T1B
DRQ127-4R7
Figure 3 By adding second power stage and shifting the phase by 1808, you can reduce the output ripple currents by
more than 50%.
edn090625di44123 DIANE
(PLACED IN THE 7-9 FOLDER)
designideas
VIN
MAX16823
7
8
9
2
8
4 10F200
4
6
10
11
IN
OUT1
IN
OUT2
IN
OUT3
DIM2
2
1
16
DIM1
DIM3
LEDGOOD
LGC
REG
22 F
15
CS1
14
CS2
13
CS3
GND
12
R1
R2
R3
Figure 1 A microcontroller provides pulses with adjustable widths to create fading in LEDs.
output at Pin 3 of the 10F200, you access the tabled number of dwell cycles
from the first table entry to the last
for a high final state or from the last
entry to the first to arrive at the final
low state.
Fade-transition timing is user-selectable for either a 3- or a 9-second
period. The circuit periodically samples both the fade rate and button or
switch mode, allowing you to multi-
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
43 Solar-powered sensor
controls traffic
PREAMPLIFIER
CIRCUIT
900- TO 1700-NM
SWIR AREA
CHARGE-COUPLED
DEVICE
IMAGE-DATA GRAB
ADC
IMAGE-GRABBING
CARD
(LVDS INTERFACE)
FOUR-PIN
COMMAND PORT
INTEGRATION-TIME
CONTROL
TIMING-DRIVER
CIRCUIT
TIMING-GENERATOR
CIRCUIT
MAIN CLOCK
CIRCUIT
MICROCONTROLLER
(RS-232 INTERFACE)
Figure 1 An ADC digitizes an analog signal from an SWIR sensor and sends
the signal to a frame grabber for processing.
Figure 2 An electroluminescence
image of solar cells shows dark
areas that indicate failed cells.
6V, 900-mA
SOLAR CELL
dumb, with relays, cams, and switches, although they now may include
software that accepts data from local
sensors, automobile-sized inductive
loops buried in the asphalt. Modern
controllers have gained some intelligence. For example, they may share
BQ24083R
BATTERY CHARGER
Th is de
s ig n w
as
winning
ent
r
y
in
EDNs rec
ent onli
ne
IRon
Designe Circuit
r
see the contest;
design at complete
w
com/091 ww.edn.
126dia
LOW-DROPOUT
REGULATOR, SWITCH
3V, 19-AHR
LITHIUM BATTERY
MEASURE VOLTAGES
STRIP-DETECTOR
PNEUMATIC
1.5V OPA333
GENERATOR
TWO
PRESSURE
SENSORS
MOVING
WEIGHT
3V
INSTRUMENTATION
AMP INA333
SWITCHED
3V
2.4-GHz
CC2500
WIRELESS
TRANSCEIVER
TMP102
TEMPERATURE
SENSOR
WEIGHT
WIM-DETECTOR
CAPACITIVE
CAP PAD
CAPACITIVE
SENSOR
940-nm LED
FET
PIN
PHOTODIODE
OPA364
AMP
DRIVE
IR-BEAM
INTERRUPT
DAC6311
DAC
MSP430
F248
MICROCONTROLLER
SWITCH,
LED
PGA112
PROGRAMMABLEGAIN AMP
PASSIVEINFRARED
DETECTOR
OPA364
AMP
MOVING IR
Figure 1 Most of the circuit amplifies outputs from four sensors, digitizes them with the MSP430s 12-bit ADC, does some
preprocessing, and messages the controller.
designideas
data with nearby interP3
sections, respond to radio
CAP PAD
RC=100 SEC
requests from emergency
R14
J4
R15
vehicles, and sometimes
100k
2k
CAP PAD
4
take commands from a
3
C13
traffic-control center. This
T=RCP
D1
EMS
220 pF
D
CP
Design Idea describes the
1N5333
2
24 nF
TSP (traffic-sensor post),
Q1
1
G
CAP DRIVE
ESD
a more accurate, effective,
S QMN-2N7002
inexpensive, and easy-to863-1N5228BG
install approach to moni
10-mSEC MINIMUM PULSE
toring traffic flow. These
30-mV CAPACITIVE SENSOR
sensors measure vehicle loFigure 2 The Cap Pad sensor has a nominal capacitance of about 24 nF at rest, with a
cation and speed in four or
change of about 7% full-scale when a truck passes.
more streets at an intersection or at a distance from
the intersection for early warning. A the deep-IR band for moving IR sourc- tion. You use multiple pads to handle
second application of this technology, es. This technology finds use in inex- multilane roads. The Cap Pad can be
the WIM (weight-in-motion) sensor, pensive motion-detecting lamp con- fastened to the asphalt with adhesive
edn091126newone DIANE
weighs moving trucks.
trols and senses vehicles from
30 feet or pavement tape or buried under as
(PLACED IN THE 11-26 FOLDER)
The circuit comprises a wireless, away. The detection range is good, the much as an inch of asphalt for protecsolar-powered sensor array that handles parts are cheap, and the beam can see tion. Its materials cost is only a couple
all the data collection at an intersec- through a layer of dirt. It cant measure hundred dollars, a huge saving over the
tion (Figure 1). Cities can install these speed, distance, or direction.
piezoelectric WIM sensors currently in
sensors at each of the four corners of
The TSP also uses conventional use.
an intersection for full coverage. The pneumatic tubes. Rubber tubes are staThe TSP also uses a near-IR transsensors send data to the single control- pled to the asphalt and feed two pres- mitter/receiver using a pulsed LED for
ler box over IEEE 802.15.4 in a star sure sensors. This approach accurately transmission and a PIN (positive-innetwork. The approach combines four measures speed, but permanent instal- trinsic-negative) photodiode for resensors in an inexpensive, low-mainte- lations cannot use it because it gets ception. Both need cylindrical lenses
nance, 6-in.-diameter, 6-foot-tall post. damaged easily. Municipalities often to focus the beam to a 28-wide, 58-high
You can build the circuit into the post deploy pneumatic tubes to measure ellipse that covers a remote retrorethat holds the traffic lights, or you can traffic volume in road construction.
flective screen, as in highway signs, or
use it stand-alone. Not all TSPs require
The Cap Pad comprises a 10-in.312- to the IR sensors on another TSP. A
all four sensors; you can select those foot sandwich of three 0.05-in.-thick multilayer optical bandpass filter that
that your application needs based on stainless-steel sheets separated by two removes visible light further improves
usage. The TSP is the first wireless ap- 0.05-in.-diameter closed-cell urethane- the range.
proach to this problem, and one of the foam layers (Figure 3). You capacitivePrecision capacitive sensors can measensors, the Cap Pad, provides a huge ly measure the 0.025-in. deflection of sure an air gap between adjacent metal
advantage over current expensive and the pad under a trucks tire to weigh plates to subnanometer accuracy. Uninaccurate WIM sensors (Figure 2).
the axle. One Cap Pad can handle fortunately, accuracy in the WIM appliThe TSP uses a PIR (passive-infra- the WIM requirements, and using two cation requires flat and parallel surfaces,
red) sensor that looks 10 microns into can add speed and direction informa- and the Cap Pad has neither. Capacitive sensors can also accurately measure
a force on adjacent flat plates with a reSTEEL
storing spring, but flatness and parallelism are still requirements. Maintaining
parallelism over a 10-in. pad would be
0.25 IN.
difficult, and roads are seldom flat.
If compression of the air pockets in
closed-cell foam provides the restorCLOSED-CELL
ing force, however, the resulting spring
URETHANE FOAM
constant changes from the conventional F5K3x of springs or cantilevered
Figure 3 The Cap Pad sensor is a 10-in.312-foot sandwich of three 0.05-in.beams to F5P03H/(H2x), where F
thick stainless-steel sheets separated by two 0.05-in.-diameter closed-cell
is force, P0 is atmospheric pressure,
urethane-foam layers.
H is the starting gap, and x is the dis-
designideas
placement. The result of this equation
is that the capacitance of the pad varies linearly with applied force, and the
surfaces of the Cap Pad no longer need
to be parallel or flat. It accurately measures a force regardless of its size.
Most of the circuit amplifies outputs from the four sensors, digitizes
them with the MSP430s 12 bit-ADC,
does some preprocessing, and messages the controller. The 6V solar panel,
40 IXYS (www.ixys.com) solar cells in
series, charges a 19-Ahr, 3V, lithiumpolymer battery through IC1. Lowdropout regulator/switch IC2 regulates
battery output at 3V. The battery generates more than 4V at full charge and
3.2V at the end of charge, and the
low-dropout regulator at 42 mA generates only 50 mV. IC2 also switches
active-mode 3V power.
The road-strip sensor senses the 0.1to 1-psi pulse when a car drives over
the pneumatic tubes. A 400V silicon
bridge sensor differentially outputs approximately 50 mV. Instrumentation
amplifiers IC3 and IC4 boost the output to a few volts. The pressure sensor,
Self-oscillating
H bridge lights
white LED from
one cell
Luca Bruno, ITIS Hensemberger
Monza, Lissone, Italy
VBAT
S1
R4
3.9k
Q4
R3
3.9k
BC557C
ON/OFF
Q3
BC557C
VBAT
R5
15
C1
1.5 nF
R1
5.6k
D1
BYV1030
VBAT
R2
5.6k
C2
1.5 nF
R6
15
C3
1 F
D3
WHITE LED
Q1
BC550C
BC550C
BT1
1.5V
SINGLE
CELL
Q2
C4
1 F
D2
BYV1030
Figure 1 Resistors R1 and R2 and capacitors C1 and C2 set the oscillation frequency.
designideas
Transistors Q1, Q2, Q3, and Q4 form
the H bridge, which acts as a simple
charge-pump converter and requires
only two small, inexpensive ceramic
capacitors, C3 and C4, to perform its
function. When Q2 and Q4 are on, capacitors C3 and C4 charge to the battery voltage through forward-biased
Schottky diodes D1 and D2. When Q1
and Q3 are on, they discharge the capacitors through resistors R5 and R6
and the LED. Because this process repeats at a high rate of speed, the LED
appears always on.
The circuit oscillates with a frequency based on time constants R1C1 and
R2C2. During discharge, the voltage
that develops across resistors R5 and R6
and the LED remains approximately
constant because of the high switching frequency. The measured value,
for a nominal 1.5V battery voltage, is
3.8Venough to drive a white LED
with a forward voltage of 3 to 3.5V.
Resistors R5 and R6 set the LEDs peak
current and limit the possible current
(R41R5)]R5}, where VMAX is the maximum desired output voltage and VCC
is the supply voltage. To achieve optimum operation, increase the PWM signals duty cycle when you need higher
voltages. Use the following equation
to determine the 8-bit PWMs value:
2552VOUT/(VOUT2VIN)3255, where
VCC
5V
R5
10k
R1
10k
C4
100 nF
Q1
R2
2.2k
VCC
5V
C3
100 nF
(ADC0)PB5
BC858ASMD
D2
BAS70
R4
33k
2
(ADC3)PB4
IC1
3
(ADC2)PB3
ATTINY15
7
(ADC1)PB2
6
8
(OCP)PB1
VCC
5
4
(AREF)PB0
GND
L1
330 H
VOUT
10V
C1
22 F
edn091112di45771 DIANE
(PLACED IN THE 11-26 FOLDER)
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
40 Reset an SOC
power-supply-sequence testing
46 Inexpensive power switch includes
3V
V
RS
100k
0.2%
16 15 14
13
VS
NC VS
NC
470 nF
1
NC
2
3
4
NC
ST
32k XOUT 12
11
NC
VREF
RR
10k
10 nF 0.2%
10
VS
2
IC1
ADXL335
32k YOUT
COM
NC 9
NC
10 nF
Z
X
RR
10k
0.2%
VREF
RS
100k
0.2%
32k
ZOUT
8
VGZ
AD8603,
AD8607, OR
AD8609
IC2A
OUT
6.2k
AD8603,
AD8607, OR
AD8609
IC3
SN74AHC132
IC2B
LED
HLMP-EG3A
10 nF
0V
Figure 1 The tilt on MEMS accelerometer IC1 produces a voltage, VGZ. When compared with VREF and 2VREF, VGZ
produces a digital output at the NAND gate.
designideas
ent the detector from the top down or
from the bottom up. Op amp IC2 compares the voltage at the ZOUT pin to the
reference voltage, VREF . If the positive
voltage at the ZOUT pin is equal to or
lower than the reference voltage, the
output of IC2A goes high, and the output of IC2B remains high (Reference
2). Thus, the output of NAND gate
IC3 becomes low, and the LED turns
off. You can calculate the threshold tilt
angle, aT, at which this action occurs
from the equation cosaT5(VREF/VG).
Resistors RS and RR set the voltage
reference to 136.36 mV. Thus, the
threshold tilt angle is 62.968. Similarly,
when the negative voltage at the ZOUT
pin becomes lower in magnitude than
the negative reference voltage, it indicates a tilt of 62.968 or more, the output
of IC2B goes high, and the LED (Reference 3) also turns off. Theoretically,
you can choose any other threshold angle within the interval of 0 to 908. The
practical limits with the 10-nF filtering capacitor, however, are 21.23 and
86.108. The probability of a short-term
false detection is 831025. From the
properties of the cosine function, the
sensitivity of the tilt detector rises with
rising tilt angle. To select another value
of tilt within this interval, you calculate the appropriate reference voltage
from the equation cosaT5(VREF/VG)
and then change the value of the RR
resistors as necessary.
Gravity causes a voltage difference at
the ZOUT pin of IC1. The circuit detects
the detectors
operation is
virtually insensitive
to power-supply
variations.
fall on the loss of this gravity-induced
voltage difference within free fall
moving bodies with no acceleration
other than that provided by gravity. If
the circuit is fixed to such a body while
the Z axis of IC1 is pointing roughly vertically, the free fall manifests itself as almost fully disappearing within the 300or 2300-mV voltage excursion at ZOUT.
When the voltage remains close to the
power supplys midvoltage, the voltage
at ZOUT is 1.5V. The threshold of detecting the free fall in this case is an apparent decrease in gravity to 0.4545g.
The probability that the noises peak
value will achieve this threshold value
is practically zero for heavy bodies.
The probability that the noises peak
value will achieve 0.0679g is fairly low,
and it decreases vastly when you elevate the decision level. An apparent
decrease in gravity within the free fall
causes a low-to-high transition at the
output of either IC2A or IC2B, depending on whether the Z axis is close to
parallel or antiparallel to vertical. The
outputs of both IC2A and IC2B remain
at a high state. Thus, in both orientations, the output of the NAND gate
Reset an SOC
only when power is ready
Goh Ban Hok, Lantiq Asia Pacific Pte Ltd, Singapore
An SOC (system on chip) normally requires two power suppliesone for the core supply and the
other for the I/O. To properly power
up the chip, you need to get one of
the power supplies ready before the
other, according to the SOCs powersequence requirement. Normally, the
core voltage must power up first, and
the I/O voltage powers up second. In-
designideas
parator IC 1 remains inactive until
the I/O voltage activates. When the
I/O voltage turns on, comparator IC1
and AND gate IC2A operate. As the
voltage at IC1s Pin 2 is higher than
that of Pin 3, the comparator produces a high at Pin 7, which pulls up
through R5.
The reset signal at IC2As Pin 1
(Trace C) initially remains at zero and
starts to charge capacitor C1 to the I/O
voltage through R6. Depending on
your application, you can adjust the
RC time constant to suit your needs.
The reset-in signal goes high after C1
charges to the logic-high level, which
produces a logic-high signal at Pin 3
(Trace D), resetting the SOC.
In Figure 3, the I/O voltage (Trace
B) powers up first, and the core voltage (Trace A) follows. The core volt-
3.3V I/O
VOLTAGE
1.8V
CORE
VOLTAGE
R2
5k
5
IC 6
1
LM311N
3
1.65V
1
REFERENCE 4
VOLTAGE
R5
10k
R1
10k
S
A
R4
5k
2
R6
10k
RESET IN
C1
10 F
2
IC2A
3
1 74LS08N
RESET
SOC
S1
edn091022di45521 DIANE
(PLACED IN THE 10-22 FOLDER)
Figure 3 When the core voltage (Trace A) is late, the resetSOC signal (Trace D) remains low.
designideas
Circuit provides simpler
power-supply-sequence testing
VIN
5V
2
1
IC1
ATTINY13
1
PB5/RST
2 PB3
3
PB4
4 GND
TRIGGER
S1
SEQUENCE
S2
OPEN=PS1, PS2
CLOSED=PS2, PS1
VCC
PB2
PB1
PB0
C1
0.1 F
3
8
7
R3
10k
DELAY
PS1 EN
PS2 EN
IC2
TPS75501
IN
EN
GND
OUT
FB
C5
47 F
2
1
3
IC3
TPS75501
IN
EN
GND
OUT
FB
VOUT1
1.5V
4
R4
10k
D1
RED
R5
30k
R8
1k
VOUT2
3.3V
4
5
C6
47 F
R6
50k
R7
30k
D2
GREEN
R9
Figure 1 This circuit needs only an eight-pin microcontroller, an SPST pushbutton switch, an SPST toggle switch, and a
potentiometer to control the sequence delay.
designideas
for an easy enhancement or change in
operation.
The voltage level on Pin 7 of IC1
determines the delay, under firmware
control, between turning on or off the
first and the second power supply. The
microcontroller reads this delay voltage
with its 10-bit ADC and uses the value
to determine the delay according to the
following equation: Delay5(VDELAY/
VCC)3102431 msec, where VDELAY is
the delay voltage. This equation yields
a delay range from a few microseconds
to a bit more than 1 second. As an example, if the delay-voltage value from
R3 is the midwiper value of 2.5V, the
sequencing delay is approximately 512
msec: (2.5/5V)3102431 msec. The
delay value is approximate because the
microcontroller uses its internal 9.6-
MHz RC oscillator to generate the timing with a simple firmware delay loop.
The code in Listing 1 follows the
original Design Idea in that a second press of trigger switch S1 causes
the power supplies to turn off in the
same sequence and with the same
delay with which they turn on. The
listing includes a constant off_sequence that you can change to
change the turn-off sequence with
the second press of S1 (Figure 2). This
constant OFF_sequence is currently sequence_same to operate
as the original Design Idea did, but if
you set the OFF_sequence to sequence_reverse, the turn-off sequence will be in the opposite order of
the turn-on sequence. Alternatively, if
you set the constant off_sequence
TRIGGER
SEQUENCE
PS1_EN
PS2_EN
-- DELAY --
(a)
TRIGGER
SEQUENCE
PS1_EN
PS2_EN
-- DELAY --
(b)
Figure 2 The timing sequence shows the power sequence for S1 (a) and S2 (b).
EDN091203DI4573FIG2
MIKE
positive supply through R6, thus holding Q4 off. During this off condition,
the circuits quiescent-current drain
is 0A.
A 3 to 5V signal at the control terminal turns on Q3, which pulls R7 to 0V,
providing gate drive for Q4. The MOSFET now turns on and sources the load
current, IL, through sense resistor R3 to
the load. If R3s and Q4s on-resistances are smaller than the load resistance,
the magnitude of the supply voltage,
VS, and the load resistance mainly determine the load current.
Under normal load conditions, the
sense voltage developed across R3 is
too small to bias Q1 on; thus, Q1 and
Q2 are both off. If, however, the load
current increases, the voltage across R3
may become large enough to turn on
Q1. At that point, base current flows
through R4 to Q1, and Q1s collector
current in turn provides base current
for Q2. As Q2 turns on, it provides extra
base drive for Q1, and the two transistors rapidly latch in the on-state.
With Q1 saturated, its collector
pulls D2s anode to the positive supply, which clamps Q4s gate voltage to
a diode drop below VS. Without gate
designideas
Q4
drive, the MOSFET turns off,
test circuit using the values
R3
VE SUPPLY
OUTPUT
and IL falls to 0A. With Q1
in Figure 1 trips at a load
and Q2 both latched on, Q4 recurrent of 70 mA. The actual
R4
1k
mains off, which protects the
trip point varies slightly with
R6
Q1
100k
power source from excessive
temperature and depends on
IL
D2
load currents. You can reset
the device you use for Q1,
the circuit breaker simply by
so be prepared to adjust the
R5
taking the control signal low
value of R3 to achieve the deR1
10k
10k
or by cycling the power. The SUPPLY
sired trip current.
VOLTAGE
Create a DAC
from a microcontrollers ADC
Vardan Antonyan, Glendale, CA
designideas
The algorithm can run as a software
loop. You can call it based on another
timer interrupt. To minimize the response time, make sure that this algorithm runs at the desired output value
slightly longer than 2.2RC. You need
the extra time to completely charge
or discharge the capacitor through
resistor R1.
The DACs resolution depends on
several factors, the foremost of which
is ADC resolution. The DACs resolution never exceeds that of the ADC.
Variable selection and timer resolution
also affect DAC resolution. To implement a 10-bit DAC, you need a 16-bit
timer and 16-bit variables for the PID
algorithm. You can use a lower-resolution timer, but you must more frequently call the algorithm. That action results in longer settling times and
higher CPU usage.
By adjusting the algorithms PID
variables, you can achieve surprisingly good output settling times with little change to the DACs output after
settling. The stability of the ADCs
MICROCONTROLLER
DESIRED OUTPUT VALUE
PID
ALGORITHM
ADC MEASUREMENT
ERROR
R1
DAC OUTPUT
C1
HIGH
LOW
Z
I/O
CONTROL
TIMER
DELAY
I/O
TRISTATE
Figure 1 You can develop a PID algorithm to control pulse width and time, thus
creating a DAC from a general-purpose I/O pin. Use the ADC as part of the
feedback loop.
designideas
Edited By Martin Rowe
and Fran Granville
Compact, four-quadrant
lock-in amplifier generates
two analog outputs
D Is Inside
47 Eight-function remote uses
16
5k
1 2.5k
A1
17
VIN
14
2.5k
10k
15
20 A
19
B
13
10k
VOUT 0
7
0 REFERENCE
REF
10
5k
1 2.5k
A2
17
14
2.5k
IC2
AD630
15
20 A
19
B
10
90 REFERENCE 9
VA
VR1
OA1
5V
10k
13
OA3
5V
VOUT 90
VMON
10k
7
VR2
VA
16
OA2
5V
5V
Figure 1 OA1 integrates the bipolar VA signal and creates a triangular wave.
VR1 and VR2 obtain a 908-shifted reference voltage with respect to VA.
VOUT =
designideas
the reference signal. OA1 integrates
the amplifier voltage, which generates
a triangular wave that IC2s comparator compares with the VR2 voltage. You
must regulate VR1 and VR2 to obtain a
perfect 908-shifted command for IC2.
You can monitor the voltage at IC2s
Pin 7. Measurement accuracy and repeatability depend strongly on the RC
time constant of the integrator and the
values of VR1 and VR2.
You can use a different approach
to generate in-phase and in-quadrature reference signals. Figure 2 shows
an all-digital circuit, which you can
implement in a small CPLD (complex programmable-logic device) to
generate the 0 and 908 reference signals in Figure 1. Counter 1 measures
the reference-signal time in terms of
the N number of digital clock pulses,
where the reference time can be different from 50%. It receives a preset
command at the N151 value at each
positive front edge of the reference signal. D-type flip-flop IC1 generates such
pulses. At each positive edge of the
reference signal, IC2 acquires the N/4
value. Meanwhile, Counter 2 counts
the clock periods and receives a restart
an increase in the
number of bits
decreases the
maximum reference frequency.
command at the N251 value when its
value reaches the comparator-measured N/4 quantity.
To overcome the lack of the last
EQ signal when the reference time is
greater than approximately four times
the N/4 integer value, the OR combination of the two RST and EQ pulses
yields four almost-equidistant positive-edge commands in each reference-time period. The N/4 integer division, a logical right shift by 2 bits of
N1, gives a maximum error of three on
the last pulse position. These pulses
generate the in-phase and in-quadrature signals, 0 and 908, respectively,
resulting from simple commutations
on the positive or negative edges of
the signal. T-type flip-flop IC3 generates a signal with twice the frequency
R e fe r e nce
AD630 Balanced Modulator/
Demodulator, Revision E, Analog
Devices, 2004, www.analog.com/
static/imported-files/data_sheets/
AD630.pdf.
1
REF
REFERENCE
VCC
IC1
Q
VCC
COUNTER 1
N-BIT
COUNTER
N2
D
Q1
Q0
RST
N2 N
T Q
IC3
IC2
N2
0 REFERENCE
T Q
90 REFERENCE
VCC
A=B
B
REGISTER
COUNTER 2
T Q
2FREF
4FREF
COMPARATOR
N2
RST
FREF RANGE: 0.66 kHz
60600 Hz
660 Hz
0.66 Hz
(N=15)
VCC
20 MHz
RCI
CLK
2 MHz
RCO
MOD 10
RCI
200 kHz
RCO
MOD 10
RCI
20 kHz
RCO
MOD 10
VCC
VCC
REMOTE
CONTROL
VCC
8 4
R4
1k
16
5
4
6 IC3A
D5
1N4001
D6
1N4001
D7
1N4001
R3
1k
R1
1M
IC1
TLC555
14
2
IC2
4017
4081
4066
1
IC3B 3
4081
10
8 IC3C
LED4
1.8V
2 mA
CLK ENB
8
13
6 5 1 10
C1
4.7 F
LED3
1.8V
2 mA
LED2
1.8V
2 mA
LED1
1.8V
2 mA
R2
15k
7
IC5
4066
3
4081
4081
4066
3
5
4
6 IC3D
4
4081
10
8 IC4A
9
D1
D2
D3
D4
1N4001 1N4001 1N4001 1N4001
LED5
1.8V
2 mA
3.4V
VCC
13
FOUR
AA
BATTERIES
13
4066
10
11
4081
4066
1
3
2 IC4C
LED7
1.8V
2 mA
IC6
4066
8
9
4081
11
12 IC4B
LED6
1.8V
2 mA
4066
8
4081
11
12 IC4D
LED8
1.8V
2 mA
4066
10
11
CH
CH
VOL
VOL
VCR
CABLE
TV
POWER
R5
1k
Figure 1 This interface circuit allows a disabled person to control eight remote-control functions.
DIANE
designideas
Doorbell transformer acts
as simple water-leak detector
Jeff Tregre, www.BuildingUltimateModels.com, Dallas, TX
DOORBELL TRANSFORMER
TO 120V AC
whether it will leak; it is simply a matter of when it will leak. The builders
of new homes in the Midsouth region
of the United States have been installing hot-water heaters in attics. This
approach saves valuable space; how-
D1
D2
16V AC
D4
26V DC
R1
5.1k
S1 NO
WATER PROBES
R4
10k
D3
C1
220 F
35V
PUSH TO TEST
R5
10k
6V DC
2N2222A
R2
10k
2N3906
Q1
Q2
R3
10k
6V PIEZOELECTRIC
SPEAKER
edn090917di45581 DIANE
(PLACED IN THE 10-8 FOLDER)
AUTO-RESET
24V
TIMER
24V
12V
R3
C1
178k
0.1 F
9
1%
16V
R2
IC1C
8
100k
TLV2374 10
1%
D3
1N4148
D4
1N4148
23.5V
R14
10k
1%
23.5V
R7
47k
1%
R9
100k
12V
12.4V REFERENCE
GENERATOR
24V
12.4V
12
IC1D
TLV2374
13
12.4V
R16
345
1%
14
R6
22k
12V 12V
IC2B
TLV2374 5
IC1B
TLV2374 5
D2
1N4148
R5
47k
R4
47k
24V
OPTIONAL
VISUAL
INDICATOR
12V
LED1
R11
1k
C3
6.8 F
16V
TANTALUM
GND
MOTOR
DRIVER
PH1 VS
GND
12V
24V
C2
6.8 F
16V
12V
Q2
FDC5614P
VDD
3
4
IC2A
TLV2374
2
11
24V
1
GND
IC3
2 LM320T-12 3
VI
VO
R12
0.33
1W
24V
2N2907
Q1
12V
R1
10k
1%
24V 24V
R10
0.33
1W
D1
1N4148
R15
10k
1%
R8
100k
23.5V REFERENCE
GENERATOR
24V
R13
435
1%
3
C4
6.8 F
16V
TANTALUM
NOTES:
THE VI PIN CONNECTS TO CIRCUIT GROUND, AND THE GROUND PIN CONNECTS TO THE 24V.
THE 24V REGULATOR GENERATES 12V REFERENCED TO 24V.
VDD
Q3
FDC5614P
4
IC1A
TLV2374
11
MOTOR
DRIVER
PH2 VS
GND
12V
Figure 1 Current-sense resistors turn off MOSFETs when current through them exceeds a limit.
designideas
input amplifier and brings up the question of how to respond to an overcurrent. The differential amp produces a
low ground-referenced signal from a
high-side event, but you can prevent a
high-side overcurrent resulting from a
short to ground only by turning off the
high-side power. In effect, the differential amp translates the high-side signal
into the low-side domain in which you
must then translate the response back
into the high-side domain.
A simpler approach for any high-side
overcurrent-protection circuit references the entire circuit to the high-side
rail. Such circuits typically consume
little power, which a small, three-ter-
Debug a microcontroller-to-FPGA
interface from the FPGA side
data-capture circuit, the JTAG communication circuit, and the GUI (graphical user interface). The data-capture
circuit uses standard HDL (hardwaredescription language) and instantiates
Bibo Yang, Sunrise Telecom, Beijing, China
a FIFO (first-in/first-out) buffer in the
Microcontrollers and FPGAs write transactions on the microcon- FPGA. Whenever you read or write to
often work together in embed- troller/FPGA interface. This method a register, the debugging tool records
ded systems. As more functions move is nonintrusive because the circuit that the corresponding value of the address
into the FPGA, however, debugging captures transactions sits between the and data on the bus and stores it in the
the interface between the two devices microcontroller and the FPGAs func- FIFO buffer. You can retrieve the data
becomes more difficult. The tradition- tioning logic and monitors the data through the JTAGs download cable to
al debugging approach comes from the without interfering with it. It stores the PC (Listing 1, which is available
microcontroller side, which relies on the captured transaction in the FPGAs in the online version of this Design
a serial-port printout. This approach RAM resources in real time. You can Idea at www.edn.com/091215dia).
adds overhead and may cause timing transfer the data to a PC through the
Because the FPGA has limited onproblems. Furthermore, this approach JTAG ports download cable.
chip RAM resources, you must keep
cannot guarantee uninterrupted and
The debugging tool comprises the the FIFO buffer shallow. To efficientexclusive access to cerly use the FIFO buffer,
tain addresses because
the design includes filter
of operating-system
and trigger circuits. With
TRANSACTION
multitasking. Thus,
inclusive address filterFILTER
a serial-port printout
ing, the circuit monitors
FROM JTAG
TRANSACTIONdoesnt accurately deonly several discontinuTRANSACTIONCAPTURING
CAPTURING
scribe the actions on
ous spans of addresses
LOGIC WITH
FIFO BUFFER
FILTER AND
the microcontroller/
instead of the whole adTO JTAG
TRIGGER
FPGA interface.
dress space. Exclusive-adTRANSACTION
Instead, you can apdress filters can filter out
TRIGGER
FROM JTAG
proach the problem
several smaller address
from the FPGA side
spans from the inclusiveusing a JTAG (Joint
address spans, enabling
up_addr up_data up_cs up_wr up_rd
Test Action Group)
finer control of the filter
FROM MICROCONTROLLER
interface as a commusettings (Listing 2, which
nication port. This apis also available in the onproach uses the interline version of this Design
Figure 1 The JTAGs vendor-supplied, customizable communinal logic of the FPGA
Idea at www.edn.com/
cation circuit has two interfaces.
to capture the read/
091215dia).
edn091112di45601 DIANE
(PLACED IN THE 11-26 FOLDER)
designideas
With transaction triggering, the circuit starts when you read from or write
to a certain address. You can add certain data values to the triggering condition (Listing 3, which is available in
the online version of this Design Idea
at www.edn.com/091215dia). You can
dynamically reconfigure the settings of
address filters and transaction triggers
through the JTAGs vendor-supplied,
customizable communication circuit
without recompilation of the FPGA
design (Figure 1). The circuit has
two interfaces, one of which is written
in HDL to form a customized JTAG
chain. It communicates with the user
logic (listings 1, 2, and 3). The circuit is accessible through specific programming interfaces on the PC and
communicates with the user program
or GUI (Listing 4, which is available
in the online version of this Design
Idea at www.edn.com/091215dia).
The FPGA-based circuit facilitates
writing and reading functions from PC
to FPGA logic, and it promotes the