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D Is Inside
66 High-speed clamp functions
VCC
C1
100 nF
R2
1k
1
GP3/MCLR
GP0/AN0
GND
GP1/AN1
IC1
PIC10F222
VDD
GP2/T0CK1
D1
LED
4
R1
1M
Q1
2N7002
Figure 1 Adding a MOSFET and associated circuitry to a PIC microcontrollers MCLR input pin transforms the pin into an output.
edn071025di41541
as pulse-forming circuit
68 Depletion-mode MOSFET
DIANE
designideas
High-speed clamp functions
as pulse-forming circuit
Marin tofka, Slovak University of Technology, Bratislava, Slovakia
Amplifiers with positive feed old shifts to a higher value before the
back are the bases of signal- positive-output transition, and it shifts
grade pulse-forming circuits. This to a lower value after switching to the
setup ensures a triggerlike operation positive-output level. You can set the
in which the input signal crosses the amount of hysteresisfrom zero to
input-threshold level; in most cases, latch-upfor Schmitt-trigger circuits
the input signal is a voltage signal. The comprising discrete parts. Schmitt
most well-known of these triggers is the circuits find wide use in logic ICs, in
Schmitt trigger, which, by the way, will which the hysteresis is rather high and
this year celebrate
its 70thEDN071025DI4156
birthday. fixed.
STEVE
FIGURE 1
British scientist OH Schmitt in 1938
As an alternative, you can use a cir
originated the Schmitt trigger in the cuita fast-response voltage limiter,
form of a two-stage amplifier with cur or clamperas a pulse-forming cir
rent feedback. The two active devices cuit. The input-voltage range is nar
were vacuum tubes.
rower than that of Schmitt-trigger cir
The operation of a Schmitt trigger cuits, because, at low input voltages,
has the advantage of fast, almost-con the voltage limitation becomes inac
stant transition times of the output re tive, and the circuit operates as a lin
gardless of the slope of the input signal. ear amplifier. On the other hand, be
One consequence of this type of opera cause of its nonhysteretic behavior, the
tion is the hysteresis in the I/O char decision threshold of the input voltage
acteristic. In other words, the thresh is precise and equal for both directions
AD8045
HSMS-282L
IC2
D3
RT2
180 D4
D2
D1
VS
IN
RI
330
2
3
RT1
180
1
6
IC1 FB
4
OUT
100 nF
47 nF
VS
CI
1.2 pF
RI
IC1
NOTES:
ALL COMPONENTS ARE SMD.
ALL EXPERIMENTS WERE PERFORMED
FOR ASYMMETRIC CONFIGURATION WITH D4
SHORTED AND RT2 OMITTED.
FOR SYMMETRIC CONFIGURATION, USE THE IC2
HAVING A SUFFIX R (RING-QUAD DIODES);
EVENTUALLY, USE P (BRIDGE-QUAD DIODES) INSTEAD
OF L AND COMPLETE THE CIRCUIT WITH D4
AND RT2 AS DEPICTED.
Figure 1 This clamping circuit uses diodes to achieve nonlinear feedback. The
circuit employs a single diode in one feedback path and two diodes in the
other. The dual-diode configuration offers cleaner switching.
designideas
Depletion-mode MOSFET
kick-starts power supply
Gregory Mirsky, Milavia International, Buffalo Grove, IL
L
D1
FDLL4148
RECTIFIER
LINE
FILTER
GBU-608
D4
CSD06060G
D2
FDLL4148
D3
FDLL4148
C2
20 F
35V
VCC
IC1
PFC
GATE
CONTROLLER
R5
100k
R1
100k
420V
C1
1 F
GND
C3
0.1 F
R2
10
Q1
STP11NM60FD
R3
1M
Q2
DN2470
C4
470 F
450V
Q3
CMPT2222A
D5
BZX84C15LT1
SETS
R4
INITIAL
6.2M CURRENT
Figure 1 A depletion-mode, high-voltage MOSFET provides a kick-start for a PFC IC. During normal operation, the MOSFET
switches off and dissipates negligible power.
designideas
Simple continuity tester
fits into shirt pocket
Tom Wason, Phoenixville, PA
This
TextDesign Idea describes a
handy continuity tester with
two modes of operation: It may sound
if it detects continuity between its two
probes, or it may sound when it de
tects no continuity. The second option
permits testing for intermittent cable
breaks. Response must be sufficiently
fast to permit swiping a probe across
perhaps 100 pins to instantly find a
connected pin. The tester may also
identify microfarad or larger capaci
tance between two conductors.
To properly test for continuity, the
testers voltage and current are limited
so that low-power semiconductors do
not suffer overstress or appear as a con
nection between two conductors. The
tester must protect itself if you acciden
tally connect it across an energized cir
cuit or a charged capacitor. Power con
sumption must be low so that if you
accidentally leave the tester on over
night, it will not discharge the battery.
The tester must operate even with low
battery voltage.
Continuity requires a threshold of
less than 200V. Depending on bat
tery voltage, that threshold may even
B1
9V
R1
5.6k
R4
680k
R5
1M
R6
1M
C2
0.01 F
S2
Q5
BS170
Q1
RED
PROBE
BLACK
D3
1N4003
R3
1k
W
D1
1N5819
2N5087
R2
330
SOUND
Q4
BS170
D2
1N5819
Q3
BS170
Q2
C1
0.1 F
D5
1N4003
2N5089
D4
1N4003
DIANE
designideas
White LED shines
from piezoelectric-oscillator supply
TA Babu, Chennai, India
edn071203di41781
DIANE
designideas
Edited By Charles H Small
and Fran Granville
D Is Inside
62 8-bit microcontroller
Raw range
Normalized
range
0 to 0.189
Raw
Normalized
0 to 0.2855
0.1427
0.189 to 0.265
0.2855 to
0.4003
0.3429
1000
0.5333
0.265 to 0.378
0.4003 to
0.571
0.4856
1100
0.8
0.378 to 0.662
0.571 to 1
0.7855
1110
0.933
1111
designideas
R16
1000k
3
R1
15.625
R2
7.8125
R3
15.625
R4
31.25
R26
62.5
C3
10 nF
IC1
LTC1150
2
R13
6 100k
LSB
IC6
LTC1150
3
R15
1000k
3
R5
62.5
R6
15.625
R7
15.625
R8
62.5
R27
125
C1
10 nF
IC2
LTC1150
2
R14
6 100k
IC4
LTC1150
3
R18
1000k
3
R9
250
R10
31.25
R11
31.25
R12
62.5
R28
250
C2
10 nF
IC3
LTC1150
2
R17
6 100k
IC5
LTC1150
3
R20
1000k
3
R21
1000
V1
1V
R22
62.5
R23
62.5
R24
125
R25
250
C4
10 nF
IC7
LTC1150
2
R19
6 100k
MSB
IC8
LTC1150
2
1
2
Figure 1 This Hopfield neural ADC provides a robust output in the presence of noise.
stant. For bit-pattern readout reversals, you can have the curve equation
Y5A3(X2B)C and the complementary-curve equation Y512A3(X2B)C.
Figure 1 shows a 4-bit neural ADC
employing voltage inverters that comparators feed. The comparators connect with their positive terminals
joined to input nodes and with their
negative terminals grounded. The bases of this network are inverse factors
of one-halfthat is, reciprocal factors of twoinput-node conductances
SIJ52132(22I2J), where the 21 factor
comes from negative feedback through
the related resistor; SIR52(1223I); and
SIS52(12I). To determine node resistances, choose a maximum node resistance of 1000V corresponding to a
minimum conductance of 0.0078125,
and a minimum node resistance of
7.8125V corresponding to a maximum
conductance of one. Calculate all oth-
normalized graph by reversing the bitorder readout from the circuit so that
the resulting curve equation would be:
Y51.62433(X20.1427)3.1508.
Without analog-input-voltage transformation, such as the use of look-up
tables or logarithmic amplifiers to process the input voltage, or digital corrective logic, digital responses from
simple Hopfield neural converters
are nonlinear and crude. However,
these responses are still possibly useful for such applications as associative
memory and pattern classification because of robustness in output precision.
Indeed, because of output digital
stability, the Hopfield neural converter can allow for unwanted analog-input-signal noisiness or variations. This
scenario is in strong contrast to conventional interface circuits between
analog-transmission media and digital-
designideas
computing machines. This Design Idea
shows that flexible circuit adaptability
can exist in producing various forms
of stable digital outputs from neural
R1
15.625
R2
7.8125
R3
15.625
R4
31.25
R19
62.5
C3
10 nF
IC1
6
LTC1150
3
IC4
LTC1150
2
6
R22 R13
900k 100k
2
R5
62.5
R6
15.625
R7
15.625
R8
62.5
R20
125
C1
10 nF
IC2
6
LTC1150
3
IC6
LTC1150
2
6
R24 R23
900k 100k
2
R9
250
R10
31.25
R11
31.25
R12
62.5
R21
250
C2
10 nF
IC3
6
LTC1150
3
2
R14
1000
V1
1V
R15
62.5
R16
62.5
R17
125
R18
250
C4
10 nF
IC7
LTC1150
2
6
R26 R25
900k 100k
MSB
IC5
6
LTC1150
3
IC8
LTC1150
2
6
R28 R27
900k 100k
1
2
Figure 2 This version of the Hopfield neural ADC features inverted bit outputs.
designideas
Leaving aside the sophisticated design methods based on Z transformation
with its extensive math, this idea uses
another approach based on a recursive
equation. You calculate each output-signal sample as the sum of the input signal and the previous output signal with
corresponding coefficients. A recursive
equation defines a single-pole lowpass
filter as: Y[n]5X[n]3a01Y[n21]3b1,
where X[n] and Y[n] are input and output values of sample [n], Y[n-1] is an
output value of the previous sample
[n21], and a0 and b1 are weight coefficients that decrement d controls. The
coefficients have the value of 0,d,1,
a0512d, and b15d. Physically, d is
the amount of decay between adjacent
output samples when the input signal
drops from a high level to a low level.
You can directly specify the value of d
or find it from the desired time constant of the filter, d, which is the number of samples it takes the output to rise
to 63.2% of the steady-state level for a
lowpass filter. A fixed relationship exists between d and d: d5e21/d, where e
is the base of natural logarithms. The
preceding equations yield Y[n]5Y[n2
1]1(12d)3(X[n]2Y[n21]).
Numerically
performing the
filtering function
provides the benefit
of consistency
because component
tolerances, temperature drift, and aging
do not affect the
filters algorithm.
Instead of multiplying a decimal-point
number, 12d, it is more convenient
for assembler programming to divide
by the reciprocal integer, F51/(12d):
Y[n]5Y[n21]1(X[n]2Y[n21])/
F. Thus, you can determine the digital
filters parameters using the following
steps:
1. Choose the parameter F. For assembler, it is convenient to perform division as right shifts. For right shifts, the
value of F should be 2S, where S is the
number of shifts. Let F equal 8, which
you reach after three right shifts.
designideas
with a drain-to-source voltage (VDS)
of 30V120V (zener diode D1 voltage), has an on-resistance of 95 mV at
a gate-to-source voltage of 2.5V, and
comes in a thermally efficient SC706 package. For some applications, the
regulators output voltage may be insufficient to fully turn on the selected protection MOSFET, so you can increase
the bootstrap voltage with a separate
zener reference, as the LM2734Zs data
sheet shows (Reference 1).EDN
RF2
10k
PORT
D4
SI1470DN
R1
510k
D1
20V
MM3Z20VT1
Q1
5
C5
10 nF
6.3V
C1
2.2 F
25V
BOOST
EN
PIN 1
PIN 3
FB
VIN
D3
D4
BAT54SWT1
1
CB
10 nF
IC1
LM2734Z
4
RF1
25k
PIN 2
VBATTERY
8 TO 50V
R e fe r e nce
1
SW
GND
D2
MBR0530
VOUT
2.8V AT
400 mA
L1
4.7 H
C2
1 F
6.3V
PORT
Figure 1 The N-channel MOSFET and zener diode protect the switching regulator against transient voltages as high as
50V in automotive applications.
edn071108di41621
DIANE
designideas
Edited By Charles H Small
and Fran Granville
D Is Inside
62 Isolated supply powers
DVM module
RTDs (resistance-temperature
detectors) are the preferred sensor choices for designs requiring precision. Although RTDs are approximately linear over the limited temperature
range of 0 to 1008C, these sensors exhibit a slight but progressively more
nonlinear temperature-versus-resistance characteristic as the measurement range widens. Consequently, over
an extended span, curve fitting is necessary if the system is to achieve a high
level of precision. One way to obviate
the nonlinear characteristic of an RTD
sensor is to design analog hardware to
VREF
2.5V
15V
R1
68k
5%
0.1 F
R3
1k
1
OFFSET
TRIM
C1
0.22 F
R2
20k
R4
560
5%
R5
75k
IC1
400-A 6
5 REF200
15V 15V
15V
4 7 8
VT
0.1 F
R6
18.7k
8
5
1 X VS VS
1
2 X
2
7
IC3
3 Y AD633JN W
1
6
4 Y
Z
0.1 F
GAIN
TRIM
3
RS
TM
0 TO 350C
VS(400 A)RS.
7
IC2
6
QP177
3
4
0.1 F
R7
10k
VO 10 mV TM.
C
T1
R8
1.74k
15V
VT75VS3V.
NOTES:
RS IS A PLATINUM, 100-AT-0C RTD,
WITH OF 0.00385//C.
ALL RESISTORS ARE METAL-FILM,
1%-TOLERANCE UNLESS
OTHERWISE NOTED.
0.1 F
OPTIONAL CIRCUITRY
TO ADD OFFSET
VOLTAGE OF 0.0005V.
R10
12.35M
VREF
2.5V
R9
10k
VO0.0005V0.8507VT0.0123VT2.
Figure 1 This RTD circuit uses a second-order polynomial to linearize the output of the sensor.
designideas
Table 1 Excel-spreadsheet data
0.00392V/V/8C and follow the
Equations
for
DI
4151
for
11
8
US curve. The circuit in Figure
Measured
RS
temperaVS
VT
VO
1 uses a standard RTD to measure
ture (8C)
(V)
(V)
(V)
(V)
temperature over the extended
range of 0 to 3508C, an output
0
100
0.04
0
0
voltage
of 0 to1 3.5V, and overEquation
25
109.73
0.0439
0.292
0.25
all system accuracy greater than
50
119.4
0.0479
0.582
0.5
0.58C. The following linear equa75
128.99
0.0516
0.87
0.75
tion expresses this sensor system:
10 mV
VO
T .
C M
6 + R 7(Reference
second-order
1). Also, driving the RTD with a
current source preserves its intrinsic nonlinearity and allows you to
express the sensors output voltage, VS, as: 400 mA3RS, where RS is
the resistance of the sensor.
IC2 initially signal-conditions the
sensors output by first scaling the output voltage and then offsetting the result so that VT is slightly larger than
the 3.5V output at 3508C and that VT
equals 0V at 08C. Adding gain and offset before linearization places less of a
burden on the curve-fitting circuitry
and helps to meet the systems precision specification. The combination of
C1 and R5 implements a lowpass filter
with a pole at approximately 10 Hz to
remove power-supply noise. The following term describes the performance
of IC2 and its accompanying circuitry:
VT575VS23V.
Next, an Excel spreadsheet creates
the nonlinear-mathematical relationship between the voltage, VT, and
the system output, VO (Table 1). The
spreadsheet features 17 temperature
entriesstarting at 08C, increasing
in increments of 258C, and ending at
4008Cfor the measured temperature.
Using a data set that extends beyond
the intended measurement range of
3508C can reduce end errors in nonlinear systems. Values for RSwhich
you derive from a standard RTD-resistance-versus-temperature tableand
designand then use the preceding equation to find the value for R6.
Resistors R8, R9, and, optionally, R10 form a passive adder to
create the offset term, a, and the
linear coefficient, b. You apply
the output of the passive adder
directly to the Z input, Pin 6 of
IC3, which adds the offset and
100
138.51
0.0554
1.155
1
linear terms to the square term
125
147.95
0.0592
1.439 1.25
to form the system response at
150
157.33
0.0629
1.72
1.5
Pin 7. Again comparing these
terms, note that the offset term
175
166.62
0.0666 1.999 1.75
must equal 0.0005V. The offset
200
175.86
0.0703
2.276
2
term is only 0.5 mV, and elimi225
185.01
0.074
2.55
2.25
nating it would add an error of
250
194.1
0.0776
2.823
2.5
approximately 0.058C, so you
can initially neglect it. Then,
275
203.1
0.0812
3.093 2.75
because the linear terms coeffi300
212.05
0.0848 3.362
3
cient, b, must equal 0.8507, you
325
220.91
0.0884
3.627
3.25
first select a suitable value for R9
350
229.72
0.0919
3.892
3.5
and use the following equation
to solve for R8: b5R9/(R81R9).
375
238.88
0.0956 4.166 3.75
If you wish to design the op400
247.09
0.0988 4.413
4
tional circuitry and include the
the equations allow you to compute VS offset term, which is part of the passive
and VT. The VT and VO columns are the adder, choose a stable 2.5V reference
input and output signals, respectively, for VREF, calculate the parallel combifor the linearization circuitry; you chart nation of R8//R95REQ (the equivalent
them using Excels XY-scatter feature. resistance of R8 in parallel with R9),
You can use Excels Trendline feature and solve for R10 using the following
to create the following equation, the voltage-divider equation: a5(REQ/
mathematical representation of the (R9+REQ))VREF.
curve-fitting circuitry you need to linTo calibrate this circuit, replace the
earize the sensors output: VO50.0005V sensor with a precision decade box. Set
Equations
for DI4151
for 11
8 the decade box to simulate 08C and ad2
10.8597V
10.0123V
. IC
and
T
T
3
four 1%-tolerant resistors or, option- just the offset trim of R2 for an output
ally, five resistors implement a sec- of 0V at Pin 7 of IC3. Next, set the deond-order polynomial: VO5a1bVT cade box to simulate 3508C and ad1cVT2,Equation
where a 1is the offset term, b just the gain trim of R3 for an output
is the linear coefficient, and c is the of 3.5V. Repeat this sequence of trim
square-term coefficient.
steps until both points are fixed. The
The curve-fitting-circuit design be- circuit in Figure 1which includes
gins by first wiring
10 mVthe
four inputs of optional circuitryexhibits a worstT .
O a positive
IC3 to V
create
C M square term case measurement error at 2508C and
that is scaled at the chips output by 2.504V of 0.16%, or 0.48C. Testing
an internal scale factor of 110V. Then, the circuit without the optional circomparing terms, you find that the co- cuitrythe reference voltage and R10
efficient, c, must equal 0.0123. Because shows no discernible improvement
ion a2 voltage divider that in precision.EDN
R6 and Equat
R7 form
attenuates the signal, VT, you can express the coefficient with the following R e f e r e n c e
1 IC Generates Second-Order
equation:
2
c=
1 R7
.
10 R 6 + R7
designideas
Isolated supply powers DVM module
Richard Dunipace, Fairchild Semiconductor, Irving, TX
Low-cost DVM (digital-volt- applications requiring low-input-voltmeter) modules are economi- age operation.
cal and can significantly reduce deThe power-supply design in Figure 1
sign time for instrumentation. Yet, is a blocking oscillator that operates as
these modules also involve a signifi- a flyback converter with fixed on-time
cant number of design challenges. For and variable off-time. The variable
example, their inputs are not isolated off-time regulates how often the transfrom the power supply, so you must former charges and delivers power to
add an isolated power supply. This the load. The blocking oscillator contask can both consume critical design sists of NPN transistor Q2, transformer
time and add to system costs.
0.7 TO
Additionally, many uses for
C
15V 0.1 6F
IC1
the modules require one- to
FOD2741C
50V
four-cell-battery operation,
2
C
IC1
5
+
and the modules require ap22 F
FOD2741C
proximately 9V, translating
D2
MMBT5087
10V
3
MMBD4148
T
to operation from 0.7 to 6V
1 1
Q1
10
if you use new batteries until
R2
D1
R3
7
R1
390
MMBD4148
4
they are fully discharged. This
5.6k
100k
5
wide input range also means
R4
2
9V
27k
C3
that you should regulate the
6
Q2
AT
22 F
C4
11
power-supply output.
10 mA
10V
KSD1621STF
8
0.1 F
DVM modules also have
50V
7
low parts count, and you can
C1
R5
6
5
0.1 F
10k
implement them using off-the3
50V
ERROR
shelf components. Optionally,
12
AMPLIFIER
C2
9
the modules can operate with
0.0022 F
50V
input voltages as low as 0.25V
if you replace the silicon tranNOTE:
sistors with germanium deT1=COILTRONICS VP1-1400.
vices. However, germanium
transistors are relatively ex- Figure 1 This isolated flyback supply powers a digital-voltmeter module from 0.7 to 15V.
pensive, so use them only in
edn071203di41661
before
you can apply the reset, or acDIANE
tive low. The circuit in Figure 1 proves
useful during power-up when there is
no need to press the reset button once
the device powers up, because reset occurs automatically with the predetermined hold time before you apply the
reset-low signal.
The circuit employs a reset-supervisory chip with the MR pin and active-low output, RESET. Normally, the
MR input has an internal pullup resistor with a value of 20 to 50 kV. During power-up, this MR internal resistor
charges up capacitor C1 to the maxi-
designideas
mum value to VDD at the positive side.
To create an MR reset input to the supervisory chip, its MR input must receive an active-low ground signal, requiring transistor Q1 to turn on. The
turn-on-time period depends on the
RC-time constant of R1 and C2. These
two components determine when Q1
turns on and thus provide an adjustable
hold time for the RESET output to
hold high. To increase the hold time,
simply increase the RC-time constant
of R1 and C2.
The supervisory reset chip asserts its
RESET output only when the voltage
at the MR pin exceeds the thresholdtrigger voltage and the supervisors internal reset period has elapsed. This
time-out period filters any short inputvoltage transients. Because of Q1s turnon, the negative side of C1 becomes
grounded. Because the positive side of
C1 cannot instantly change its polarity, it pulls low and slowly charges up
again through the internal pullup resistor of the MR input. When it reaches
the threshold voltage of the reset chip,
it then asserts the reset once it reaches
VDD
OPTIONAL
PUSHBUTTON
R1
100k
R2
C1
100k 10 F
Q1
2N2222
C2
47 F
R3
2.2k
VCC
RESET
MAX6805
OPEN-DRAIN
OUTPUT
GND
MR
RESET
D1
designideas
dimming with 7V at 74-mA current
and are fully on with 8.5V at 1 mA, remaining off for a 5V supply at 1.53 mA.
To turn on the LEDs, you must configure the microcontrollers I/O pin as
an output; an output value of one turns
VCC
3.3V
D1
TS4148
LED1
KP-2012
MICROCONTROLLERI/O PIN
R
D1
BZX84-C3V0
MICROCONTROLLERI/O PIN R
LED2
KP-2012
LED1
KP-2012
LED2
KP-2012
D2
BZX84-C3V0
D2
TS4148
(a)
(b)
edn071122di41711
DIANE
designideas
Edited By Charles H Small
and Fran Granville
D Is Inside
In 1971,STEVE
Signeticslater
Phil- thirds of VFIGURE
, the 555s
CC
EDN071214DI4185
1 internal disips (www.philips.com)intro- charge transistor opens, and the voltage
duced the NE555 timer, and manu- on C1 returns to one-third the voltage
facturers are still producing more than of VCC, the lower comparator thresh1 billion of them a year. By adding a old. At one-third this voltage, the disfew components to the NE555, you charge transistor switches off, and C1
can build a simple voltage-to-frequen- again starts charging. The NE555s
cy converter for less than 50 cents. output is high while C1 is charging
The circuit contains a Miller integra- and low while C1 is discharging. The
tor based on a TL071 along with an product of the input voltage and the
NE555 timer (Figure 1). The input charging time of C1 is constant. Bevoltage in this application ranges from cause the discharge time is shorter than
0 to 210V, yielding an output-frequen- the charging time, the following equacy range of 0 to 1000 Hz. The current tion results for the output frequency:
of C1 is the function of input voltage: fOUT;VIN/(P11R1)3C131/3VCC.
IC52VIN/(P11R1).
P1 calibrates the relationship beAs the voltage on C1 reaches two- tween the output frequency and the
76 Optoisolators compute
78 Single-supply circuit measures
RESET
quency in the middle
4.7 nF
2/
3
P1
VCC
TH 6
of the input-voltage
220k R1
range at 25V, then
7
270k
CONTROL
2
LOWER
VIN
5k
the conversion error
FLIP-FLOP
COMPARATOR
IC
6
1
0 TO 10V
TL071
will be less than 1.3%
3
1/
3
over the entire range.
VCC
4
TL 2
To improve perforfOUT
7
Q1
mance, C 1 should
OUTPUT
3
POWER
have a low dissipation
C
5k
15V
2
OUTPUT
factor. You can dimin100 nF
ish temperature de1
pendence if R1 has a
low temperature coefficient and P1 is a mulFigure 1 Preceding an NE555 timer with a Miller integrator yields a voltage-to-frequency
titurn, ceramic-metal
converter that costs less than 50 cents.
potentiometer.EDN
designideas
Optoisolators compute watts
and volt-amperes
bridge for the ac excitation of the lefthand side. The analog product of instantaneous load current times the average voltage optically couples to phototransistor Q4/D4, which A2 amplifies
and the Q5 through Q8 transistor array
rectifies to provide an analog voltage
proportional to load volt-amperes.EDN
D1
D2
4
IZL
D3
PS2501-4
6
D4
ZL
R2
0.001
NEUTRAL
15V
COPPER
SHUNT
15
POWER
1300W
Q1
16
14
Q2
13
12
R3
5.1k
15V
Q3
11
Q4
10
R4
5.1k
SPAN
R5
200k
R6
30k
C1
4.7 F
16V
10k
T1
ZERO
OUT
1V
100W
15V
7
A1
OP27
3
15V
DIANE
120V AC 60 Hz IN
CALIBRATE
2N3906
VA
OUTPUT
1V100 VA
4.7 F
16V
2N3906
4.7 F
16V
CW 500k
Q5
2N3906
10k
15V
Q6
5.1k
2
A2
3
4
7
4.7 F
10
16V
Q4
7
8
D4
4.7 F
16V
D5
1N4004
0.001
COPPER
SHUNT
D2
1
2
16
Q1
WATTS CALIBRATE
15
5.1k
CW
0W
500k
10k
3
4
14
Q2
13
2
5.1k
Q8
100k
D1
15V 4.7 F
16V
7
6
A
2N3906
Q7
15V
PS2501-4
12
6
Q3
D3
5
11
5.1k
15V
WATTS OUTPUT
1V100W
15V
15V
15V
120V AC 60Hz OUT TO LOAD
Figure 2 The right-hand side of this circuit is simply a half-wave version of the circuit in Figure 1. The left-hand side is similar but substitutes rectified-dc excitation of its half-wave bridge for the ac excitation of the right-hand circuit.
edn071108di41572
DIANE
designideas
Single-supply circuit measures
248V high-side current
The nominal 248V rail, which has a fixed gain of one, so the output
finds wide use in wireless base voltage is I3RS1VREF. The AD8603
stations and other telecommunications functions as a subtractor so that it can
equipment in network central offices, reject the common-mode voltage, VREF,
can vary from 248 to 260V. Measuring and apply gain to the signal of interest,
its current draw typically requires com- I3RS. A factor of 20 amplifies the sigponents that operate on 615V dual sup- nal to span the 2.5V full-scale range of R e f e r e n c e s
1 High Common-Mode Voltage,
plies. Eliminating the negative supply the ADC.
would reduce system complexity and
This Design Idea uses the AD8603 Difference Amplifier AD629, Analog
cost. This Design Idea uses an AD629 because it has low input-bias current Devices, 1999 to 2007, www.analog.
difference amplifier and an AD8603 and low offset drift. In addition, the com/UploadedFiles/Data_Sheets/
operational amplifier, both from An- rail-to-rail output allows it to share the AD629.pdf.
alog Devices (www.analog.com), to same supply as the ADC. In this stage, 2 Precision Micropower, Low Noise
measure current at 248 to 260V and the subtractor rejects the 5V common- CMOS Rail-to-Rail Input/Output
operates from a single positive-power mode signal from the voltage refer- Operational Amplifiers AD8603/
supply (references 1 and 2).
ence. The four resistors that form the AD8607/AD8609, Analog Devices,
Figure 1 shows how the AD629 subtractor must have matched ratios 2005, www.analog.com/Uploaded
and AD8603 measure current in the to obtain maximum common-mode Files/Data_Sheets/AD8603_8607_
presence of a 248V common-mode rejection. If you cannot obtain tight- 8609.pdf.
voltage. The following equations demonstrate how the
200k
12V
CURRENT
AD629 difference amplifier
I
VREFIRS
5V
can condition voltages beyond
VS
20IRS
10k
its supply ranges: VCOM_MAX5
VCOM
V
AD629
RS
GAIN=20
48V~60V
203(VS21.2)2193VREF, and
R
REFERENCE
ADC
AD8603
PINS 1
V COM_MIN5203(2V S11.2)2
VS AND 5
C
V
193VREF. With a 5V reference,
10k
SUCCESSIVEthe common-mode input range
APPROXIMATIONREGISTER
ADC
5V
is 271 to 1121V. The current,
0 TO 2.5V INPUT RANGE
I, flows through the shunt re200k
sistor, RS, causing a differential
voltage, which the difference Figure 1 The AD629 and AD8603 measure current in the presence of 248V commonamplifier senses. The AD629 mode voltages.
edn071203di41831
DIANE
DDR bit=0
DDR bit=0
Port bit=0
Port bit=1
Pin bit=1
Pin bit=1
Pin bit=0
Pin bit=0
Pin connects to
ground through a veryhigh-resistance path
Pin bit=0
Pin bit=1
designideas
1
PC6(RESET)
22 AGND
21
AREF
PC0(ADC0)
PC1(ADC1) 24
25
PC2(ADC2)
26
PC3(ADC3)
27
PC4(ADC4/SDA)
28
PC5(ADC5/SCL)
20 AVCC
9
10
5V
8
7
23
PB6(XTAL1/TOSC1)
PD0(RXD)
PD1(TXD)
IC1
PD2(INT0)
MEGA8
PD3(INT1)
PD4(XCK/T0)
PD5(T1)
PD6(AIN0)
PD7(AIN1)
PB7(XTAL2/TOSC2)
GND
VCC
PB0(ICP)
PB1(OC1A)
PB2(SS/OC1B)
PB3(MOSI/OC2)
PB4(MISO)
PB5(SCK)
2
3
4
5
6
11
12
13
LED1
R2
330
LED2
R3
330
LED3
R4
330
14
15
16
17
18
19
S2
R5
1k
2
3
R1
330k
designideas
pF. Thus, a standard mains-test lead,
whose typical lead-to-lead capacitance is 200 pF, would test OK. The
circuit is also immune to false triggering that the 60-Hz pickup from the
power lines causes. Because the typical current draw of this low-power circuit is less than 40 mA, the circuit can
D1
ON/OFF
IN
IC1
2 IN
R2
1M
C1
100 nF
C2
470 pF
C4
100 nF
MAX9022
R3
100k
standard ceramic decoupling capacitors, and the circuit contains no critical passive components. The comparators high-side drive is somewhat better than its low-side drive, so it should
source rather than sink current to the
indicator device. D1, D2, and D3 are
silicon diodes.EDN
C3
100 nF
VDD/2
R1
1M
3
THREE
AA OR AAA
BATTERY
CELLS
1
R4
100
D2
D3
C5
100 nF
TO CABLE
UNDER TEST
8
MAX9022
VDD
7
IC1 V
SS
6
IN
4
VDD/2
R5
1M
IN
PIEZOELECTRIC
BUZZER
Figure 1 Based on a low-power dual comparator, this ac-continuity tester locates open-circuit pins in a cable.
edn071203di41821
DIANE
designideas
Edited By Charles H Small
and Fran Granville
D Is Inside
as light sensors
To discover potential power- the sense resistor equals the positivesupply problems, you must run input voltage. The voltage across the
dynamic and static tests. This simple sense resistor is proportional to the
current sink tests low- to medium- load current from the power supply unpower supplies and voltage sources. In der test and is independent of its outthis application, the current sink can put voltage. Q1 features a maximum
draw current of 0 to 1.5A for an input- current of 14A at a case temperature
voltage range of 0 to 5V with a sup- of 258C with drain-to-source voltage
ply voltage as high as 20V. The basis of 100V, low gate charge, and maxiof the circuit is precision op-amp IC1, mum on-resistance of 0.16V at a gatean OPA277 from Texas Instruments to-source voltage of 10V and a drain
STEVE
FIGURE 1
(www.ti.com), which
featuresEDN071214DI4187
a maxi- current of 7A.
mum input-offset voltage of only 100
The MOSFET can dissipate a finite
mV, maximum input-bias current of 4 amount of maximum powerto 30W
nA, and low drift over the temperature with the heat sinks thermal resistance
range of 240 to 185C (Figure 1). of 18C/W or less and an ambient temThe op-amp IC compares its positive perature of 408C or less in still air. The
input voltage with the voltage across maximum power depends on the thersense resistor RSENSE.
mal resistance of the heat sink you
IC1s output drives an enhancement- use and the ambient temperature, so,
mode N-channel power-MOSFET, Q1, when you increase the supply voltage,
an STMicroelectronics (www.st.com) you must accordingly reduce the load
IRF530, such that the voltage across current. By pulsing the input voltage,
VIN
5V
0V
GND
15V C
1
100 nF
R1
90.9k
0.1%
3
R2
10k
0.1%
IC1
6
OPA277
4 C2
100 nF
15V
C3
2.2 nF
R3
470
C4
100 pF
Q1
IRF530
OUT
ILOAD
0 TO 1.5A
POWER
SUPPLY
UNDER
TEST
TURNS
AREA
R4
1k
NOTES:
Q1 NEEDS ADEQUATE HEAT-SINKING.
KEEP TERMINAL LEADS AS SHORT AS POSSIBLE.
RSENSE
0.33
1%
2W
Figure 1 This simple current sink allows you to test both the static and the
dynamic behavior of power supplies.
no flicker-noise component
94 Analog voltage controls
digital potentiometer
94 Harvest energy
designideas
the upper limit of the output current Also, you can test power supplies or
to several amperes, which allow you to voltage sources as low as 1V because
test low-voltage power supplies with of the low channel resistance of Q1
high output current.
and the RSENSE resistor; the lower limCapacitors C3 and C4 and resistors it is 1.5A(RSENSE1RDS(ON) )5735 mV,
R3 and R4 ensure loop stability, yield- where RDS(ON) is the on-resistance.
ing a circuit with a rise time of 1.4
You can also test multiple regulatmsec for an input step voltage of 0 to ed outputs of power supplies such as a
5V. So, you can test power supplies in 25 or a 212V supply voltage. In this
either static conditions, applying a dc case, you must connect the ground of
input voltage, or dynamic conditions, the power supply to the output of the
applying, for example, a pulsed input current sinkthat is, the drain terSTEVEfast EDN071214DI4189
FIGURE
1 output with
voltage to simulate
load transients. minaland
the negative
R3
1M
ON/OFF
R1
820
1N914
9V
BATTERY
3
7555
ON/OFF
NC
LED
R2
390
C1
100 nF
9V
BATTERY
R1
10k
R2
1M
C1
100 nF
7
6
3
7555
2
1
NC
1N914
LED
designideas
put is low.
These circuits require no currentlimiting resistor. The timer IC must
be a CMOS type because, to operate
correctly, the circuit design requires
low input currents. The prototypes use
Intersils (www.intersil.com) ICM7555
devices.EDN
R e fe r e nce s
10
2.5V
VOLTAGE
NOISE
(V/Hz)
15k
IC1
MAX4238
OUT
75
2.5V
COMMON
0.1
0.001
0.01
0.1
10
100
10,000
1000
FREQUENCY (Hz)
MIKE
designideas
Analog voltage controls
digital potentiometer
Hrishikesh Shinde, Maxim Integrated Products, Dallas, TX
VCC
VCC
PIC12F683
2
ANALOG
VOLTAGE
ADC
13
EXTRACT
8 MSBs
SDA
I2C
ROUTINE 3
SCL
DS1803
1
3
R e fe r e nce s
H
W
L
Figure 1 This circuit allows an analog-voltage input to select the digital potentiometers resistance.
Harvest energy
using a piezoelectric buzzer
edn080124di42011
DIANE
designideas
you can use them in the opposite way:
You obtain the maximum ac peak voltage that the piezoelectric buzzer generates when the vibration frequency
matches the resonant frequency of the
piezoelectric buzzer.
The power generator in Figure 1
is a simple circuit. The piezoelectric
buzzer produces an ac voltage when
it is under vibration; therefore, you
must convert this voltage to a dc voltage before charging the capacitor. The
four Schottky diodes form a bridge rectifier to perform this task. For a reliable and efficient operation, select
Schottky diodes, such as the 1N5820
rectifier diode from On Semiconductor (www.onsemi.com), that exhibit
22 H
PIEZOELECTRIC
BUZZER
1N5820
3.3VDC
1N5820
0.47F
2.5
1N5820
BZX85-C2V7
47 nF
1N5820
100 nF
1
2
3
4
MAX1675
FB
OUT
LX
LBI
GND
LBO
REF
SHDN
8
7
6
5
100 nF
47 nF
Figure 1 A simple vibrational-energy-harvesting circuit using an off-the-shelf piezoelectric buzzer as the power generator
turns mechanical energy into electrical energy.
Retriggerable monostable
multivibrator quickly discharges
power-supply capacitor
EDN080221DI4215FIG1
MIKE
uses a MOSFET, Q1, and a current-limiting resistor, RD, to discharge the highvoltage filter capacitor, CF, within one
second after you switch off the mains
power. The trick is to use a retriggerable monostable multivibrator to control the MOSFET.
While the mains power is on, optocoupler IC1 and the associated passive
components continue to generate symmetrical square pulses that they apply to
the A input of multivibrator IC2. Each
pulse triggers the circuit, forcing the
Q output to the low level. The multivibrator generates a 100-msec negative
pulse; then, Q should turn high. However, because triggering pulses arrive
before the multivibrators pulse is complete, the Q output never turns high,
the MOSFET is always off, and the rectifier works as usual. When you turn off
mains power, the Q output stays low for
100 msec after the last triggering pulse;
designideas
1 mH
220 nF
400V
L
INPUT
90 TO 264V AC
50/60 Hz
1M
1N4007
1N4007
6.8k 1N4007
2W
1N4007
RD
2k
6.8k
2W
9.1V
IC2
CD4538
16
20k
1M
N
1N4148
IC1
4N35
1N5924
10 F
100 nF
C
B
A
T2
T1
CF
100 F
400V
OUTPUT
125 TO 365V DC
Q
Q
Q1
IRF820
Figure 1 Because of the retriggerable feature of the CD4538 IC, the discharge network, Q1 and R D, remains off when
mains power is present; otherwise, it turns on and quickly discharges high-voltage filter capacitor, CF.
designideas
Edited By Charles H Small
and Fran Granville
amp in an inverting gain-of-10 configuration, along with several of its pertinent specifications. All of the input
offset arrives at the output with a gain
of 11 (called the noise gain) as an
output error. Any downstream circuitry
or observer looking at the output voltage cannot distinguish the output error
from the desired output signal.
Figure 2 shows the chop-the-noisegain method. S1 switches the additional shunt resistor, R3, in and out, changing the noise gain without affecting the
signal gain or bandwidth. There would
normally be some degradation of bandwidth, but C1 dominates the bandwidth limitation whether the switch
is open or closed. Now, you impose a
small square wave on the output with
an amplitude that is equal to the present dc errors. You can demodulate out
the error as with a conventional chop-
VIN
R2
1k
LTC6240HV
R1
10k
C1
0.01 F
Figure 1 An op amp has a conventional gain of 210. The noise gain is 11, so
all of the input errors appear at the output with a gain of 11. You cannot distinguish the signal from noise just by looking at the output.
edn080110di41961
DIANE
D Is Inside
66 Simple analog circuit provides
Class A buffer
designideas
resultant square wave now represents
an easily measurable 11 errors, which
you can then subtract from the output.
This technique is similar to that of
conventional chopper amplifiers, except that, in this case, you are chopping the error rather than the signal.
Figure 3 shows the oscillogram of
the output of the circuit of Figure 2,
with an input voltage of 0V (grounded). The top trace is S, the control
signal applied to S1 at 750 Hz. The bottom trace is the output error alternating between 1 and 2 mV, indicating 90
mV of op-amp offset. The output sees
the effect of doubling the noise gain of
the output offset. The difference between the two noise gains is 11, and
this difference dictates the amplitude
of the square wave that S1 causes, independently of the input voltage.
Figure 4 is similar to Figure 3, but
zoomed out and with a 2-mV-p-p slowmoving sine wave signal at the input
5V
VIN
11 OFFSETS S1 OPEN
VOUT =10VIN+ 22 OFFSETS S CLOSED
1
LTC6240HV
R2
1k
5V
R1
10k
R3
909
A
OPEN
S
CLOSED
S1
C1
0.01 F
33 pF
2k POTENTIOMETER
Figure 2 S1 switches the additional shunt resistor, R3, in and out, changing the
noise gain without affecting the signal gain or bandwidth.
2N7002
S
NC7SZ04
Figure 3 This oscillogram shows the output of the circuit in Figure 2, with an input voltage of 0V (grounded).
The top trace is S, the control signal applied to S1 at
750 Hz. The bottom trace is the output error alternating
between 1 and 2 mV.
edn080110di41962
5V
designideas
plifier IC1A has a voltage gain of five.
This block also provides high input impedance and low output impedance, so
that the second block, IC1B, operates
properly. The second block does most
of the work. Starting from a basic inverting amplifier comprising IC1B, R4,
and R5, you obtain the clipping effect by adding R3 and D1. R3, D1, R4,
and R5 determine the clipping level.
In addition, adding the IDC current
dc-shifts the output voltage. You can
trim adjustable potentiometer resistor
P1 to obtain the desired output voltage
shiftthat is, 1.6V.
If diode D1s current is negligible,
the output voltage, VO, is 2(11R2/
R 1 )3(R 5 /(R 3 1R 4 ))3V I 1V CC 3R 5 /
(R61P11R7)51.6253VI. Given that
the diode voltage, VDIODE, is 0.6VS,
V O 52(R 5 /R 4 )3V DIODE 1V CC 3R 5 /
(R61P11R7)51.621.65520.05V.
The clipping takes place near 0V,
protecting the ADC. Raising the clipping level makes the circuit less linear in the nonclipping range. In other
words, a design trade-off exists between
clipping level and linearity. Resistor R8
limits the current through the ADCs
input pin. Capacitor C2 is optional; it
C1
10 F
IDC
VI
R1
750
IC1A
AD8002
2
1 VO1
R3
820
R6
2.2k
R4
470
D1
1N4148
R2
3k
R5
1.3k
5V
8
IC1B
AD8002
5
4
6
7
VO
R8
51 VADC
ADC
C2
47 pF
5V
limits the VADC/VI bandwidth. Capacitor C1 helps to reduce the voltage noise
that might come from the VCC power
supply.EDN
R e fe r e nce s
ADC1175 - 8-Bit, 20MHz, 60mW
edn080207di42101 DIANE
A/D Converter, National Semicon-
VCC
P1
500
R7
1.5k
ductor, www.national.com/mpf/DC/
ADC1175.html
2 AD8002 Dual 600 MHz, 50 mW
Current Feedback Amplifier, Analog
Devices, www.analog.com/en/prod/
0%2C2877%2CAD8002%2C00.
html.
(placed in 3-6 folder)
designideas
VCC
9V
IN
PG
IC1 OUT
TPS7201
FB
EN
RS
31.6
0.5W
VB
IN
VF
576k
249k
0.1 F
OUT
IC2 ADJ
LT1763
BYP
SHDN
10 F
100k
6.49k
IC3
TL1431CD
10 nF 10 F
100 nF
VF DL
ENABLE INPUT
OF TLC070
1.37k
IC4
TLC070
2.8k
10k
Q1
VP0610L
LD_EN
ENABLE INPUT
OF CIRCUIT
1M
1M
VF
100 nF
VB
37.4k
53.6k
VDD
9V
10k
10k
>
Q2
DN2530N8
DL
IC5A
LM393
62k
>
237k
LASER
DIODE
IOP=80 mA
IC5B
LM393
100 nF
NOTE: THE POWER RATINGS OF THE RESISTORS ARE ALL 0.125W UNLESS OTHERWISE NOTED.
Figure 1 This laser-diode-drive circuit provides a constant current and protection against input overvoltages and start-up transients.
IC
IBIAS
Q1
Q2
VBE
R1
designideas
sources in the figures) with resistors.
At the quiescent, 0V-input-voltage operating point, both halves of
the circuit run at maximum current,
and both the input and the output
are at the same potential. When you
impress a voltage on the input, you
inject current into the Q2-Q3 emitter node. From there, current can go
up into base of Q1 or down into base
of Q4. The output voltage relative to
the input voltage determines the direction of the injected current. If the
input voltage is positive, it has no effect on the upper half because it is
already limiting. It can, however, reduce drive current in the lower half,
resulting in a reduction of lower output-drive current. Reduction of lower
side output current results in a rise in
output voltage. In short, an injected
signal current unlimits the stage of
opposite polarity.
At first glance, the circuit appears
to have unity gain. But, because Q2
and Q3 sense the tops of R2 and R3
VCC
an injected signal
current unlimits
the stage of
opposite polarity.
and not circuit output, R1 and R2 are
effectively in series with the output
load. If the loads impedance, RLOAD,
is small, the circuit gets significantly loaded down. However, as long as
the input stage does not clip, the circuit does not become distorted. The
source driving the buffer stage sets
hFE(Q1)3(R11RLOAD)V, where hFE is
forward-current gain.
Q2 and Q3 are common-base stages.
Their purpose is to translate input voltage to the bias voltage that Q1 and Q4
require. This voltage-translation action allows direct substitution of other
devices, such as MOSFETs or Darlington transistors.EDN
IBIAS
Q1
Q2
R1
VIN
R3
VOUT
R2
Q3
Q4
IBIAS
VCC
DIANE
designideas
Edited By Charles H Small
and Fran Granville
Figure 1 This family of curves shows that a thermoelectric cooler may actually
heat rather than cool at the maximum drive current if the heat sink the cooler is
mounted on is less than perfect.
Figure 2 A derating factor for maximum voltage and current is based on the
real-world thermal impedance of the TECs heat sink.
D Is Inside
94 Interface MIDI instruments
designideas
maximum cooling at a heat-sink impedance of zero, the situation changes
radically with increasing impedance
until theres no net cooling whatsoever. Further, for impedance greater than
VCC
CN1
CN-USB
FB1
R1
470
FERRITE BEAD
+
C2
C6
C7
10 nF
10 F 0.1 F
1
2
3
4
C5
0.1 F
GND
VCC
C1 VCC
0.1 F
VCC
C3
0.1 F
14
1
IC2B
IC2A
74HC14
74HC14
2 3
4
R3
220 5 2
1
R4
27
R5
27
Y1
6-MHz
RESONATOR
VCC
8
7
6
5
VCC
CS
IC4
NC 93C46/56/66 SK
NC (OPTIONAL) DIN
GND
DOUT
R12
10k
1
2
3
4
R2
220
4
3
C9
VCC
30
3
26
13
0.1 F
AVCC VCC VCC VCC-IO
6
25 TXD
3V3OUT
VCC
TXD
24 RXD
RXD
IC3
8
USBDM
23
R6
TLP115A
RTS#
6
22
4.7k
CTS#
7
5
21
DTR#
USBDP
R11
4
DSR# 20
1.5k 5
19
DCD#
RSTOUT#
18
VCC
VCC
RI#
27
XTIN
IC1
D2
D3
FT232BM
TRANSMIT
LED
LED RECEIVE
28
TXDEN 16
XTOUT
4
15
VCC
PWREN#
RESET#
R9
R10
14
220
220
32
PWRCTL
EECS
12
TXLED#
R11
RXLED# 11
1
EESK
2.2k
2
EEDATA
SLEEP# 10
31
TEST
AGND GND GND
29
9
17
J1
MIDI-OUT
C4
33 nF
SHIELD
C8
0.1 F
VCC
VCC
R8
220
D1
1N4148
5 2
1
J2
MIDI-IN
Figure 1 This USB-to-MIDI interface uses the FT232BM, a USB-to-UART interface chip that you need not program.
4
3
designideas
Equation 1
H(z) =
B 0z2 + B1z + B 2
z2 + A1z + A 2
STEVE EDN070124DI4203
FIGURE 1
Designers use PSpice mainly to able for filter design (Reference 1).
z21
H(z) = 2
.
simulate analog circuits. How- The sampling frequency, fS, relates to
z 0.9096707z + 0.809374
ever, you can also simulate digital filters with it. The main components in
B2
a digital filter are delay elements, adders, and multipliers. Although you
can implement adders and multipliers
using operational amplifiers, you can
Equations
for EDNwith
080124
DI4203
B0
simulate
a delay element
a transB1
mission line. The transmission line
in PSpice is a long-forgotten element
STEVE EDN070124DI4203 FIGURE 2
that can realize a delay of seconds.
INPUT
OUTPUT
Z1
Z1
Equation 1Figure 1 shows a secFor example,
ond-order recursive digital filter. The
transfer function for this filter is:
H(z) =
B 0z2 + B1z + B 2
z2 + A1z + A 2
A1
A2
Figure 1 The transfer function for a second-order recursive digital filter has
coefficient values that yield a lowpass, highpass, band-reject, or bandpasstransfer function.
z 0.9096707z + 0.809374
R3 1/A1
1.0992989
1/B1 R11
1e6
E2
R1
1
R10
1
1/B0 R6
1
E4
T1
T2
E1
R2
1
1Vac
0Vdc
R9
1
1/B2 R7
1
E3
E
R4 1/A2
1.23552143
Figure 2 In the PSpice circuit, the VCVSs (voltage-controlled voltage sources), E1 and E2, simulate voltage followers, and
VCVSs E3 and E4 and the resistors that connect to them simulate summers.
designideas
In this case, the transmission-line delay is 1/60005166.67 msec. If you additionally specify an impedance, Z, of
1V for the transmission line, then the
parameters for the transmission line are
Z051V, and t5166.67 msec. Figure 2
shows the PSpice circuit. The VCVSs
(voltage-controlled voltage sources),
E1 and E2, simulate voltage followers,
and VCVSs E3 and E4 and the resistors that connect to them simulate
summers. Figure 3 shows the results of
the simulation.EDN
Reference
Lpez, David Bez, Windows
Based Filter Design with Winfilters,
IEEE Circuits and Devices, Volume
13, 1997, pg 3.
1
VOLTAGE 4
(V)
0
0.05
0.5
1
FREQUENCY (kHz
1.5
Figure 3 In this PSpice simulation, the digital bandpass filter uses transmission
lines as delay lines.
input pulse. A dc-control voltage selects a time delay within the full-scale
EDN080124DI4203FIG
MIKE
range. When the rising edge of a pulse
triggers the input, the circuits output
Luca Bruno, ITIS Hensemberger Monza, Lissone, Italy
generates a pulse with its rising edge
Some applications require ing and pulse-delay applications. This delayed by an amount equal to the seSTEVE
EDN080306DI4217
1
clock-timing
adjustments,
such DesignFIGURE
Idea describes
a delayed-pulse lected time delay, TD, plus a fixed inas generating precision clocks for generator using a dual-CMOS D-type herent propagation delay TPD. Also, a
time-interleaved ADCs, or delay ad- flip-flop (Figure 1). The circuit pro- time constant, R4C2, determines the
justments in a variety of precision-tim- vides precision time delays of a trigger- output pulses width.
A precision dc source, IO, and capacitor
C1 set the full-scale delay range.
CURRENT SOURCE
When Q3 is off, the current source
5V
charges capacitor C1, generating a linR1
6
ear-ramp voltage with slope equal to
1.33k
5
1
S
DELAYED
D
Q
5V
0.1%
IO/C1. The delay is the time it takes for
VREF
PULSE_OUT
5V
R2
3
1.233V
the ramp to rise from its initial voltage
11k
IC
CLK
C3
1A
0.1%
CD4013B
100 nF
to the control-voltage value.
2
Q
IC3
R
In this application, the ramp slope
DELAYED
LM4041
4
C2
R4
is
10 mV/1 msec, so that the full-scale
PULSE_OUT
8
100 pF
10k
3
Q1
delay range is 256 msec for a control
IC2A
R6
1
D1
2N5087
DC-CONTROL
TS3702
100
voltage of 0 to 2.56V. You can set the
2
Q2
1N4148
VOLTAGE
4
2N5087
0 TO 2.56V
full-scale delay by changing IO through
IO
C4
100 A
either R11R2 or capacitor C1. For best
1 nF
R5
8
accuracy, the current source can range
100k
C
1
9
13
S
D
Q
R3
10 nF
IC1B
from 10 mA to 1 mA, the capacitors
OPTIONAL
Q3
18k
1%
CD4013B
2N2222A
NOTES:
TRIGGER
value can range from 1 nF to 1 mF, and
11
CLK
12
IC1 POWERED AT 5V.
INPUT
Q
NC
the corresponding full-scale delay can
R
CONNECT A 100-nF
5V
RAMP
10
DECOUPLING CAPACITOR
range from 2.56 msec to 256 msec. Use
0V
VOLTAGE
CLOSE TO IC1s
a precision film capacitor for C1.
POWER-SUPPLY PINS.
The basis of the current source is a
shunt
precision-micropower-voltageFigure 1 The rising edge of a trigger input starts a precision ramp voltage that compares
reference,
IC3, producing a reference
with a control voltage, generating a precise delay.
voltage of 1.233V with an initial ac-
designideas
curacy of 0.2%. A Texas Instruments
(www.ti.com) LM4041, through precision resistors R1 and R2, biases the
Darlington-coupled transistors Q1 and
Q2 with a reference current IO5VREF/
(R11R2)5100 mA. The Darlington
configuration ensures that base current is negligible and that the output
collector current can achieve a worstcase accuracy of 0.3%. You can use any
small-signal transistor, but, for best accuracy, use high-gain, low-level, lownoise BJTs, (bipolar-junction transistors) such as a 2N5087 or a BC557C.
IC1A is a one-shot circuit (Reference 1). The output pulses width,
TW, is R4C23ln(VDD/VTH), where VTH
is the threshold voltage of the digital
CMOS. Because VTHPVDD/2, then
TWPR4C230.69. Diode D1 reduces
recovery time. After power-up, Q3 is
in saturation, absorbing the current
sources output, and, as soon as an input
pulse triggers the circuit, IC1Bs Q output goes low, switching off Q3, starting
a ramp. When the ramp exceeds the
control voltage, then the IC2A compar-
a leap ahead
in DC/DC-Converters
AS1340
2.7V to 50V adjustable output voltage
2.7V to 50V input voltage range
100mA @ 12V from 3.3V VIN
Up to 90% efficiency
https://shop.austriamicrosystems.com
Power-OK output
Part
No.
Input
Voltage
Output
Voltage
Output
Current
Efficiency
mA
AS1323
0.75 to 2.8
2.7
100
85
AS1325
1.5 to 3.5
3.3
300
96
SOT23-6
AS1326
0.7 to 5.0
650
96
TDFN-10
AS1329
0.65 to 5.0
2.5 to 5.0
315
95
TSOT23-6
AS1340
2.7 to 50
2.7 to 50
100
88
3x3 TDFN-8
AS1341
4.5 to 20
1.25 to VIN
600
96
3x3 TDFN-8
Package
TSOT23-5
designideas
Edited By Charles H Small
and Fran Granville
D Is Inside
54 Microcontroller moving-dot dis-
multiple chart or
oscilloscope-timing ticks
Noureddine Benabadji,
University of Sciences and Technology, Oran, Algeria
56 Fast-settling synchronous-
register during the application softwares initialization of the device. Because the calibration value is unique to
each microcontroller, problems arise
for time-sensitive applications if you
erase or overwrite the last address.
The circuit in Figure 1 recovers
the calibration value by recalibrating against a reference clock, the 4MHz crystal. The frequency looks for
the best calibration value to ensure
that the microcontrollers internal oscillator runs within 1% accuracy at 4
12
11
CD
MR
RS
R1
1M
C2
47 pF
4 MHz
RTC
10
CTC
9
C3
47 pF
C1
100 nF
14 13 15
PIC10F2XX
Q8=128 SEC
(4 MHz/512)
GP0 5
GP3
GP1 4
GP2
VDD
R3
680
VSS
5V
R2
680
7
C4
100 nF
1 MHz1%
OPTIONAL FREQUENCY
METER OR OSCILLOSCOPE
Figure 1 This circuit and an assembly-language program that occupies less than 250 bytes allow you to calibrate a
PIC10F2xx microcontroller against a 4-MHz reference clock.
edn080207di42121
designideas
in a compressed zip file from www.edn.
com/080501di1.
The baseline PIC microcontroller,
which includes the PIC10F, PIC
12C508/509/510, or PIC16F505/506
series, uses its internal timer, Timer
0, to count the number of instruction
cycles that execute in one period from
R1
1
VDD
11
IC1
MC68HC900QT1 PA1 6
10
PA0
PA4
VDD
OUT1
OUT2
OUT3 12
IC2
C
CD4051
OUT4
VSS
8
OUT5
6
7
14
IN
15
LED1
LED2
LED3
LED4
LED5
INH
OUT6
VCC
VSS
OUT7
LED6
re-create it (Reference 2). The method in this Design Idea needs three output linesdata, clock, and latchand
requires some firmware and hardware.
Exploiting the fact that only one LED
in a dot display should light at a time,
you can use National Semiconductors
(www.national.com) CD4051 1-to-8
analog demultiplexer (Figure 1). This
circuit needs three microcontroller
outputs, and the firmware is simple and
straightforward. The additional benefit is that the microcontroller now does
not limit the LED current and voltage;
you can choose them independently.
Listing 1, which you can download
from the Web version of this Design
Idea at www.edn.com/080501di2, provides demo firmware illustrating this
design. The demo program automatically moves the lit dot back and forth
by incrementing and decrementing a
modulo-7 counter. Ideally, any three
adjacent microcontroller outputs,
such as pA0, pA1, and pA2, are available for the A, B, and C inputs of the
CD4051. But, this scenario is not always possible. In this application of a
low-end, eight-pin MC68HC908QT1
microcontroller, you can use pins pA2
and pA3 only as inputs. You can easily overcome this problem by programming, as Listing 1 shows. This Design
Idea applies to any small microcontroller because it uses only a standard
instruction set.EDN
R e fe r e nce s
Jayapal, R, Microcontrollers
single I/O-port line drives a bar-graph
display, EDN, July 6, 2006, pg 90,
www.edn.com/article/CA6347254.
2 Raynus, Abel, Squeeze extra
outputs from a pin-limited microcontroller, EDN, Aug 4, 2005, pg 96,
www.edn.com/article/CA629311.
LED7
Figure 1 Using the 1-to-8 CD4051 analog demultiplexer you can interface a
moving-dot LED display to a low-end microcontroller using just three outputs.
bits nibbles of the 8-bit oscillationcalibration registers best value. Output GP2 acts as a multiplexing line to
drive these LEDs for 8 to 10 sec and
then as the oscillator output to yield a
1-MHz signal, which you can measure
with a frequency meter or an oscilloscope.EDN
designideas
Microcontroller displays multiple
chart or oscilloscope timing ticks
William Grill, Honeywell, Lenexa, KS
B
A
6
10 pF
TIMINGSEQUENCE
MODE
4 MHz
2 12F508
10k
5k
TO CHART
ADC
10 pF
PT1
PT0
VREF
R1C1=T2.
C1
9 S1
3
5
X1
R1
A
5 1
12
7
V1
74HC4053
R3
X1
X0
74HC4053
C2=C3.
R2
OPTIONAL
C3
9
A
10 2
11
14
X0
S2
13
VOUT
VOUT=DACVREF(1+R2/R3).
0VOUTVREF(1+R2/R3).
Figure 1 This DAC ripple filter combines a differential integrator, A1, with a
sample-and-hold amplifier, A2, in a feedback loop operating synchronously
with the PWM.
edn080320di42311
DIANE
C2
designideas
timers and comparators. This
situation results in ac-frequency components as inconveniently slow as 100 or 200 Hz.
With such low ripple frequencies, if you employ enough ordinary analog lowpass filtering
to suppress ripple to 16-bit
that is, 296-dBnoise levels,
DAC settling can become a
full second or more.
The circuit in Figure 1
avoids most of the problems of
lowpass filtering by combining
a differential integrator, A1,
with a sample-and-hold amplifier, A2, in a feedback loop
operating synchronously with
Figure 2 The DAC output settles within one cycle.
the PWM cycle, T2 in Figure
2. If you make the integrator
time constant equal to the PWM cycle resulting DAC exactly high speed,
timethat is, R13C15T2and, if the 0.01-sec settling is still 100 times betsample capacitor, C2, is equal to the ter than 1-second settling. Just as imhold capacitor, C3, then the filter can portant as speed, this improvement
acquire and settle to a new DAC value in settling time comes without comin exactly one PWM-cycle time. Al- promising ripple attenuation. Ripple
though this approach hardly makes the suppression of the synchronous filter
designideas
plies allows the output swing of the
phase detector to be symmetric at approximately 0V. If your design doesnt
require this symmetry, you can use a
single 5V supply with 2.5V positive
offset-biasing of the op amp. In this
case, the output swing is symmetric with respect to 2.5V. As with all
wide-bandwidth-op-amp circuits, you
should take care to connect the power-supply bypass capacitors to ground
with short connections and as close to
the op amps power-supply pins as possible to avoid instability.
This same gain-switching scheme
also works as a frequency mixer. If
the input signal is at frequency vS
and the reference-square-wave input
is at frequency vlo, the IF output signal is (vlo2vS) or (vlo1vS). You obtain the desired IF signal by replacing
the output lowpass filter in Figure 1
with a bandpass filter tuned to the desired IF frequency of vlo6vS. If the
switching rate for the reference signal is higher than the disable function can provide, then you can use
5V
75 0.1 F
1.5k
3k
2 7
0.1 F
INPUT
V (t)
SIGNAL IN
2k
6
EL5100
8 DISABLE
3
4
10k
VOUT (t)
0 TO 4V
SQUARE-WAVEREFERENCE1k
SIGNAL INPUT
0.1 F
PHASEDETECTOR100 OUTPUT
SIGNAL
0.1 F
75
5V
the harmonic mixing using the oddorder harmonics of the reference signal. This approach reduces the gain
designideas
Edited By Charles H Small
and Fran Granville
D Is Inside
66 Tiny microcontroller hosts
) ,,
V
V1122
V
V2222
3
tt == Equation
C
C
22PP
( 2)2PP tt
CHARGE-PUMP
DOUBLER
OR BOOST
CONVERTER
V
V1122
V
V2222
Equation
2
U
=
C
,,
U= C
22
C
C ==
MINIMUM VOLTAGE
THRESHOLD 37V
..
2
V
V1122
V
V2222V
IN
80V
C1
S1
1
(( ))
COMPARATOR
VIN
40V
POWER-SOURCE
INPUT: 36 TO 80V
OUTPUT: 5V
LOAD
Figure 1 Charged to double the input voltage, the energy stored in capacitor
C1 dumps into the input of the brick power supply during brownouts when
the input voltage drops to less than 237V.
edn080221di42141 DIANE (in the 3-6 folder)
push-pull-driver overlap
using ECL-wired OR
designideas
280V. Figure 1 shows how you can use
this feature. The figure depicts a positive input voltage. The brick is isolated, so polarity is irrelevant, but positive
interpretation is easier to illustrate.
Remember that the stored energy
in the capacitor grows exponentially, whereas the capacitors voltage increases linearly. The doubler charges
C1 to twice the input voltage or at least
to 80V. Even if, hypothetically, you expect a 5-msec brownout as often as 10
Batteries are the typical power help of a few additional discrete comsources for portable-system ap- ponents.
plications, and it is not unusual these
This Design Idea shows how to creSTEVEateEDN080306DI4218
FIGURE
days to find microcontroller-based
not just one, but two dc/dc convertportable systems. A variety of micro- ers with just a tiny eight-pin microconcontrollers operates at low power-sup- troller and a few discrete components.
ply voltages, such as 1.8V. Thus you The design is scalable, and you can
can employ two AA or AAA cells adapt it for a wide range of outputto power the circuit. However, if the voltage requirements just by changing
circuit requires higher voltagefor the control software for the microconLED backlighting for an LCD, for ex- troller. You can even program the miample, which requires approximately crocontroller to generate any required
7.5V dcyou must employ a suitable output-voltage start-up rate. Figure
dc/dc converter to boost the power- 1 shows the basic topology of a boost
supply voltage from, for example, 3V switching regulator. The output voltto the required voltage. However, you age in such a regulator is more than the
can also employ a microcontroller to input voltage. The boost switching regdevelop a suitable dc/dc-boost-volt- ulator operates in either CCM (conage converter (Reference 1) with the tinuous-conduction mode) or DCM
VDC
INDUCTOR
VOUT
DIODE
R1
C
RLOAD
R2
ERROR
AMPLIFIER
PULSE-WIDTHMODULATOR
OUTPUT
PULSE-WIDTHMODULATOR
GENERATOR
VREF
MODULATION
INPUT
Figure 1 The output voltage in a boost switching regulator is more than the
input voltage. The boost switching regulator operates in either CCM (continuous-conduction mode) or DCM (discontinuous-conduction mode)
SWITCH
(discontinuous-conduction
It
Equation
1
Equations
for DI4218 3mode).
6 2008
is easier to set up a circuit for DCM
VDCThe
D name
T
operation (Reference
I L MAX = 2).
,
L
comes
from
the
the4218
inductor
Equations
for DI
3 6 2008
VDC
1Dfact
T that
Equation
I L MAX =falls to 0A for,some time during
current
L
each PWM
period in
in 3CCM,
Equations
forDCM;
DI4218
6 2008
Equations
fornever
6 2008
Equation
2DI4218
the inductor
current
is
0A. 3The
Equation
1
V
T
DC
maximum
I L MAX 2=current passes, through the
Equation
L of high period of
inductorEquation
at the end
1
1the PWM Equation
1 V the
output (when
Dswitch
T is
DT
=DC DC
,
on) and is:IL T=R V
(V
V, )
OUT
DC
V MAX
D2 T
L
Equation
TR = DC
, DT
V
(VOUT
)V D ,T
(1)
I L MAXV
= DCDC
I L MAX = DCL
,
L3
Equation
Vtheinput
D 2 Tvoltage, D is the
where VDCEquation
is
TR = DC
,
duty
cycle,(3VTOUT
is
the
total
Equation
VDC
) cycle time,
2
and L is Equation
the
inductance
Equation
2 of the induc TRfalls
L Tdiode
tor. The current through
VDC DIthe
,
TR =I LOAD = MAX ,
to zero
inItime3T
2 ) T
(V. R VDC
Equation
L MAX RTOUT
VDC , D T
I LOAD =
TR =
T VDC D T, ,
(2)
TR2 (=V
V )
(OUT
VOUTDC
VDC )
Equation
4
Equation
I L MAXis3the
TR average diode
The Iload current
=
,
LOAD
Equation
4
2
T
current, Equation 3
Equation 3
VR2DC D2 T
I L MAX T
I LOAD
=
.
(3)
I LOAD
=
L ,(VOUTVDC )
EquationV24DC D222TT
I L MAX2and
TR simplifies
I LOADequations
=
.
from
I L MAX
T,)R
L =(1Vand
VDC
I2LOAD
OUT
I LOAD = 2 T
,
to:
2 T
Equation
52
Equation
2 4
V DC D T
I LOAD =
. (4)
Equation
5 2 L (VOUTVDC )
Equation 4
Equation 4
The output voltage, VOUT
2 V
V2 , is: D
TDC D2 T
I LOAD
= = VDC
.
VOUT
1
+
,
L DC
(V2 V
2DC
L) I LOAD
Equation 5 2VDC
2 DOUT
2T
(5)
VOUT = IVDC =1 + V VDC
2 D 2 T
D , T .
LOAD
DC
I LOAD
I LOAD
.
2=2LL(V
V
)
2 L (OUT
VOUTDC
VDC )
5
The valueEquation
of Equation
the output
V6DCcapacitor,
D2 T
VOUT
= VDC the
1 +ripple
which
determines
voltage, ,
2 L I LOAD
Equation
6
Equation
5
is:
Equation 5
dV I
V D2 T
=DC . 1 + DC (6) ,
VOUT = V
dt C
2 L I
dV Equation
I
6
VDC D2LOAD
2 T
= .
T
V
=
V
1
+
,
dt
C
where dV/dt
represents
in the
DC
OUT
VOUT
=DC
V the
1drop
2+ L I LOAD ,
period
2 ofL the
I LOAD
output voltage
duringDC
the
Equation
PWM
dVsignal,
I I is the6load current, and
= .
C is the
output capacitor.
dt required
C
Equation
The totalEquation
period6 of6 the PWM wave
dV I
= .
dt C
dV I
dV
= .I
= .
dt C
dt C
designideas
is T and is a system constant. D is the
duty cycle of the PWM wave, and TR
is the time during which the diode
conducts. At the end of TR, the diode
current falls to 0A. The period of the
wave is T.D3T1TR for DCM. The
difference of the PWM period, T, and
(D3T1TR) is the dead time.
The switch that operates the inductor is usually a BJT (bipolar-junction
transistor) or a MOSFET. A MOSFET
is preferable because of its ability to
handle large current, better efficiency, and higher switching speed. However, at low voltages, a suitable MOSFET with low enough gate-to-source
threshold voltage is hard to find and
can be expensive. So, this design uses a
BJT (Figure 2).
Microcontrollers offer PWM frequencies of 10 kHz to more than 200
kHz. A high PWM frequency is desirable because it leads to a lower inductor value, which translates to a small
inductor. The Tiny13 AVR microcontroller from Atmel (www.atmel.
com) has a fast PWM mode with a
frequency of approximately 37.5 kHz
and a resolution of 8 bits. A higher
PWM resolution offers the ability to
more closely track the desired output
voltage. The maximum inductor current from Equation 1 is 0.81A for a
20-mH inductor. The transistor that
switches the inductor should have a
maximum collector current greater
than this value. A 2SD789 NPN transistor has a 1A collector-current limit,
so it is suitable for this dc/dc converter.
The maximum load current achievable
with these values, from Equation 4, is
54 mA and thus meets the requirement
of maximum required load current for
an output voltage of 7.5V.
V1OUT
7.5V AT 50-mA
VCC
1N5819
R1
1k
Q1
2SD789
330 F
16V
R3
5.1k
100 F
25V
R6
12k
4
TINY13
VCC
0.1 F
Figure 2 An Atmel Tiny13 AVR microcontroller regulates two boost-dc/dc-converter outputs using its internal ADCs and PWMs.
R4
1k
Q2
2SD789
R5
168k
1N5819
5
VCC
3V
VCC
L2
100 H
R2
33k
L1
20 H
V2OUT
15V AT
15 mA
designideas
R3
22k
IC2A
HCT132
1
3
2
VCC
D1
Q1
IC1A
R1 HCT7A Q1
4
S1 C1
1
IC2B
HCT132
4
6
5
VCC
5
6
IC2C
HCT132
9
8
10
IC2D
HCT132
12
11
R4
22k
R1
330
Q1
T1
FUSE
F1
R2
330
13
CLOCK
Q2
R5
22k
1
FREQUENCY
R6
22k
2
FREQUENCY
Figure 1 Cross-coupled gates prevent one transistor from turning on before the other turns off. Fuse F1 protects against
catastrophic failures.
polarity to drive the switching transistors. Monitoring the transistors collector voltages senses the turn-off of each
transistor using the voltage dividers
R3/R4 and R5/R6. Because the collector voltage swings to twice the supply
voltage, the voltage dividers halve the
voltage. The impedance of the voltage
dividers also limits the gates input current to a safe level during overshoot.
designideas
DATA B
CLOCK
250-MHz,
4-NSEC
PERIOD
DATA B
CLOCK
250-MHz,
4-NSEC
PERIOD
D
Q
10H131
Q
D
Q
10H131
Q
(a) AN1650/D,
Designs, Application Note
On Semiconductor, www.onsemi.
10H107
com/pub/Collateral/AN1650-D.PDF.
2 Dual D Type Master Slave FlipFlop, MC10H131 Data Sheet, On
(b)
Semiconductor, www.onsemi.com/
10H107
DATA A
10H131
Q
pub/Collateral/MC10H131-D.PDF.
Triple 2-Input Exclusive OR/
Exclusive NOR Gate, MC10H107
Data Sheet, On Semiconductor,
www.onsemi.com/pub/Collateral/
MC10H107-D.PDF.
D
Q
10H131
Q
A XNOR B
2
D
Q
10H131
Q
(c)
DATA A
(a)
DATA B
10H107
(b)
(d)
CLOCK
250-MHz,
4-NSEC
PERIOD
D
Q
10H131
Q
D
Q
10H131
Q
D
Q
10H131
Q
2
A XNOR B
D
Q
10H131
Q
Figure 1 The XNOR comparison of inputs A and B results in too much propagation delay to guarantee setup at the final
flip-flops input (a). The
equivalent XNOR circuit uses NOR, AND, and OR gates (b), and OR gates and inverters realize
1
3
the XNOR function (c). You can also implement the circuit using wired ORs (d) to eliminate the interflop XNOR-gate delay
and almost double the usable clocking speed.
2
(c)
DATA A
DATA B
(d)
CLOCK
250-MHz,
4-NSEC
PERIOD
D
Q
10H131
Q
D
Q
10H131
Q
D
Q
10H131
Q
2
D
Q
10H131
Q
A XNOR B
designideas
Edited By Charles H Small
and Fran Granville
D Is Inside
UARTs with a PC
VCC2
EPM240Z-M100
WEAK
PULLUP
RESISTOR
PIN
PIN
OSCILLATOR
LPM REGISTER
CTOUCH
PIN
OSCILLATOR
8 mm
LPM COUNTER
EN
LPM REGISTER
SWITCH
FAST
D
Q
CO
MODULUS=16
TOUCHSWITCH
LAYOUT
ALTUFM
OSCILLATOR
4.4 MHz
25%
25
HEADER
EN
APPLICATION
LOGIC
SWITCH
SYNC R
LPM COUNTER
CO
MODULUS=80
SAMPLE
JTAG
Figure 1 This capacitive-touch-switch decoder uses only a MAX IIZ CPLD and no
external components other than the capacitive switch.
edn080515di42501
DIANE
designideas
the slow-rising pin signal. Once the pin
node reaches the high-voltage threshold, the D input of the PINOSC registers a zero. On the next clock edge, the
PINOSC signal goes low, driving the
pin node low for one full clock cycle.
This PINOSC circuit oscillates at two
fundamental frequencies, depending
on the state of the touch capacitor.
Putting the register into the oscillator
loop reduces noise and makes the oscillator stable and synchronous with the
decoding logic. The PINOSC period is
always a multiple of 1/4.4 MHz or the
frequency of the internal oscillator.
The switch decoder counts the period of 16 PINOSC cycles and compares
it with a known time period. If 16 or
more cycles happen in less than the
sample period, it means that no one is
touching the switch. If fewer than 16
cycles happen in the sample period, it
means that someone is touching the
switch, and the PINOSC oscillation
becomes slower. The lower LPM counter sets the sample period.
For example, the sample signal was
active once every 80 clock cycles in a
prototype (Figure 2). The upper LPM
counter measures the period of 16 PI-
INTERNAL
OSCILLATOR
TOUCH
PIN OSCILLATOR
FAST
SAMPLE
SWITCH
designideas
3.1253805250R(21110.125)380
5250R(2380)1(1380)1(0.1253
80)5250. The result is ((foo,,1)1
foo1(foo..3)). Left-shifting by one
is the same as multiplying by two, multiplying by one is the same as adding the multiplicand once to the result, and right-shifting by three is the
same as dividing by eight or multiplying by 0.125. A third example is 2.62
53805210R(210.510.125)3805
210R(2380)1(0.5380)1(0.1253
80)5210. The result is ((foo,,1)1
(foo..1)1(foo..3)). Left-shifting
by one is the same as multiplying by
two, right-shifting by one is the same
as dividing by two or multiplying by
0.5, and right-shifting by three is the
same as dividing by eight or multiplying by 0.125.
All of these examples take up less
space and are faster than calling the
RS232-to-TTL converter
tests UARTs with a PC
Matthieu Bienvene, Malissard, France
R2
10k
LED1
Q1
BC546
VCC
D3
5.6V
D4
3.9V
5V
3.3V
S1
1
2
IC1
MAX3232
11
10
INPUT
C5
100 nF
R3
1k
R1
10k
R5
1k
CN1
D2
1N4001
VCC VCC
R4
270
D1
DTR 1N4001
RTS
R6
1k
CN2
1
2
OUTPUT
14
TTL
RS-232
12
1
3
C4
100 nF
TX
RX
DTR
RTS
13
TTL
9
C3
100 nF
CN3
4
5
C1
C1
RS-232
5
4
3
2
1
8
2
TO SUBMINIATURE
C1
100 nF D9 CONNECTOR
V
V 6
C2
100 nF
C2
C2
VCC 16
15
GND
VCC
Figure 1 An RS232-to-TTL converter uses the unused DTR and RTS outputs of a PCs COM port to self-power the circuit.
edn080207di42111
designideas
Hot-swap circuit allows two computers
to monitor an RS-232 channel
Jeff Patterson, All Weather Inc, Sacramento, CA
C1
10 F
25V
IN
C2
0.1 F
5V
IC1 OUT
LM2937IMP
GND
2
5V
C3
33 F
10V
C4
0.1 F
C5
0.1 F
J1
J1
J1
RADIO SERIAL J1
PORT
J1
(DB9-M)
J1
J1
J1
POWER IN J1
1
2
3
4
5
6
7
8
9
C6
1 F
16V
C7
1 F
16V
2
16
6
V
VCC
V
14
11
DOUT1
DIN1
7
10
IC2
DOUT2
DIN2
13
MAX3232ID ROUT1 12
RIN1
8
9
RIN2
ROUT2
C2 C2 GND C1 C1
5
C8
1 F
16V
15 3
5
4
IC3
MC74ACT08D
C9
1 F
16V
5V
C10
0.1 F
J2
J2
J2
J2
CDP 1 PORT J2
(DB9-F)
J2
J2
J2
J2
1
2
3
4
5
6
7
8
9
J3
J3
J3
J3
CDP 2 PORT J3
(DB9-F)
J3
J3
J3
J3
1
2
3
4
5
6
7
8
9
C11
1 F
16V
C12
1 F
16V
2
16
6
V
VCC
V
14
DOUT1
DIN1
7
IC4
DOUT2
DIN2
13
MAX3232ID ROUT1
RIN1
8
RIN2
ROUT2
C2 C2 GND C1 C1
5
15 3
C14
1 F
16V
5V
11
10
12
9
C13
0.1 F
1
2
14
IC3
7 MC74ACT08D
C15
1 F
16V
9
10
IC3 8
MC74ACT08D
12
13
IC3 11
MC74ACT08D
Figure 1 This hot-swap RS232 interface allows two computers to monitor traffic on a computers RS232 port.
edn080306di42201
DIANE
designideas
Improved laser-diode-clamp circuit
protects against overvoltages
James Zannis, Baulne-en-Brie, France
LASER-CURRENT SUPPLY
LASER-CURRENT SUPPLY
R3
100k
LASER
LASER
R1
1M
Q1
1N914
PN4391
C1
47 nF
R2
47k
2N2222A
Q1
12V
edn080306di42191
Q2
1N914
PN4391
R1
100k
C1
47 nF
R2
47k
12V
edn080306di42192
designideas
Edited By Charles H Small
and Fran Granville
D Is Inside
70 Programmable current source
Accurate and stable temperature control is necessary for effectively using many thermally sensitive components and sensors, such as
semiconductor lasers and optical detectors. An industry has grown up in
response to provide thermal-control
devices, such as TECs (thermoelectric coolers), temperature sensors, and
both monolithic and hybrid application-specific driver ICs, to facilitate
the associated designs. This availability eases the implementation of highperformance thermostasis electronics
with good dynamic behavior, because
it allows you to assemble feedback
loops with flexible and sophisticated
control characteristicsPID (pro-
RT1
RT2
RH
100k
RC
30k
RC
CW
25k
SETPOINT
PID
NETWORK
TEMP
digital control
74 Microcontroller controls
74 Composite instrumentation
THERMAL GRADIENTS
T=ZHEAT FLUX.
HYTEK HY5640
1
RH
portional-integral-differential) feedback loops, for examplewith nothing more than appropriate choices of
shunt resistance and capacitance. Unfortunately, achieving good static stability is sometimes more difficult because the thermal properties of a system, rather than the electronics, often
cause limited temperature-controlloop static stability.
Every thermal-control system incurs nonzero thermal impedances in
the heat-transfer paths between the
source of heating, cooling, or both.
These paths include the thermal load,
which is the object of thermostasis;
the temperature sensorthe thermistor, for example; and the ambient
TEC
14
13
2 HEAT_LIMIT
TEC
12
3
COOL_LIMIT GND2
11
4
GND1
5
10
TC
VS
9
6
THERM
TEC
7
8
THERM/TEMP VCC
Z1
HEAT
SINK
5V
Z2
HEAT
0.1 F
SETPOINTVERSUSTEC-DRIVE
FEEDBACK
THERMAL
LOAD
Z3
Z4
AMBIENT
TEMPERATURE
RT
THERMISTOR
Figure 1 This circuit partially cancels the effects of thermal gradients in the loads thermal impedances. It works by providing an adjustable positive- or negative-feedback path from the TEC-drive level that couples changes in ambient temperature into compensating changes in the thermistor setpoint.
edn080417di42371
DIANE
designideas
even perfect thermostasis of
to an adjustable bridge circuit
the sensor doesnt equate to
that comprises RT1, RT2, the
10
adequate stability of the loads
potentiometer, and associattemperature (Figure 1).
ed circuitry. With correct ad9
For example, if Z1/Z2 is greatjustment of RT1 and RT2, a test
er than Z3 /Z4, where Z is the
determined that the thermisCURRENTLIMIT SET
impedance, then rising ambitor setpoint must move either
8
FOR
ent temperatures will cause the RESISTORS RC
with or in opposition to ambiAND RH
temperature of the load to rise,
ent temperature, so that net
(k)
7
whereas falling ambient temstability of the load results. A
peratures will cool the load.
version of this concept flew
By contrast, if Z1/Z2 is less than
as part of two tunable-diode
6
Z3/Z4, then rising ambient temlaser spectrometers in the
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
peratures will cause the temscience package of the 1999
MAXIMUM CURRENT (A)
perature of the load to fall and
Mars Polar Lander (Refervice versa (Figure 2). Reducence 1).EDN
Figure 2 The TECs maximum-drive heat- and cool-curing the parasitic impedances
rent ratings determine the selection of current-samwith tighter thermal coupling
R e fe r e nce
pling resistors RC and R H.
1 May, Randy D, Siamak
and better insulation can reduce but seldom eliminate the
Forouhar, David Crisp, W
EDN080417DI4237FIG2
gradient and magnitude of the error.
couples
changes inMIKE
ambient tempera- Stephen Woodward, David A Paige,
The circuit in Figure 1 provides a ture and, therefore, in TEC drive into Asmin Pathare, and William V Boyndifferent solution: an electronic work- compensating changes in the thermis- ton, The MVACS tunable diode laser
around to at least partially cancel the tor-setpoint temperature. The imple- spectrometers, American Geophysieffects of thermal gradients in the im- mentation in Figure 1 uses a popu- cal Union, Journal of Geophysical
pedances. It works by providing an ad- lar hybrid TEC controller. Two signal Research, Volume 106 (E8), 2001,
justable positive- or negative-feedback nodes that track TEC drive, COOL_ pg 17,673, www.agu.org/pubs/#
path from the TEC-drive level that LIMIT and HEAT_LIMIT, are inputs journals.
IN
LM317
ADJ
OUT
1.55
3.1
6.2
12.4
15.5
31
62
124
155
310
620
100 TO 900 mA
10 TO 90 mA
1.24k
1 TO 9 mA
Figure 1 This programmable current source uses BCD switches to set the
current limit.
edn080417di42391
DIANE
designideas
on the digit setting of the switch.
The circuit operates as follows: Assume that the red terminal in Figure
1 connects to a 5V power supply and
that the black terminal connects to
the power supplys ground. Assume
that the middle digit (labeled 10 to 90
mA) gets set to two and that the other
two digits get set to zero. The BCD
switch connects a 62V resistor from
the LM317s output to adjust pins.
The LM317 forces 1.25V across the
62V resistor, causing 20 mA to flow
from the output pin through the resistor, and to the black terminal of the
Pulse-width modulator
has digital control
zero. The last input of the multiplexer does not connect, so the final input
selection becomes independent of the
PWM output. The design uses all the
intermediate input selections of the
multiplexer.EDN
In this Design Idea, the total put becomes zero because the setting
time period of an output pulses time and clearing time become nearly
width is 16 times the pulse
width of the input clock.
11
OUT
The input clock connects
5V
1
2
13 741S393
to a binary counter (Fig5V
24
ure 1). The output of the
5V
24
1
12
binary counter then goes
14
9
16
2
NC
to a decoder. The decoder
3
23
3
8
scans the signal such that
22
7
4
741S393 4
1
5
21
5
6
the first output of the de6
20
5
6
coder goes to an invert5V
4
7
er gate and then to the
3
8
7
2
741S154
14
counter. The output of
1
3
4
2
9
MC14067
the counter then goes to
10
23
7
11
22
one as soon as the signal
21
13
to the counter goes from
14
20
zero to one and then from
15
19
one to zero.
16
18
15
17
17
The multiplexer de5V
codes the output pulse
10 11 14 13
19 18 12
4 8
12
widths time to be in the
A B C D
on state. The first output
10k
INPUT
of the demultiplexer sets
7
3
555
the output of the coun6
10k
ter, and the next outputs
2
clear the output of the
1 5
C
0.01 F
47 F
counter. The multiplexer, a 14067, selects the
clearing signal. Upon the
0th input of the multiFigure 1 In this digitally controlled pulse-width modulator, the period of the output is 16 times
plexer, the PWM (pulsethe pulse width of the input clock.
width-modulator) outedn080626di42321
DIANE
designideas
64 points, the 720kHz input sine wave
rotates several times from 0 to 3608.
The AD5227 acts as a potentiometer,
in which A and B are the extremes and
W is the wiper.
This example uses IC2, a PIC16F84
microcontroller with a crystal frequency of 20 MHz. This microcontroller has
a theoretical potential performance of
5 MIPS and should serve many purposes in PLL (phase-locked-loop) circuitry. You could use any microcontroller or even an FPGA to control the
AD5227.EDN
Microcontroller controls
analog phase shifter
Nick Ierfino, IGS Technologies, Montreal, PQ, Canada
R2
10k
R1
10k
INPUT
FREQUENCY
5V DC
2
3
5V DC
6
RA0
RB0/INT
7
18
IC
2
RA1
RB1
1 RA2 PIC16F84
8
RB2
9
2 RA3
RB3
10
3 RAL/TOCK1
RB4
11
RB5
16
12
OSC1CLKIN RB6
13
15
OSC2CLKOUT RB7
4
MCLR
14
VDD
17
C2
33 pF
Y1
20 MHz
C3
33 pF
CLK
VCC
C1
1
LF353
PHASESHIFTED
OUTPUT
5V DC
FCENTER=1/(2RC).
7
IC3 CS
AD5227
6
3
A
B
5
4
GND
W
2
UD
5V DC
Figure 1 A PIC16F84 sets the resistance of the AD5227 digital potentiometer, precisely controlling the phase shift of the
output with respect to the analog input.
edn080529di42611
DIANE
Devices (www.analog.com)AD8253
monolithic instrumentation amplifier
is digitally programmable with voltage
gains of one, 10, 100, and 1000 (Reference 1). This IC has high bandwidth at lower gains, but you inevitably sacrifice this bandwidth when the
designideas
15V
100 nF
IN
IN
IC1
A 5
AD8250 0 A1 7
VREF
2
10 WR 9
6
3
4
IC3
A 5
AD8250 0 A1 7
VREF
2
10 WR 9
6
3
IC2
A 5
AD8250 0 A1 7
VREF
2
10 WR 9
6
3
100 nF
OUT
DGND
5 OR
3.3V
15V
5
LOGIC A0
INPUTS A1
G0
IC4
SN74AHC1G32
G1
IC5
SN74AHC1G08
G2
100 nF
R e fe r e nce s
AD8253 10 MHz, 20V/ms, G51,
10, 100, 1000 iCMOS Programmable Gain Instrumentation Amplifier,
Analog Devices, 2007, www.analog.
com/pr/AD8253.
2 AD8250 10 MHz, 20V/ms, G51,
2, 5, 10 iCMOS Programmable Gain
Instrumentation Amplifier, Analog
Devices, 2007, www.analog.com/pr/
AD8250.
1
A0
A1
G0
G1
G2
0
1
0
1
0
0
1
1
0
1
1
1
0
0
1
1
0
0
0
1
0V
A1
A0
A1
A1
0 1
0 1
0 0
1 1 A0 0 1 A0 0 1
G0
G1
G2
1: HIGH
0: LOW
Figure 1 Although comprising five IC packages, this digitally gain-programmable instrumentation amplifier reaches a typical bandwidth of 1.9 MHz at a
gain of 1000 and thus covers the megahertz range at any of the programmable
gains of one, 10, 100, and 1000.
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
80 Control system uses
The advent of instrumenta- tors. Moreover, the value of the relation amplifiers with digital gain tive permittivity of the plastic package
switching offers obvious advantages, and that of the silicon chip are higher
such as board-space saving, higher re- than that of the air. As a consequence,
liability because of fewer solder joints, the field strength of the electrical comand lower total cost. These valuable ponent of any stray field penetrating
features stem from the fact that the into the chip is lower than that in the
gain-setting networks
integral surroundings.FIGURE 1
STEVEareEDN080320DI4225
parts of the monolithic ICs. This feaBecause the gain-setting circuitry is
ture makes these IC amplifiers much inaccessible directly, a digitally gainless sensitive to stray electromagnetic programmable amplifier is a black box.
fields because the area of internal resis- However, the simple fixture in Figure
tors is a negligible fraction of the pre- 1 can help to evaluate some of the statviously used discrete gain-setting resis- ic characteristics of these ICs. The fixVS
15V
VREF
10V
IN
OUT
GND
IC1
REF01
1
R1
99.5k
0.1%
R2
100
0.1%
8
4
DUT A0 5 7
A
AD8253 V 1
REF 2
WR
10
9
6
3
DGND
RF1
470k
RF2
GOLD-PLATED
470k
PINS
AND SOCKETS
100 nF
V
100 nF
VS
15V
Figure 1 Comprising a handful of components, this circuit allows you to perform your own, independent testing of basic static properties of digitally gainprogrammable amplifiers.
designideas
trically and remain at the VS potential.
The DUT uses all permutations of the
binary values at A0 and A1 logic (Reference 1). The corresponding voltage
gains are one, 10, 100, and 1000.
The evaluation procedure involves
measuring the output voltage of the
DUT with resistor R1 both connecting
to and disconnecting from the output of
IC1. Thus, you obtain an output voltage
of the gain times 10.02 mV and 0V for
all voltage gains. The 0V output voltage has a nonzero value because of the
input-voltage offset; this voltage might
seem high at first glance. However, any
fraction of a millivolt of the input-volt-
steve uses
EDN080301DI4122 figure 1
Control system
LabView and a PCs parallel port
designideas
Figure 2 This LabView VI (virtual instrument) controls the operation of a parking lot.
INPUT 3
INPUT 4
INPUT 5
INPUT 7
INPUT 6
DB25
(a)
INCREMENT
DECREMENT
LIMIT
edn080306di4222a
FEEDBACK
(b)
DIANE
LATCHED OUTPUT
(c)
DISPLAY
CONTROL
AND
LIMIT
LATCHER
FEEDBACK 2
(c)
(a)
ITERATIONS
SENSOR IN
FEEDBACK 1
SET
FLIP-FLOP
ITERATION
Q NOT
RESET
edn080306di4222c DIANE
(d)
(d)
(b)
Figure 3 These VIs change the inputs to a low state (a), determine a limit for the number of cars in the parking lot (b), work
as a latch-on-release circuit (c), and act as a flip-flop (d).
edn080306di4222b
DIANE
edn080306di4222d
DIANE
designideas
tivate the sensors. The VI in Figure 3b
determines a limit for the parking lot,
allowing incrementing and decrementing the number of cars parked. This VI
also drives a user-oriented display and
the shift-register connectors, feedback
and iteration, on a while loop. The
VI in Figure 3c works as a latch-on-release circuit; it generates a pulse upon
an iteration when the circuit releases
the high state on any of the input signals. The VI in Figure 3d works as a
flip-flop. The VI in Figure 4 allows
switching from automatic to manual
mode. Feedback and iteration terminals connect to shift registers, so the
latches and the flip-flops inside the VI
work correctly.EDN
FEEDBACK 1A
FEEDBACK 1B
FEEDBACK 2A
FEEDBACK 2B
GO
OUT
IN
MODE
FEEDBACK 5B
FEEDBACK 4B
FEEDBACK 4A
FEEDBACK 3B
FEEDBACK 3A
FEEDBACK 5A
INPUT 7
INPUT 6
INPUT 5
INPUT 4
INPUT 3
GO SIGNAL
STOP SIGNAL
INCREMENT
AUTOMATIC
ITERATION 4
ITERATION 3
ITERATION 2
ITERATION 1
edn080306di42224
C1
0.01 F
4
C1 S1
FF1 R1 1
Q1
5
D1 2
Q1
5V
D2
12
FF2 R2 13
9
Q2
10
S2
8
Q2
C2 VCC 14
GND
7 11
C2
0.01 F
14
7
10
CP0
DIANE
V Gopalakrishnan,
Indira Gandhi Centre for Atomic Research, Kalpakkam, India
74LS74
ITERATION 5
MANUAL
General-purpose components
implement USB-based
data-acquisition system
R1
R2 100k
1M
DECREMENT
11 Q3
74LS90
12
Q0
1
CP1
5
VCC
C4
0.01 F
R3
5V
6
DOUT
7
CS
8
SCLK
3
SHDN
VDD 1
MAX187
REF
VIN GND
2
5
5V
C3
0.01 F
4
+
C7
4.7 F
+ C
8
4.7 F
C5
0.01 F
IP
CLK
QA
QB
QC
74LS164 Q
D
QE
5V
QF
14 VCC
QG
7
GND
ANALOG
INPUT
QH
CLR
8
3
4
5
6
10
11
12
13
9
24
23
22
21
20
19
18
17
D0
D1
D2
D3
D4
D5
D6 DLP-USB245M
D7
USB
CONNECTOR
TO PC
16
RD
13 RXF
15
WR
2
3 10 11
C6
0.01 F
5V
Figure 1 This circuit performs a serial-to-parallel conversion of serial-ADC data and transfers the data to the USB port of
a PC.
designideas
dlpdesign.com), you can communicate
with the peripheral device through the
USB port of a host computer. You can
write your own program to read and
write the data through this module or
simply download free test-application
software available from DLPs Web
site. Additionally, you could download
National Instruments (www.ni.com)
LabView serial-read and-write VIs (virtual instruments).
Writing a dummy block of data from
the host computer to the buffer of the
DLPUSB245M generates a spike at
the modules RXF pin, which triggers
the D flip-flop, FF2 of the 74LS74. The
flip-flops Q2 pin initiates the conversion cycle of the MAX187 serial ADC
from Maxim (www.maxim-ic.com) by
pulling down its chip-select pin. The
ADCs end-of-conversion cycle causes
a low-to-high transition from its DOUT
pin, which triggers the other D flip-
3 TO
5.5V
2.2 F
6.3V
VCC
40 TURNS
AWG #30
HIGH-VOLTAGE
OUTPUT
0.1 F
250V
BAV21
40 TURNS
AWG #30
LX
0.1 F
250V
0.1 F
250V
MAX1605
LIM
GND
0V
FB
30V
1N4148
FIVE TURNS
AWG #26
365k
0.1 F
250V
5.76M
Figure 1 Obtaining feedback from a low-voltage secondary winding, this highvoltage supply generates 500V with low quiescent current.
pin and shifts it into the 74LS164 serial-to-parallel shift register at the rising
edge of the next SCLK. The MAX187
needs nine serial-clock pulses to shift
valid 8-bit data. This circuit uses only
8 bits of the 12-bit ADC. If the circuit
requires all 12 bits, then you must connect all NAND gates at the appropriate outputs of the binary counter to
generate a reset signal by its 13th clock
pulse, and you must make the shift register larger.
The serial data from the ADC converts to parallel data in the serial-toparallel shift register; a WR (write)
signal to the DLP-USB245M then
transfers this data to the PC. This action is a complement of the CS signal
from Q2 of the 74LS74. The DLP-USB245Ms RXF pin generates a trigger
to initiate the conversion cycle and
clears the previous data of the shift
register.EDN
designideas
520
500
480
OUTPUT
VOLTAGE 460
(V)
440
INPUT CURRENT
420
400
2.5
600
5
OUTPUT VOLTAGE 4.5
4
3.5
3
3.5
4.5
5.5
500
2.5 INPUT
CURRENT
2
(mA)
1.5
1
0.5
0
80
OUTPUT 300
VOLTAGE
(V)
200
60
INPUT
CURRENT
(mA)
40
100
0
50
150
200
0
250
(electromagnetic
interference) and cir- achieve lower output ripple.EDN
MIKE
EDN080626DI4236FIG3
MIKE
cuit parasitics can present problems.
The circuit needs careful PCB (print- R e f e r e n c e
ed-circuit-board) layout, along with fil- 1 30V Internal Switch LCD Bias
tering, decoupling, and shielding. The Supply, MAX1605 data sheet,
high-voltage output has approximately Maxim, October 2003, http://
1% ripple. You can add an RC or an datasheets.maxim-ic.com/en/ds/
LC filter in series with the output to MAX1605.pdf.
100
20
INPUT CURRENT
100
400
120
OUTPUT VOLTAGE
sion and to operate with a single supply. In this configuration, the DAC
acts as a digitally programmable resistor, and the DACs code changes the
effective resistance between the input
voltage and the IOUT1 output-current
terminal of the DAC. Figure 2 shows
a practical implementation using one-
VIN
IOUT1
A1
VOUT
A1
EQUIVALENT TO
IOUT2
RFB
VOUT
RFB
Figure 1 This simple circuit avoids a phase inversion and operates with a
single supply. In this configuration, the DAC acts as a digitally programmable
resistor.
edn080320di42331 DIANE (in 4-3 folder)
designideas
Wire the split-feedback
age rises with the voltage on
5V
resistors, R FB and R 1, to
IOUT1A. As this voltage inproduce a composite-feedcreases, the on-resistance of
5V
back resistor equal in value
the switches becomes large
A1
VOUT
to the DACs ladder impedand indeterminate, leading
VIN
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
In many applications, the frequency-conversion steps comprise a buffer, preferably with some
extra voltage gain; a mixer; and some
filtering. Instead of including an amplifier in front of the mixer, you can
easily integrate the mixer function
with the amplifier. A low-cost implementation uses an amplifier with a
power-down-disable feature. When a
square-wave local oscillator drives the
disable pin, a square wave at the oscillators frequency multiplies the input
signal, and frequency conversion takes
place.
The circuit in Figure 1 uses an Analog Devices (www.analog.com) lowcost, 300-MHz, rail-to-rail AD8063
amplifier. The test circuit comprises
a noninverting-op-amp circuit, which
drives a load of 4 kV. The two resistors
in the feedback loop regulate the voltage-conversion gain. In the test circuit, the voltage gain is 20 dB. How-
78 Tester cycles
system-power supplies
80 Touch-activated timer switch
14
5V
120
LOCAL OSCILLATOR
IN
sounds an alarm
16
5V
220 nF
OUT
91
AD8063
RLOAD
4k
2k
18k
10
VOLTAGECONVERSION 8
GAIN
6
(dB)
4
2
0
220 nF
10
20
30
40
50
60
70
12
DIANE
designideas
Simple blown-fuse indicator
sounds an alarm
Vladimir Oleynik, Moscow, Russia
IN
78L05
*ST
OUT
COM
INPUT
4 TO 30V
78L05
OUT
C1
0.1 F
HCM1206X
IN
COM
BC547
Q1
D1
1N4148
F1
D3
LED
Figure 1 When fuse F1 blows, the transistor biases on, sounding the buzzer
and powering D2.
RLOAD
2k
1/2W
D2
BLINKING
LED
edn080417di42381
R1
1k
1/8W
into power socket J1. The output voltage of this circuit from socket J2 then
connects to the system board to perform the power cycling. The 12V supply passes through resistors R5 and
R6, which limit the current flowing
through relay switches S1 and S2.
During start-up, the contact of relay
S2 is normally closed, allowing the
12V supply coming from R6 to pass to
DIANE
designideas
The system board remains powered up
for approximately 45 sec. During the
on time, capacitor C1 discharges slowly through R2, Q2, and R8. C1 turns off
transistor Q2 once the voltage across
J1
R6
160
R5
160
R7
470
POWER-SUPPLY
JACK
2B
D1
1B
S2
D2
2A
OPTOCOUPLER
Q2 2222
C1
4700 F
R8
75
S1
1A
R1
36k
R2
36
VIN
VDC ADAPTER IN
R4 2222
470
Q1
R3
4.7k
VOUT
VDC
12V
VOUT
VDC
J2
17-SEC 45-SEC
OFFONTIME
TIME
MALE
POWER
PLUG
POWER-SUPPLYJACK SOCKET
SYSTEM-TEST
BOARD
Figure 1 This simple and inexpensive power-cycle circuit uses just a few components.
edn080417di42401
DIANE
mil-wide strip of dual-sided PCB (printed-circuit board) between the negative pole of the battery and the spring
contact of the battery holder (Item A
in the figures). Q3 is a low-threshold
MOS transistor that connects between
the two sides of the strip and serves as
the switching element (Figure 1). C1
is a 0603 X7R ceramic-chip capacitor, and R1 is a 0603 chip resistor. You
mount Q3 and all associated components near the upper edge of Item A.
You insert a narrow strip of thin brass,
Item B, in series with the positive pole
of the second cell. You connect it to
the circuit with a piece of thin, flexible
wire. Touch contacts C and D comprise
short strips of self-adhesive copper tape
that you attach outside the battery
compartment. Thin and flexible wires
connect C and D to the circuit.
Q1, Q2, and C1 form a monostable
flip-flop. When the switch is off, C1
designideas
does not charge, and both Q1 and Q2
are off. When you momentarily touch
both C and D with bare fingers, current through your hand charges C1
to the threshold level of Q2. Both
Q2 and Q1 turn on, discharging C1
through Q1 and your conductive fingers. The voltage level at the gate of
Q2 is then close to the battery voltage. After you remove your fingers,
the leakage through the internal gate
protection of Q2the zener diode in
the figurescauses the voltage at the
gate of Q2 to slowly drift lower until it
reaches the threshold level of approximately 1.3V. Q2 exits conduction and,
with Q1, causes a regenerative action
to quickly turn off Q3.
The switch remains off until you
again touch C and D. Item E is an optional contact similar to C and D. If
you touch E and D, the switch turns
off. Using a value of 0.01 mF for C1,
you obtain a delay of approximately
one hour. Because the gate leakage is
on the order of a few picoamperes, you
must clean the circuit with a flux solvent and then coat it with a drop of
wax or epoxy resin.
In some cases, you might want to be
able to adjust the timing of the switch.
The circuit in Figure 2 provides that
option. It uses a tiny microcontroller in
an SOT-23 package. Listing 1, which is
available in the Web version of this Design Idea at www.edn.com/080710di1,
contains the touch-activated timer
switch. Items A, B, C, and D are the
same as those in Figure 1. When the
switch is off, the PIC10F200T microcontroller is in sleep mode and consumes practically no power. When you
simultaneously touch contacts C and
D, the level at Pin 1 of IC1 goes high,
and the microcontroller starts to tally
the time that Pin 1 remains high. After
0.5 sec, the buzzer sounds a short beep.
The buzzer then sounds two, three, and
four fast beeps in 0.5-sec intervals. By
immediately releasing contacts C and
D after hearing any number of beeps,
you can set the switch for 30 seconds,
30 minutes, four hours, and eight hours
of operation, respectively. The choices of operating times are arbitrary; you
can modify the code in Listing 1 to
whatever fits your application. Jump-
100k
100k
Q1
DTA115EU
2SK3019
Q2
D
C1
0.01 F
R1
100k
E
A
Q3
NDS331
Figure 1 In parallel with the cells of a battery-powered device, this analog circuit
disconnects the battery after a delay. Touching contacts C and D with a finger
turns on the switch, connecting the cells to the load. The components fit inside
the battery compartment.
edn080417di42261
DIANE
C1
0.01 F
C2
0.1 F
IC1
PIC10F200T
R1
4.7M
1
GP0 GP3
VSS
VDD
6
5
3 GP1 GP2 4
BUZZER
J1
A
Q1
NDS331
designideas
er switch J1 is optional. If you leave it
open, touching C and D turns it off.
Short-circuiting J1 disables this option,
and the switch will turn off only at
the end of the programmed time. As
is the case with the analog implementation, you mount all components except the buzzer at the edge of Item A.
The buzzer is a small piezoelectric element with a resonant frequency of 4
kHz and can easily fit inside the battery
compartment.
In some cases, you may not have
access to the negative contact of the
battery holder. The circuit in Figure
3 addresses this situation. It is essentially the same as the circuit in Figure
2, except that you place Item A in series with the positive pole and attach
B to the negative pole of the battery.
A P-channel MOS transistor acts as
a switch, and you modify the microcontrollers program to provide a low
level to drive Q1. A comment in Listing 1 indicates the proper line of code
for the options in either Figure 2 or
Figure 3.EDN
NDS332
Q1
C
D
C2
0.1 F
C1
0.01 F
IC1
PIC10F200T
R1
4.7M
1
2
3
BUZZER
GP0 GP3
VSS
VDD
6
5
GP1 GP2 4
J1
Figure 3 This circuit addresses the problem of a lack of access to the negative
contact of the battery holder. It is essentially the same as the circuit in Figure
2, except that you place Item A in series with the positive pole and attach B to
the negative pole of the battery.
edn080417di42263
DIANE
designideas
Edited By martin rowe
and Fran Granville
High-voltage, high-frequency
amplifier drives piezoelectric
PVDF transducer
D Is Inside
58 Microcontroller detects pulses
58 Sample-and-hold amplifier
R17
1k
VIN
R19
5.6k
D1N4148
VCC
D1N4148
VCC
R8
1k
IC2 OUT 6
3
LM7171AIN
V
4
2
VEE
R e fe r e nce
1 Duggal, Bipin, High-voltage amplifier drives piezo tubes, EDN, Dec 7,
2004, pg 100, www.edn.com/article/
CA484492.
VH
MJE340
QMJE350
VEE
R16
1k
Q4
7
V
IC3 OUT 6
3
LM7171AIN
V
4
VH
R9
10k
R18
5.6k
Q5
R7
270
MJE350
Q3
Q14
Q1
QMJE350
R15
22k
R6
220
R4
1k
R11
1
R25
2.2
R5 VB1
1k
R12
1
R26
2.2
Q6
MJE340
VH
Q13
Q2
QMJE350
VB1
VOUT
QMJE350
VH
Figure 1 This high-frequency, high-voltage amplifier can drive the capacitive load from a PVDF (polyvinylidene-fluoride)
piezoelectric transducer.
edn080501di42421
DIANE
designideas
Microcontroller detects pulses
Abel Raynus, Armatron International, Malden, MA
5V
GREEN
5
1
PB0
IRQ
15
PULSE OUTPUT
DEVICE
UNDER
TEST
PASSES
RED
OTHER OUTPUTS
PB1
14
FAILS
CONTROL SIGNALS
MC68HRC908JK1
2
INPUTCONDITION
GENERATOR
Figure 1 This 8-bit, low-end microcontroller detects pulses from LEDs, yielding
a simple tester.
ternal logic-control signal, which enables the A1, B1, and A2 voltage followers. VINA thus appears on capacitor C2,
which is ground-referenced. Capacitor
C1, which is temporarily grounded at
its upper node, Pin 9 of IC1, tracks the
VINB voltage. After a settling interval
when all of the internal logic-control
signals go inactive low, the QSB logiccontrol signal goes high. The voltage
of VC2(TS)5VINA(TS) shifts the potential at the lower node of capacitor C1 because of the enabled B3 follower. Upon the sample command, QS
is high, and the upper node of C1 is
grounded within the tracking interval.
Storage capacitor C3 therefore charges
through the B2 follower to a voltage of
VC2(TS)2VC1(TS)5VINA(TS)2VINB
(TS). The A3 follower serves as an impedance converter.
OUT
C1
10 nF
2
INB
10
10
VS
B1
B3
A2
IC2
AD8592
5
VS
A3
IC3
AD8592
C3
1 nF
VS
VS
C2
1 nF
100
nF
VS
47 nF
QD
VS
10
B2
IC1
AD8592
VS
A1
INA
VS
QS
10
2
3
VS
QDE
5
1
2
IC4
SN74AUC1G02
3
8
7
VS
9
IC6
AD8592
6
QDEB
QSB
8
4
2
5
6
IC5
SN74AUC2G08
4
VS
TS
0V
VS
VS
VS
Figure 1 The basis for the operation of this circuit is the simultaneous tracking of the VINA and VINB input voltages on capacitors C1 and
C2 and a stacking of these capacitors within the sample interval on
capacitor C3.
QDE
QDEB
GET READY
INTERNAL
TRACKING
QSB
INTERNAL QD
TRACKING
STORE
VINAVINB
QS
t
VINB2VOUTB1
0V
NOTE: LOGIC LEVELS OF ALL Q CONTROL SIGNALS ARE
THE SAME AS THOSE OF THE TOP WAVEFORM.
designideas
property of MOSFET transistors. The
same situation holds true for the bottom power transistor of the AD8592s
output stage, when the output voltage
approaches the negative-supply rail.
The turn-on time of the AD8592 is
much longer than the turn-off time.
Although the devices data sheet does
not directly specify these times, you can
see from the internal structure of the IC
that the on/off control enters almost all
of the ICs stages (Reference 1). Thus,
turn-off is fast because the turn-off of
the output stage occurs without regard
for the states of the preceding stages.
1k
4
7
10 nF
VCC
3.3V
100 nF
8
VCC
OUT
RST
shot, IC2, to produce quasistable outputs for time periods T1 and T2, which
are proportional to external timing
capacitance: T15KR0(CS1C0), and
T25KR0CS, where K is the multiplier
factor. K is nearly independent of the
external timing capacitance when that
capacitance is more than 100 pF (Ref-
DIS
IC1
6 THR
TLC555ID
2
TRI
5
CON
GND
1
10 nF
2
15
14
R0
49.9k
C0
150 pF
CS
1A
1CEXT
1CLR
R e fe r e nce
1 AD8592-Dual, CMOS Single
Supply Rail-to-Rail Input/Output
Operational Amplifier, Analog Devices Inc, 1999, www.analog.com/zh/
prod/0,,759_786_AD8592,00.html.
100 nF
16
VDD
1Q
1B
1REXT
is approximately 0.35 msec, then it follows that the maximum sampling frequency is approximately 135 kHz. The
duty-factor of the external logic-control signal, Q, for sampling frequencies
near the value of the maximum sampling frequency should be about 0.5
(Figure 2).EDN
13
IC2A
SN74LV221AD
1Q
100 nF
1
7
2 IC
3A
8
4
GND
1Z
1Y
SN65LVDS9638D
VCC
16
1k
9
10
49.9k
2B
VDD
2Q
IC2B
SN74LV221AD
2CEXT
2Q
11
2CLR
GND
8
6
NOTES:
1
CS IS A CAPACITIVE SENSOR 400 pF.
2
USE A STANDARD-CATEGORY 5E,
100 CABLE FOR DATA TRANSMISSION.
2A
2REXT
1
5
3 IC
3B
6
4
2Z
2Y
RJ45
CONNECTOR
12
150 pF
Figure 1 This compact capacitive-sensor-interface-circuit design permits great flexibility; you can easily integrate it into a
miniature sensor head near the measurement point.
VO1 = VH
Rs
T1
,
TP R f + R s
Equation 2
VCC
1Y
RT1
100
and
100 nF
8 1
2
7 IC4A
4
1Z
VCC
2Y
RT2
100
2Z
RJ45
CONNECTOR
6
5
V01
CF
220 nF
RS
150k
220 nF
150k
SN65LVDS9637D
1
IC4B
VO2 = VH
RF
20k
20k
V02
Figure 2 At the terminal, IC4 converts the signals it receives from the interface
to LVTTL levels and then feeds them to a set of passive filters.
Rs
T1
,
TP R f + R s
Rs
T2
,
TP R f + R s
SN54LV221A, SN74LV221A:
) 1folder
Equation 2
VO2 = VH
Rs
T2
,
TP R f + R s
designideas
Edited By martin rowe
and Fran Granville
D Is Inside
72 Circuit adds functions
R2
4.7M
Q1
IRF530
C1
0.1 F
S1
C2
1 nF
R2
4.7M
Q1
SI4490DY
R3
470k
C1
0.1 F
S1
C2
1 nF
to a monostable multivibrator
76 Piezoelectric driver finds
digital three-phase-waveform
synthesis
DIANE
designideas
the slow change in gate voltage as a
change in lamp brightness. Any leakage is inside and external to Q1. You
may be able to detect a change in
lamp brightness within a few seconds.
But, even if you dont notice it, some
change of voltage will occur. If you tap
S1 several times at intervals of a few
seconds, the lamp will soon toggle be-
VCC
VCC
VCC
3
TRIGGER
INPUT
4
J
PR
CLK 74LS112
2
CL
15
1
2
A
B
NAND Y
15
NEXTCEXT
13
14
Q
CEXT
74LS123
3 1
A
4
2
B CLR Q
3
VCC
63 GATES
............
INVERTING
VCC
1
INVERTING INVERTING INVERTING INVERTING INVERTING
3
QA
4
QB 5
74LS393
QC
2
6
CLR
QD
A
11
QA
10
QB 9
74LS393
QC
12
8
CLR
QD
13
INVERTING
Figure 1 By adding counters and an oscillator to the output of a monostable multivibrator, you can generate any number of
output-gate pulses.
designideas
interval of 1260 msec. When the input-trigger pulse goes to the active low,
Pin 1, of the JK 74LS112 flip-flop, the
falling edge of the input-trigger pulse
activates the flip-flop to set Q. Because the default condition of Pin 2 of
the NAND gate is at a high level, the
transition at the output pin, Pin 3, of
the NAND gate passes on to the active-low input of the monostable multivibrator at Pin 1. The falling edge of
the output pulse of the NAND gate
triggers the monostable multivibrator
to generate the first gate pulse of predefined gate width.
Subsequently, when the Q output
pulse of the monostable multivibrator
makes a transition from high to low,
the rising edge of the complementary
output pulse of the monostable multi-
(a)
(b)
Figure1 At a frequency of 4 kHz, which is closer to the resonant frequency, residual oscillations last longer (a) than the
resonant frequency with 3.2 kHz (b).
designideas
longer (Figure 1). You can determine
the actual resonant frequency by trying
all the frequencies around the nominal
resonant frequency and comparing the
duration of residual oscillations.
In this design, a Microchip (www.
microchip.com) PIC18F452 microcontroller drives a piezoelectric element through its I/O pins, RB4 and
RB3 (Figure 2). Initially setting RB3
to zero and RB4 to one and toggling
them after each half-period generates an alternating piezoelectric voltage (VP) with a 0V-dc bias. After applying 10 cycles, RB3 is kept low, and
PIC18F452
MICROCONTROLLER
RB4
VP
RB3
crocontroller or a DSP for digital control. You can perform this synthesis by
using conventional analog techniques
(Reference 1) or DDS (direct digital
synthesis). Digital techniques provide
IC1
AT91SAM7X
R1
22
PMC PCK0
22
TK
SSC
TF
TD
SYSCLK
C6
100 nF
63V
VSSA
15
VDDA
13
VSSD
5
VDDD
4
BCK
22
WS
22
DATAJ
APPL0
APPL1
APPL2
APPL3
14 VOUTL
VA
RA
16 VOUTR
VB
RB
RF
REFDAC
IC2
UDA1330ATS
APPSEL
DIGITALSUPPLY
VOLTAGE
R3
1
R2
1
C5
100 nF
63V
SYSTEM
CLOCK
higher stability and the ability to incorporate frequency, phase, and amplitude adjustments. For applications
requiring 16-bit or higher-resolution,
three-phase-signal synthesis, DDS involves the use of a microprocessor or a
DSP to interface multiple DACs. This
approach uses not only a lot of devices,
but also supporting components and
board space. Although one device can
have multiple-output serial-controlled
DACs with four, eight, 32, or more
DIGITALSUPPLY
VOLTAGE
ANALOGSUPPLY
VOLTAGE
C1
100 F
16V
+
11
10
9
8
12
IC3
VC
VREFDAC
C7
100 nF
63V
C4
47 F
16V
Figure 1 This scheme implements three-phase DDS (direct digital synthesis) with few components. The code in the ARM
processor provides the ability to incorporate arbitrary frequency, phase, and amplitude adjustments with 16-, 18-,
or 20-bit resolution.
edn080501di42441
DIANE
designideas
channels, the DACs provide
tine) whenever the output
few bits at the expense of the
buffer is empty. Listing 2,
number of channels. Hence,
also in the Web version of
using multiple-output DACs
this article, shows how to
is an unappealing approach.
achieve an ISR to send the
Alternatively, you can use
data. IC2 provides voltage
shift registers or switchedoutputs VA and VB, which
capacitor filters, but this apare two of the three signals
proach also involves a high
for a maximum amplitude
parts count, and the lack of
of 5V p-p, but with an offset
phase and amplitude adjustof 2.5V. You can derive the
ment makes this method
third channel as a function
Figure 2 Traces 1 and 2 show the voltage outputs from the
inappropriate for high-resoof the other channels. You
DAC. Trace 4 is the third channel that an inverting, summing
lution DDS (Reference 2).
can easily implement this
op amp provides.
In contrast, stereo DACs are
operation using a single inreadily available. Their widespread use troller, IC1; one stereo-DAC, IC2; and verting, summing op amp, IC3, and the
has produced low-cost, high-quality one op amp, IC3 (Figure 1). The ARM 2.5V DAC reference for canceling the
components. For example, the NXP AT91SAM7X256 code in Listing 1, offset. In this case, RF5RA5RB510 kV
UDA1330ATS has an I2S-serial da- available in the Web version of this De- for obtaining unity gain, and you could
ta-format interface; word lengths of sign Idea at www.edn.com/080807di2, add a potentiometer in the inverting
16, 18, and 20 bits; and sampling fre- generates a table containing the cosine pin for an exact offset cancellation if
quencies of 8 to 55 kHz (Reference function of the desired resolution and the resistors dont match exactly.
3). These features make the DACs at- length. The table produces cos(1
Figure 2 shows the synthesis of the
tractive for three-phase DDS with few 2/3p) and cos(22/3p). The ARM three-phase waveforms. For further excomponents.
microcontroller sends the data using planation and to access the referencThis Design Idea implements DDS I2S-serial format by using interrupts at- es to this article, go to www.edn.com/
techniques using an ARM microcon- taching the ISR (interrupt-service rou- 080807di2.EDN
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
functions
R3
10k
R1
100k
R2
100k
C1
220 pF
R4
10k
C2
220 pF
R6
2.7k
R5
150
Q3
BC557C
BT1
1.5V
SINGLE
CELL
BC550C
Q1
Q2
OPTIONAL
BC550C
Q4
BC550C
L1
150 H
FLASHING INPUT
D1
LED
80 sequential-LED outputs
DIANE
designideas
cycle always starts from zero. If this
is not the caseif you reduce TH too
much, for examplethe inductor current increases on each cycle until Q3
goes out of saturation, and the final
current value becomes unpredictable
because it depends on Q3s dc gain.
Optional transistor Q4 allows the circuit to flash the LED when a low-fre-
IC provides
versatile toggle
functions
C1
2.2 F
R1
22k
R3
47k
OUTPUT 1
SIMPLE TOGGLE
R2
22k
CD40106B
Louis Vlemincq,
Belgacom, Evere, Belgium
R6
47k
S1
CD40106B
V
R7
47k
R8
10k
R10
47k
R5
470k
OUTPUT 2
TOGGLE WITH
UNCONDITIONAL
RESET
C3
47 nF
C
OUTPUT 3
SET AND RESET WITH
PRIORITY TO RESET
CD40106B
OUTPUT 4
TOGGLE AND
CONDITIONAL
SET/RESET
CD40106B
R9
470k
C4
47 nF
D1
R12
47k
R13
10k
E 1N4148
CD40106B
R11
470k
OUTPUT 5
TOGGLE AND
CONDITIONAL
RESET AND
UNCONDITIONAL
SET WITH PRIORITY
TO RESET
C5
47 nF
C2
47 nF
B
R14
1k
COMMON
SET
R4
470k
mike
designideas
Output 2 has the same toggle function as Output 1 but also includes a direct reset. Output 3 works only in a set/
reset mode; the position of R8 determines the priority state. Output 4 also
has a toggle action, but you can set or
reset it to a state opposite that of Output 3. Output 5 works in a similar manner, except it allows only a condition-
STEVE
EDN080501DI4243 FIGURE 1
R e fe r e nce s
Zero Drift, Digitally Programmable
Instrumentation Amplifier, AD8231,
Analog Devices Inc, 2007, www.
analog.com/en/prod/0,2877,AD8231,
00.html.
2 10 MHz, 20V/s, G51, 2, 5, 10
iCMOSR Programmable Gain Instrumentation Amplifier, AD8250, Analog Devices Inc, 2007, www.analog.
com/en/prod/0,2877,AD8250,00.
html.
1
2.5V
15V
16
NC
IN A
1
VS
A2
A1
A0 CS
OUT A
IC1
AD8231
REF
IN
IN A
15 14 13
12
1
11
4
IC2 A
5
0
AD8250
A1 7
VREF 2
WR 9
10
6
3
100 nF
NC
10
SDN
5
4
IC3 A
5
0
AD8250
A1 7
VREF 2
WR 9
10
6
3
100 nF
OUT
100 nF
OUT B
6
DGND
IN B IN B
2.5V
15V
0V
Figure 1 By cascading an autozeroed instrumentation amplifier having a gain of 23 and instrumentation amplifiers having
gains of five, you get a decade-gain instrumentation amp whose dc performance is much better than that of monolithic
decade-gain instrumentation amps.
designideas
Four DIPs provide as many as
80 sequential-LED outputs
14
Q0
13
Q1
ENA
Q2
15 RST
Q3
Q4
IC1
Q5
74HC4017
Q6
Q7
Q8
Q9
CLK
EN
RST
CLK
CO
3
2
4
7
10
1
5
6
9
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
12
D1
A0
D11
A0
D71
A1
D2
A1
D12
A1
D72
A2
D3
A2
D13
A2
D73
A3
D4
A3
D14
A3
D74
A4
D5
A4
D15
A4
D75
A5
D6
A5
D16
A5
D76
A6
D7
A6
D17
A6
D77
A7
D8
A7
D18
A7
D78
A8
D8
A8
D19
A8
D79
A9
D10
A9
D20
A9
D80
ONES ROW
R1
20k
CLK
13
ENA
15 RST
IC2
74HC4017
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
CO
DA
2
3
4
5
6
7
8
9
3
2
4
7
10
1
5
6
9
11
1
19
12
A1
A2
A3
A4
A5
A6
A7
A8
A0
TENS ROW
6V
14
R e fe r e nce
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
18
17
16
15
14
13
12
11
G1
IC3
G2 74HC540
COM
TO IC1
DB
TO IC2
R1
680
16
C0
R2
680
15
C10
R3
680
14
C20
R4
680
13
C30
R5
680
12
C40
R6
680
11
C50
R7
680
10
C60
R8
680
C70
70S ROW
RESET
SELECT ON
OUTPUT COUNT
Figure 1 This circuit provides a simple means of multiplexing the outputs of two 4017 counters for as many as 80 outputs.
DIANE
VIN
RI
20k
RF
1M
RP
18.3k
2
3
VOUT
0VOUT/VIN10.
OP37A
VIN
RI
20k
RF
1M
RP
22.5k
RCOM MBT-303-A
VOUT
10VOUT/VIN0.
OP37A
RCOM MBT-303-A
H11
H12
R1
E
R2
H21
H22
H11
HGND
H12
E
E
R1
E
R2
H21
H22
HGND
0.90R1/R21.1.
NOTES:
Set RP=20.4 k FOR A PROGRAMMABLE-GAIN RANGE
OF 5GAIN5.
VOUT/VIN=50(R2/R10.9)=0 IF R2/R1=0.9 AND =10 IF R2/R1=1.1.
0.90R1/R21.1.
NOTE:
VOUT/VIN=50(R2/R11.1)=0 IF R2/R1=1.1 AND
=10 IF R2/R1=0.9.
DIANE
edn080612di42752
DIANE
designideas
Edited By Martin Rowe
and Fran Granville
Platinum-RTD-based circuit
provides high performance
with few components
D Is Inside
72 Proportional-ac-power
controller
Equation
1 doles out whole cycles
of ac line
78 Extend monolithic program-
mable-resistor-adjustment
range
Y1
VOwith
= VREF
negative
active
resistance
The standard way of using an additional current to the sensor that
Y2
RTD (resistance-temperature- relates to the temperature you are mea- R (Y78+1-YWire
Y
Y
network
Equations for DI4264 (5 29) 0
2
3 Y4 )1 controls remote
,
detector) sensor is to include it in a suring.
With proper
Equations
for DIdesign,
4264 (the
5 circuit
29) R [ Y + SPI
peripherals
bridge followed by a differential am- can provide good linearity and stabil- 1 Y3R 2Y4 (Y0 + Y1)] + 1
EWhat are your design problems
plifier. The problem is that two non- ity over a wide range of input tempera2
1
and solutions?
Publish them here
linearitiesone from the sensor and tures. TheEquation
output voltage,
VO, depends Equation
Equation
1
and receive $150! Send your
another from the bridgeaffect the on circuit components in the followDesign Ideas to edndesignideas@
transfer function. Some approaches ing way:
are available that attempt to avoid the
Y1
R reedbusiness.com.
= R 0 (1 + + 2),
VO = VREF
R
Y
(
Y
+
Y
)]
+
1
Equation 3
ferential amplifier but provides neither 1
3
2 4 0
1
design guidelines nor results (Refer- where YI51/R
and
I=0
to
4.
in
the first and doing some rearrangeEquation
2
I
Equation
ence 4). This Design Idea fills the gap.
For
positive 2temperatures, a second- ments, you get:
Although circuit analysis is somewhat degree polynomial of the following form
B
V0 = 2
K = f ()K,
complex, performance is good, and the can approximate RTD characteristics:2
C
R
=
R
(
1
+
),
0
circuit uses few components.
R = R 0 (1 + + 2),
Besides the platinum RTD, RU, the
where B, C, and K are constants and
circuit features only six precision resis- where R0 is sensor resistance at 08C, f(U) is a function of temperature. Figtors, an op amp, and a voltage refer- a and b are coefficients, and U is the ure 2 shows the general shape of f(U).
ence (Figure 1). R4, the extra resistor measuredEtemperature.
The output voltage depends linearly
quation 3
for the differential amplifier, delivers
After
replacing
Equation
3 the second equation on temperature when f(U) is as close
as possible to a conVREF
stant. This situation
R2
B
is most true around
V0 =B
=
f
(
)
K
,
V0 = 2 2BKC = f ()K,
R1
R1
the minimum point
Bf()
C
of f(U).
Some additional
VO
/
relations
provide
that
the
output
volt, C
age is 0V at temperature 08C, the conR4
R0
R
R3
version coefficient
is 10 mV/8C, the
minimum of function f(U) is in the
Figure 1 This generic RTD circuit needs few
Figure 2 The general shape of function f(U)
middle of the meacomponents.
varies with temperature.
surement span, and
edn080529di42641
DIANE
edn080529di42642
DIANE
designideas
the current through RU causes
adjustment at 5508C to match
TABLE 1 experimental results
negligible self-heating of the
the magnitudes of the posiMeasurement range
1100 to 1600C
sensor.
tive and the negative errors.
Figure 3 shows the circuit Nominal sensitivity
You can also extend the tem10 mV/C
that meets these requirements. Basic accuracy (nonlinearity)
perature range to start from
Well below 61C
The sensor is a DIN-IEC 751
21008C instead of 08C withAmbient-temperature effect
0.05C/10C
platinum RTD. Microsoft (www.
out exceeding the basic non0.1C/V
microsoft.com) Excel software Power-supply effect
linearity. The three-lead confits 13 points of 0 to 6008C in Cable effect (three-lead connection)
nection to the sensor signifi0.7C/V
steps of 508 from the RTDs cal- Power-supply range
cantly reduces the influence of
612 to 618V
ibration table. The spreadsheet
connection-cable resistance,
9 and 13 mA
software determined R0 to have Consumption (600C input)
RC, on accuracy.
140 to 185C
a value of 100V, a to have a Operating temperature
Table 1 shows the results of
value of 3.908310238C21, and
evaluating this circuits perb to have a value of 25.801310278C22 coefficient is 50 ppm/8C. You can use formance with a calibrated, precisionwith an R2 factor of one.
two trimming potentiometers, VR1 and decade resistance and a calibrated,
All the circuits resistors have toler- VR2, to independently adjust zero and 4.5-digit multimeter with readings
ances of 0.02%, and the temperature span readings. You should perform span at ambient temperatures of 24 and
688C; power supplies of 612, 615,
R2
VR1
and 618V; and cable resistances of 0
2.46k
100
and 5V.EDN
15V
2
REF01H
R1
10k
6
5
VR2
100k
OP07C
R0
100
4
RC
15V
R1
10k
R e fe r e nce s
VO
RC
RC
R3
2.67k
15V
R4
28.4k
Figure 3 The full circuit needs trimming potentiometers VR1 and VR2 to adjust
zero and span, respectively, and a three-lead cable for sensor connection.
RC is the cables resistance.
EDN080529DI42643
DIANE
Proportional-ac-power controller
doles out whole cycles of ac line
Richard Rice, Oconomowoc, WI
In industrial and process control, it is often necessary to accurately control the temperature of a
process. You control most heating elements using the bang-bang methodturning the power to them on and
off at a predetermined setpoint. The
temperature of the heated substance
constantly hunts back and forth around
the setpoint. You can achieve much
designideas
R2
100k
VIN
R1
100k
CONTROL VOLTAGE
0 TO 2V
R3
49.9k
VCC
C1
0.22 F
IC1A
TL072
OP AMP
R4
100k
IC
R5
71.5k
VCC
R14
1k
R8
100k
TL072
IC2A
LM319W
VCC
OP AMP
4
R18
1k
COMPARATOR
VCC
D1
IC3A Q1
74HCT74
D FLIP-FLOP
1
R1
4
S1 C1
D3
120V AC
8V AC
4
IC4
MOC3011
Q1
2N3906
SCR1
C2
0.1 F
250V
LINE 2
VCC
5V
IN
D1
COMPARATOR
C3
470 F
D2
R10
100
R13
180
60-Hz CLOCK
16V AC
CT
500 mA
T1 8V AC
Q1
R12
180
IC2B
LM319W
R11
180
1
LED1
8
R16
4.7k
LINE 1
R23
390
R9
1k
R7
100
1B
R17
100k
R15
100k
LINE 1
TO AC LOAD
(HEATER)
VCC
R6
249k
D4
LINE 2
C6
220 F
IC4 OUT
LM317
ADJ
R19
750
R20
243
R21
750
ADJ
IC5 OUT
IN
LM337
C4
33 F
R22
243
C7
33 F
C5
0.1 F
C8
0.1 F
VEE
5V
Figure 1 This ac controller borrows from a sigma-delta converter to output a number of whole cycles of ac-line power according
to an input-control voltage.
designideas
Extend monolithic programmableresistor-adjustment range
with active negative resistance
W Stephen Woodward, Chapel Hill, NC
A variety of solid-state, in-circuit-programmable replacements exist for the traditional electromechanical trimmer potentiomHGND
R1ADJ
e
REFFECTIVE =
RRC =RRM.
R1
R1
V
RM=MINIMUM
PROGRAMMED
RESISTANCE.
VC
RF
VMVC=0,
IF RC=RM.
RF
VC=ICRC.
RC
IC
VREF
edn080515di42591
DIANE
output accordingly. If the current data bit is the same as the previous bit,
toggle IC3s Data 0 output. The circuit
automatically generates a clock pulse
each time and requires only one 1-Wire
command for each data bit sent. When
data transmission is complete, send a
final 1-Wire command to set the IC1
output high.
This circuit allows a 1-Wire network
to control a remote temperature display, but similar techniques can provide an interface to I2C (inter-integrated-circuit)-compatible devices and
to other SPI peripherals, such as ADCs
and DACs. You can also produce a bidirectional-data capability by adding
a fourth DS2405. Note that the SPI
data rate and updates to the peripheral
are relatively slow, but speed is not an
issue for many remote-monitoring applications.EDN
designideas
5V
R1
4.7k
R2
4.7k
PIO
IC2
DS2405
DATA
GND
IC4B
IC4A
DATA 0
DATA 1
CS
PIO
IC1
DS2405
DATA
GND
R3
4.7k
R4
100
74HCT86
PIO
IC3
DS2405
DATA
GND
74HCT86
IC4C
74HCT86
C1
0.01 F
1-WIRE
5V
DIGIT ZERO
CS DIN CLK
DIGITS
ONE TO SIX
DIGIT SEVEN
SEG A
V+
SEG B
R5
SEG C
ISET
SEG D
IC5
MAX7221
SEG E
SEG F
SEG G
SEG DP
GND
GND
DIG 7
DIG 6 . . . DIG 1
DIG 0
Figure 1 Three 1-Wire switchesIC1, IC2, IC3; three XOR gates, IC4; and the associated components enable a 1-Wire
network to control this display through the SPI peripheral IC5.
edn080710di42871
DIANE
designideas
Equation 1 Edited By Martin Rowe
and Fran Granville
Equations
for
R 2 DI4268 (5 29) File 1 (1 6
VFB = VOUTNOM
,
R 2 + R1
Equations for DI4268 (5 29) File 1 (1 6
Equation 1
readerS SOLVE
DESIGN
PROBLEMS
Equation
2
Equation 1
R2
VFB = VOUTNOM
,
VOUTNOM R 2 + R1
R1 = R 2
1 . R 2
VFBV=
,
FBVOUTNOM
D Is Inside
R 2 + R1
Equation 2
Equations for DI4268 (5 29) File 1 (56
1 A
6)better approach to designing
an
RTD
Equation 3 interface with a spreadBrian Vasquez, Maxim Integrated Products, Dallas, TX
sheet Equation 2
V
0
.
6
V
tive-transient-voltage
specs
R
connection to the circuit (Figure 1). verters output so that the maximum,
VFB = VOUTNOM
Equations
for DI4268
(52 29), File 1 (1 6) Equation 3
VOUTNOM
, (1) R1 Design
0.6V1 = 2 R 2 .
R
+
R
R1 = R 2
2 1 1.
reedbusiness.com.
using the I2C bus.
VFB
2 feedback
1
.
1
2
(4)
I R1 = I R 2 + I DS4404 ,
within the output-voltage range that
FB
1.8VV
Equation
5
(3) Equations
R
the current DACs data sheet speciwhere IR1 isfor
theDI4268
current (5-29)
throughFile
R1, 1IR2(7-12)
Equation
1 = R 2 3 1 = 2 R 2 .
0.6V
Equation
6 through R2, and IDS4404 is
fies as sinking or sourcing voltage deis the current
Equation
7 the DAC.
Equation
5
pending on whether you are sinking or Summing
the 3currents at the feedback the
current
into
Equation
(5)
sourcing current. You should also ver- node derives the current to make the
I DS4404 = I R1I R 2 .
ify the input impedance of the dc/dc output voltage increase to the maxiV 7
V
VFB
Equation
1.8V
I R1 = OUTMAX
; I R.2 = FB , (6)
Equation
R1 = VRCC2 4 1 = 2 R 2 .
I DS4404
=
I
I
R1 R 2
R1
R2
0.6V
VOUTMA
XVFB VFB .
I
=
1.8V
where
VOUTMAX
DS4404
is theRmaximum output
R
R1 = R 2
1 = 2 R 2 .
61
2
VCC
voltage. Equation
R3
R4 0.6 V
I R1 = I R 2 + I DS4404 ,
VOUTMAXVFB VFB
I DS4404 = Equation
6
R . (7)
DS4404 SDA
Equation 4
R1
TO I2C MASTER OR
2
OR
VIN
VOUTMAXVFB
V
VOUT
MICROPROCESSOR
DS4402 SCL
I
=
; I R 2 = FB ,
DC/DC
Equation
5
You
can
simplify
Equation
7
by
solvR
1
Equation
8
A0
2
R1
CONVERTER
IR1
R1
Equation 4DETERMINES I C
R and
R2
ing Equation 1 for
then substiIDS4404
CIRCUIT
A1
2
SLAVE ADDRESS
VFB
VOUTMAX
VFB
I
=
I
+
I
,
OUT0
R1
R2
DS4404
tuting, which
FB
I R1 =yields:
; I R2 =
,
VFB
R1
R2
FS0
Equation
8
I
=
I
I
.
IR2
R2
MAXIMUM
V
V
S4404RFS RDETERMINES
1 R2
I R1D=
I R 2 + I DS
I DS4404 = OUTMAX OUTNOM . (8)
FULL-SCALE
CURRENT
4404 ,
R1
FOR DS4404
Equation 5
In margin percentage, you can express
Figure 1 The circuitry to the right of the dashed line adds margining capability.
VOUTMAXVOUTNOM
IEquation
.
DS4404 = 8 as:
Equation 5
R1
Equation 6
I DS4404 = I R1I R 2 .
Equation 9
edn080529di42681
9V
R1
OUTNOM MARGIN
R2
Equation
6
designideas
Equation 9
I DS4404 =
VOUTNOM MARGIN
, (9)
R1
REGISTER
SETTING.
V
MARGIN
mumIoutput voltage.
This resolution is , mine the DS4404s
output current
as a
OUTNOM
I OUT (REGIS
STER SETTING)=
DS44049=
Equation
more than adequate for this
function
of register
setting:
I OUT (REGIS
STER
SETTING)=
R1example.
Equation 13
You could, for instance, begin by ar- STEP
I OUT
(REGIS
STER SETTING)=
SIZE
15REGISTER
SETTING.
(14)
Equation
Equation
10
STEP
SIZE
REGISTER SETTING.
bitrarily choosing the full-scale current
in the center,Vor 1.25 mA,
of the speci- STEP SIZE REGISTER SETTING.
OUTNOM MARGIN ,
I
=
fied
Note
that 15
this register setting
DSrange
4404 and then performing all the
Equation
I FSS does
R1
Equation
15
EquationInstead,
10
STEP
SIZE=
R1 the
180
calculations.
for illustrative not include
sign bit, which selects=
NO.
OF
STEPS
R2 =
=15 = 90.
Equation
purposes,
the calculations
are shown sink
or source.
The
VOUTNO
MARGIN
2
23 DS4404 sinks curM
= and rent when
0.5the
10sign bit is zero, mak1 = endpoints of the range: 0.5
forRthe
I DS4404
R1 180 = 16.1 A/STEP,
R
180
2 mA. Analyzing the 0.5-mA case first, ingRthe
voltage
increase to the
= output
=31
= 90.
R 22 = 21 = 2 = 90.
R
180
.
8
0
.
2
Equation
you
perform
the
following
calculations
maximum
output
voltage. It sources
V110
MARGIN
2
2
1
OUTNO
M
Equation
16
R 2 =Equation
=
= 90.
= 720.
R1 =repeat forthe
3 2-mA case. =
and then
current
when
sign bit is one, mak2 the
2 14
0.5 10 I DS
4404
Using Equation 9 and solving for R1 ing the output voltage decrease toward
1.8 0.2
yields:
theEquation
minimum16
Equation
16output voltage.
= 720.
VOUTNOM
MARGIN
3
Equation 11
Now,
you
can
repeat
the calculations
I
(
REGIS
STER
SETTING)=
0
.
5
10
R
=
=
OUT
Equation
16
VOUTNOM MARGIN (10)
1
I DS4404
for the 2-mA case.
R1 =
=
I DS4404
STEP
REGISTER
V SIZE
MARGINSETTING.
1.8 0
.2MARGIN
R1 = VOUTNOM
11
Equation
OUTNOM
= 180. =
R1 =
=
0.2
3
R 1.8720
4404
VOUTNOM
3MARGIN
2 II DS
10
=
720
.
R2 = 1 =
=
360
.
DS4404
3
R
=
=
1 Equation 15
20.5 210
1.8I DS
0.2
(15)
1.8 04404
.2 = 180.
Equation 172 1033 = 180.
R1 720
12.8 10
03
.23
R 2 = 11
=
= 360.
= 180.
(11)
Equation
33
2
2
VREF
31
1.23
10
R21
180
R
=
=
(16)
Equation
= 90.
FS R 2 = 17 =
Equation
Equations
for full-scale
DI4268 (5-29)
File 1 (13-18)
ToEquation
calculate12
the
resistance,
I FS17
4
2
103
2
2
Equation
use the formula and the reference volt17 31
VREF
1.23
V = 4766
R
720 data sheet:
R FS =31
31
=
4.17.23
k.
age
3
R FS = 4IREF
=
R 2in=the1 DS4404s
=
= 360.
4
2
10
3
FS
VIREF
31
1
.
23
Equation
4
2V 21231
1.23
R FS Equation
= FS 16 = 2 103
(17)
R FS = REF
=
31I FS
3
31 = 47664 24.710
Equation
13
k.
I FS
4 0.5 10
(12)
Equation
4766 4.7 k.
4 = 18
31
4 = 4766 4.7 k.
31 V
31
1
.
23
, 065 =19 k.
4 VOUTNOMI FS
MARGIN
R FS4 == 19REF
STEP
= =
Equation
12I
R1SIZE=
= 18
Equation
4 0.5 103
FS
Equation 18 NO.IOF
STEPS
I FSS
DS4404
(18)
STEP SIZE=
Equation
31 NO. OF STEPS =
2 10318 1.8 I FS
= 19, 065 19 k.
0./2STEP. =
IAFS
STEP
SIZE=
=
64
.
5
= 180=
.
(13)
43
STEP31
SIZE= NO. OF3
3
0.5 V10
31
1.23
I FSSTEPS
2 OF
10
NO.
STEPS =
R FS = REF = 16.=1 A/STEP,
STEP
SIZE=
3
2 10R3 and
31I FS
4 0.5 103
Comparing
for
the
OF
2 10 1= NO.
64.R
5 2
A /STEPS
STEtwo
P. cas.5
A / STEofP.0.5 or
3 = 64
where 31
RFS is the full-scale resistance, eswith
a
full-scale
current
31
Equation
17
2 31
10
Equation
= 64is.5the
Amore
/ STEP.
1914
, 065
19 k.and IFS is 2 mA0.5
VREF
is the=reference
voltage,
mA
attrac31 V
4
31
1.23 are
the full-scale current.
tive value because
the
resistances
R FS = REF
=
R =
=
= 90.
sion 2and 2stopped
2 short of using Excel
to calculate the resistor values. You can
generalize this proposed approach such
that
you can16select any type of RTD
Equation
and any temperature range, but this
Design Idea limits the details to the
following example.
V download
MARGIN
You
the worksheet
R1 =canOUTNOM
=
I
(Figure 1) from DS
the
Web version of
4404
1.8 0.2
2 1033
Equation 17
= 180.
Equation 18
this Design Idea at www.edn.com/
I FS as an
080918di1.
plot the chart
STEPYou
SIZE=
=
XY diagram, and youNO.
create
trend
OFthe
STEPS
line on the
2 chart
103using a second-order
64.5appear
A / ST
P.
polynomial, which=will
onEthe
31 Design Idea includchart. The original
ed this information. Unfortunately, you
cannot access the coefficients you generate in this way from the worksheet,
so you cannot directly calculate the resistor values.
To access the polynomial coefficients, you can use Excels LINEST
designideas
array formula. It prescribes a specific
way of entering data; without that protocol, Excel will not provide the desired results. LINEST returns a number of regression statistics; to allow for
these statistics, you must first highlight
the range on the worksheet on which
you want the regression results. Only
the polynomial coefficients are important in this example, so this Design
Idea limits the returned results by selecting block B24:D24 for those three
values. You then enter the following
line into the formula bar at the top of
the worksheet:5LINEST(G5:G21,E5:
F21,,TRUE).
Simultaneously press the Control,
Shift, and Enter keys rather than just
Enter to terminate this command. The
coefficients will then drop into the selected range. Excel will add the braces,
{ }, to indicate the array formula. The
input range of the function in the formula above includes the Vt2 column,
allowing LINEST to create a secondorder polynomial equation.
You can enter user-selected values
as set numbers, providing easy and
quick modification and an immediate
update of the calculated values. These
values include the current source
through the RTD, the reference volt-
R e fe r e nce s
Villanucci, Robert S, Design an
RTD interface with a spreadsheet,
EDN, Feb 7, 2008, pg 57, www.edn.
com/article/CA6526816.
2 Kagan, Aubrey, Excel by Example: A Microsoft Excel Cookbook
for Electronics Engineers, Elsevier/Newnes, May 2004, ISBN
0750677562.
1
1k
2
comparator with hysterrelease voltage, VT2, of the trigQ1
esis by taking advantage of
ger as VT25VREF3(11R13R2/
BCW61
its inner voltage reference
(R11R2) 31/R3).
TL431 C 3
R1
R2
along with few additional
When the battery voltage
SHUNT
51k
100k
components. You can use
is less than the release voltREGULATOR
1
R
this comparator with hysage, the cathode voltage of the
2
teresis, like a Schmitt trigTL431 goes to its high level
A
R3
11k
ger, as a simple battery monto the battery voltage. Transisitor (Figure 1). You calcutor Q1 turns off, and LED1 does
late the threshold voltage,
not shine. LED1 turns on again
Figure 1 A shunt regulator and associated circuitry funcVT1, of this comparator as
when the battery voltage, after
tion as a Schmitt trigger, lighting LED1 when the battery
V T1 5 V REF 3 (11 R 1 /R 3 ),
recharging, exceeds the threshis fully charged.
where V REF, the internal
old voltage.EDN
DIANE
designideas
Power supply meets
automotive-transient-voltage specs
Francesc Casanellas, Aiguafreda, Spain
VBATTERY
5V
Q1
IRFR9220
D3
S1G
R1
10k
Q2
BC857B
R2
4.7k
D1
BZX84B4V7
MICROCONTROLLER
PORT
Q3
BC847B
5V
OPTIONAL
D2
BZX84C18
R4
100k
C1
470 F
6.3V
R5
10k
R3
220
Q4
DIANE
Amplitude
(V rms)
20
1.470
50
1.472
100
1.472
200
1.473
500
1.473
1000
1.473
2000
1.472
5000
1.473
10,000
1.473
20,000
1.472
designideas
Edited By Martin Rowe
and Fran Granville
Use an LM317 as
0 to 3V adjustable regulator
D Is Inside
56 Alarm monitors rotational speed
of dc motor
VIN
INPUT RANGE:
5V < VIN <10V
2
IC1
LM317T
C1
0.1 F
R1
620
GND
C2
10 F
TANTALUM
VOUT
OUTPUT RANGE:
0V < VOUT <3V
GND
R2
OUTPUT
1.5k ADJUSTMENT
R4
510
R3
82
Q1
BCW33
VSS RANGE:
5V < VSS <10V
D1
RED
R5
15
R6
ZERO
100 ADJUSTMENT
VSS
edn080821di43211
60 Microcontroller inputs
DIANE
designideas
tor R2. Calculate the output voltage as
follows: VOUT5VREF(11R2/R1)2VR3,
where VREF is the reference voltage of
IC1 and VR3 is some compensative voltage of resistor R3. You should establish
this voltage to equal the reference voltage for its compensation. In this case,
VOUT5VREF(R2/R1). With R2 having a
value of 1.2 kV, this circuit found use
as the equivalent of a typical battery
R e fe r e nce s
1 LM317 3-Terminal Positive Adjustable Regulator, Fairchild Semiconductor Corp, June 2005, www.
fairchildsemi.com/ds/LM/LM317.pdf.
2 LM350 3-Terminal 3A Positive Ad
justable Voltage Regulator, Fairchild
R2
150
C2
0.47 F
M
1
FAN
CONNECTOR
FAN
C1 R
3
10 nF 1k
R1
13
R9
120k
R6
15k
R4
39k
11
CLK1
12
RES
BC849
BC849
Q2 R
7
120k
Q1
D1
1N4148
BC849
Q3
R5
470
10
R10
51k
R
C 9
R12
1.5k
IC1
CD4060
6
Q7
BC849
Q4
R11
680k
R8
15k
Q14
D2
1N4148
C3
6.8 nF
12V
BUZZER
TO COLLECTOR
OF Q5 FOR
RELAY SWITCH
3
R13
120k
Q5
BC849
TO ATX POWERSWITCH
CONNECTION
WITHOUT RELAY
Figure 1 This circuit provides an optional audible alarm after a time-out when a brushless-dc fan motor slows down. Then,
after a second time-out, the circuit powers down the PC.
edn080724di42851 DIANE
PLACED IN THE 8-7 FOLDER
designideas
voltage mode. As the cell voltage gets
closer to this 4.2V terminal voltage, the
current through D1 drops, and at 15 to
40 mA, both LEDs illuminate.
Tests measured this range for several 2N3904 transistors. Testing with
2N4401s gave a lower range of 4 to 18
mA. When the current drops below
about 15 mA, Q1 turns off D2. The voltage across D3 now rises above its forward-voltage threshold, and the green
charging-completed LED lights.EDN
J1
OPTIONAL
CHARGINGCOMPLETE
LED
5
C1
1 F
R2
2.4k
C2
1 F
SINGLE
LITHIUM-ION
BT1
CELL
J4
NEGATIVE
2N3904
Q1
D3
J3
POSITIVE
D1
1N4001
NOTES:
R2 SETS MAXIMUM CHARGE CURRENT TO 400 mA.
CURRENT IS 400 mA WHILE CHARGING AND
ALMOST ZERO WHEN CYCLE COMPLETES.
J2
1.25 TO 2.5V
edn080710di42911 DIANE
(PLACED IN 8-7 FOLDER)
220 H
RA
1k
8
7
VCC
DISCH
RB
10k
6
2
RESET
555
CMOS
TIMER
THRESH
TRIG
GND
1
C
470 pF
CHARGE
Q > 90
OUTPUT
CTRL
5
0.01 F
DISCHARGE
edn080710di42901
VSS
PROG
RED
CHARGING
LED
GREEN
CHARGINGCOMPLETE
LED
GND
R1
300
D2
IC1
1 CE
MCP73812
VBAT 3
4
VDD
5V DC
DIANE
designideas
creates voltage pulses of 23V using
a 1.25V NiMH cell with seven connected LEDs.
The circuit uses a CMOS timer because it functions on low voltagesin
this case, as low as 1V. A single white
LED rated at 9300 mcd maintains its
brilliance down to this low voltage.
The circuit works for 192 hours using
a 2000-mAHr-rated NiMH cell. The
output of the timer is a 4.5-msec pulse
repeating at a 222-kHz rate. Although
you can use the circuit to power any
LED, it works best using high-brightness, high-power LEDs rated at 3000
mcd or higher. Obviously, the higher
Microcontroller inputs
parallel data using one pin
Rex Niven, Forty Trout Electronics, Eltham, Victoria, Australia
QQ
R3
1k
9 7
QH QH
D2
BAT54
VCC
GND
IC1
GP0/AN0
PIC12F683
GP1/AN1
GP4/AN3
GP5
GP3/MCLR
GP2/AN2
R2
100k
CK
IC3
74HC165
R4
1k
1
C2
2.2 nF
IC2A
PL
74HC14
D1
BAT54
R1
10k
C1
3.3 nF
IC2B
CP
VCC
RP1
PULLUP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
16 15 14 13 12 11 10 9
74HC14
S1
1
2 3 4 5 6 7 8
Figure 1 Careful adjustment of the RC time constants allows a microcontroller to input a serial-data stream using a single
I/O pin.
edn080626di42721 DIANE
designideas
pulses shift the data so that the 8 bits
appear in sequence at the shift-register
output, QQ.
If the microcontrollers data direction briefly changes to input with
high impedance, this shift-register
data dominates because of the relative values of R1, R2, and R3, with R3
being a much lower value. The highimpedance state must exist only for a
time less than the R1C1 time constant
(Figure 2). The microcontroller now
reads the single bit of data. The action
of three differing periods generates
three functions: load, clock, and data
read. The time the microcontrollers
need to change port direction, read
the pin data, and reset the pins direction to output determines the timing.
For example, a 1-msec microcontroller
requires 10 msec.
To avoid spurious CP pulses, this time
constant must be less than 0.33R1C1, so
R1C1 could be 30 msec and R2C2 could
be 200 msec. These settings would
allow a complete 8-bit read in about 1
msec. To achieve faster operation, re-
2.5R1C1
2.5R2C2
HIGH
IMPEDANCE/READ
< 0.3R2C2
CK
QQ
CL
PL
R4C1
Figure 2 The high-impedance state must exist only for a time less than the R1C1
time constant.
place the RC delays with a precision rect sequencing of LD and CP. Diodes
retriggerable monostable multivibra- D1 and D2 quickly discharge the capactor, such as NXPs 74HC123, and logic itors to reset the delay function of
gates. You can expand the scheme with R1C1 and R2C2.EDN
more shift registers to read dozens of
signals.
R e fe r e nce
edn080626di42722 DIANE
1
Note that internal PLACED
logic in
the
IN 8-7
FOLDER Niven, Rex, RC lowpass filter
74HC165 shift register prevents the expands microcomputers output
CP signal from shifting data when LD port, EDN, June 21, 2007, pg 74,
is active. Resistor R4 ensures the cor- www.edn.com/article/CA6451248.
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
58 Multiplexing technique yields a
edn081002di_id 57
10/2/2008 1:31:46 PM
designideas
tion. The advantages of the circuit
include the fact that its dc signals
ensure that theres no noise and that
24V
ENCODED OUTPUT
P1
P2
P3
P4
24V
C1
0.33 F
35V
POWER
CONNECTOR
GROUND
24V
R9
510
R14
510
LED POWER
R6
510
3
R3
2k
R2
2k
VREF
8
IC
3A
1
V
1
C2
VI IC4 VO 2 REF
R10
0.01 F
REF3040
10k
10V
GND
VREF/2 0.1%
3
R12
R11
10k
10k
0.1%
0.1%
R1
40k
1%
VREF/2
AD8532
2
VREF
VOUT
IC1
78L05SMD
GND
2 3 6 7
VREF
IC2A
AD8606/
2 8602
R5
510
VIN
R4
10k
0.1%
R7
10k
0.1%
3B
AD8532
6
C3
3.3 F
10V
ENCODED
OUTPUT
IC2B
AD8606/
6 8602
VREF/2
IC
to noise, no reset circuits are necessary. Best of all, the design requires no
programming.EDN
R8
10k
7 0.1%
VREF/2
R13
10k
0.1%
CONNECTOR FOR
OPTICAL BREAK
WORM ENCODER
R15
10k
5%
LED POWER
GROUND
5V
R16
10k
5%
Figure 1 This application uses IC4, a REF3040 voltage reference, which has an output tolerance of 0.2% yet costs only
approximately $1.
DIANE
Charlieplexing as a method
of multiplexing LED displays
has recently attracted a lot of attention because it allows you, with N I/O
lines, to control N3(N21) LEDs
(references 1 through 5). On the
other hand, the standard multiplexing technique manages to control far
fewer LEDs. Table 1 lists the number
of LEDs that you can control using
Charlieplexing and standard multiplexing by splitting the available
number of N I/O lines into a suitable
edn081002di_id 58
10/2/2008 1:31:46 PM
designideas
Table 1 No. of LEDs and duty cycle
No. of
I/O
lines
Multiplexingcontrolled
LEDs
Duty cycle
with multiplexing (%)
Charlieplexingcontrolled
LEDs
Two
Two
100
Two
50
Three
Three
100
Six
16.67
Four
Four
50
12
8.33
Five
Six
50
20
Six
Nine
33
30
3.33
Seven
12
33
42
2.4
Eight
16
25
56
1.78
Nine
20
25
72
1.38
10
25
20
90
1.11
Figure 3 This graph plots the voltage at node PR1 for various supply-voltage
values when the input to the transistor pair is floating.
P1
P2
Voltage at node
PR1
VCC
VCC
VCC
VCC/2
VCC/2
VCC/2
P2
Voltage at
node PR1
LED that
turns on
VCC
L3
VCC
L2
L1
L4
VCC/2
None
edn081002di_id 60
10/2/2008 1:31:48 PM
designideas
5V
5V
0.1 F
(RESET) PB5
IC1
(XTAL2) PB4
TINY13V (XTAL1) PB3
(SCK) PB2
8
(MISO) PB1
VCC
4
GND
(MOSI) PB0
VIN
1
3
2
7
6
5
5V
82
P1
P2
AIN
P3
P4
P1
22k
82
BC557
470
P2
PR1
BC547
470
82
BC557
470
BC547
470
D1
D2
P2
D3
P3
D5
D6
P4
D7
D8
P2
BC547
470
82
P2
PR2
82
D4
PR3
82
P1
PR1
BC557
470
P3
PR2
82
4.7k
5V
D9
D10
P3
D11
D12
P4
D13
P3
D14
P3
82
D15
D17
D16
P4
P3
D18
PR3
82
D19
D20
D21
P4
P4
D22
D23
D24
P4
Figure 4 With the GuGaplexing technique, controlling 24 LEDs requires only four I/O lines and three sets of transistors.
age. The
GuGaplexing
edn081030di42744
DIANE implementation uses an AVR ATTiny13 microcontroller. The analog input voltage
connects to Pin 7 of the ADC input
of the Tiny13 microcontroller.
The control program for the AT
Tiny13 microcontroller is available
with the Web version of this Design
Idea at www.edn.com/081016di1. The
source code is in C and was compiled
using the AVRGCC freeware compiler. You can modify the source code to
display only one range of input voltage
between 0 and 5V. For example, it is
possible to have a linear-display range
of 1 to 3V or a logarithmic scale for
input voltage of 2 to 3V.EDN
R e fe r e nce s
Lancaster, Don, Tech Musings,
August 2001, www.tinaja.com/glib/
muse152.pdf.
1
a standard force-sense lab power supply (Figure 1). The circuit requires an
additional power supply for the ICs
and a separate control voltage. The
feedback signal to the force-sense sup-
edn081002di_id 62
10/2/2008 1:31:48 PM
designideas
1.2
VIN=1V
1
FORCE-SENSE
POWER SUPPLY
0.8 VIN=0.75V
F S S F
VS H U NT = 0 TO 100 mV.
1
8
RSHUNT
100m 2
RS
RS
V
MAX4172
6
OUT
GND
5
IOUT
0 TO 1A
0.6
LOAD
CURRENT
(A)
0.4
VIN=0.5V
VIN=0.25V
0.2
LOAD
0
0
50
100
150
LOAD RESISTANCE ()
POWER
SUPPLY
MAX4493
9V
5
4
1
3
10k
0.03 F
IN
0 TO 1V
CONTROL
VOLTAGE
Figure 2 This graph shows load current versus load resistance for the circuit in Figure 1.
IREF
0 TO 10 mA
ROUT
1k
edn081002di_id 64
10/2/2008 1:31:49 PM
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
62 Digitally programmable
5V
0.05%
(UNTRIMMED)
VIN
AD586L V
O
8 NOISE
REDUCTION
TRIM
GND
The basis of the DACs 32-bit resolution is the summing of two 16-bit
PWM signals by analog switches S1
and S2 and precision resistor network
R2 through R6. The DACs monotonicity and DNL are theoretically infinite,
and, in practice, the only limit is the 1to-216 ratio of R2: (R61R51RS2-ON) and
R3: (R61R41RS2-ON). Typical accuracy
of 0.1% resistors yields a DNL of approximately 0.1 ppm527 bits.
The less-than-0.1V output impedance of the AD586 reference and the
130-dB CMR (common-mode rejection) of chopper-stabilized zero-drift
amplifier A1 mostly limit INL. R7 suppresses a potential contribution from
asymmetry in RS1-ON, yielding the typical INL of approximately 0.3 ppm522
bits.
PT0
R2
15.4
0.1%
X1
R1
88.7k
C2
1 F
X0
MAX4053A
MAX4053A
2
X0
X
ADC
in Excel spreadsheets
C1
0.056 F
9 S1
R7
4.99
NOTES:
PT0, PT1, AND PT2 ARE 200-Hz, 16-BIT PWMs.
PT0 HAS A HIGH-ORDER, 16-BIT DAC SETTING.
PT1 HAS A LOW-ORDER, 16-BIT SETTING.
PT2 IS A SYMMETRICAL (50-TO-50-RATIO)
SQUARE WAVE.
VOUT=5V(PT0DUTY216+PT1DUTY)/216.
PT2
R3
100 F 15.4
6V
0.1%
6
5 A1
13 X1 A
V1
15
X1 A
S2
10
MAX4053A
16
VCC
8
GND
7
VEE
15V
8
4
LTC1151
200
VOUT
R4
1M
0.1%
R5
1M
0.1%
1 F
14
MAX4053A
5V
R6
9200
0.1%
12 X0
LTC1151
2
1
3 A2
LTC1151
11 S3
0.1 F
EN
6
5V
0.1 F
0.1 F
0.1 F
15V
5V
Figure 1 This DAC circuit sums two 16-bit PWM signals using precision analog switches to achieve 32-bit resolution.
edn081003di_id 61
edn080626di42771
DIANE
10/16/2008 1:48:44 PM
designideas
of the LTC1151 A1 and A2 op amps
and the charge-injection performance
of the MAX4053A S2: approximately
0.4 ppm, or 23 bits.
The precision of the AD586L 5V
reference, which is 6500 ppm untrimmed, limits absolute accuracy. If
STEVE
EDN080515DI4256 FIGURE
1
Digitally
programmable
instrumen-
tation amplifier offers autozeroing
Marin tofka, Slovak University of Technology, Bratislava, Slovakia
VOLTAGE GAIN
LOW
THREE
HIGH
10
A1
16
NC
IN
IN
IN A 2
VS
IC1
A2
A1
A0 CS
OUTA
A1
AD8231
REF
IN A 3
NC
15 14 13
VS
12
11
100 nF
10
SDN
5
OUT
OUT B
16 15 14 13
NC
IN A 2
VS
IC2 A
2
A1
11
OUTA
A2
AD8231
REF
IN A 3
NC
VS
CS
A0
12
10
SDN
5
0V
OUT B
6
100 nF
2.5V
Figure 1 The autozeroed instrumentation amp, digitally programmable for voltage gains of three and 10, can help you to overcome the current inavailability
of monolithic ICs for this task.
edn081003di_id 62
10/16/2008 1:48:45 PM
designideas
these pins sets the gain to 10. Note that
three approaches the square root of 10,
or approximately 3.16. You can therefore consider it as roughly thegeometric center of a decade.EDN
R e fe r e nce s
CS
1
10
11
12
13
14
15
CLK
HIGH IMPEDANCE
DOUT
NULL
BIT
HIGH
IMPEDANCE
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 2 The DTR line produces the CS signal that frames the conversion process. The CS signal must be low while
the conversion is in progress.
edn081003di_id 64
10/16/2008 1:48:45 PM
edn081030di43662
DIANE
designideas
make some changes in the hardware
and software. The changes necessary to the hardware are obvious, and
you may need to change the software
source code of the application to correct the for () loop statement according to the timing diagram of the
selected part.EDN
Microsofts (www.microsoft.
com) Excel helps engineers
with calculus and graphics to solve
problems. But engineers often have to
perform bitwise operations, too. Figure
1 shows the bitwise operations tables.
The bitwise functions work for decimal values. If you need to use hexadecimal or binary values, you must use
the Dec2Bin and Dec2Hex functions
to convert all the decimal values for
the desired format.
To install the add-in bitwise functions, you can download the ins.xla
file from the Web version of this De-
AND RESULT
0 0
0
1 0
0
0 1
0
1 1
1
OR RESULT
0 0
0
1 0
1
0 1
1
1 1
1
XOR RESULT
0 0
0
1 0
1
0 1
1
1 1
0
NOT RESULT
0
255
1
254
SHIFT RIGHT
RESULT
RESULT
DIANE
edn081003di_id 66
10/16/2008 1:48:46 PM
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
62 Oscillator uses dual-output
current-controlled conveyors
latching relays
5V
IC1A
LMC6484A
2
5V
3 X0
IC1
5
X1 74HC4053
A
S1
9
FW
5V
10 Hz
1m/SEC
C
VQ1 AT 25C
600 mV
2 mV/C.
O1
EE-SY124
BIAS
550 A
5.1k
22 F
6V
IC2
1
X1 74HC4053
A
S2
10
V3
13 X0
0.01 F
15
IC3
12
X1 74HC4053
A
S3
11
51k
0.01 F
14
400k
51k
400k
10
0.1 F
1M
IC1C
LMC6484A
0.1 F
VOUT
1V1 kW/m2.
1M
11
16
IC2
VCC
74HC4053
8
GND
7
EN VEE
6
0.33 F
V2
Q1
2N4401
14
500k
0.33 F
2 X0
0.1 F
IC1D
LMC6484A
500k
5V
IC1E
LMC6484A
AMBIENTTEMPERATURE
SENSOR
13
3.6k
FREE-SPINNING
ANEMOMETER
IMPELLER
1k
CALIBRATION
12
CW
100k
110k
1 F
IC1B
LMC6484A
V
6
5V
220k
3.6k
5V
+
22 F
6V
0.1 F
11.7m/SEC26.2 MPH1 kW/m2.
20m/SEC44.7 MPH5 kW/m2.
1m/SEC2.2 MPH0.625 kW/m2.
VREF1
LM4040CIM3-2.5V
Figure 1 This meter circuit uses a free-spinning anemometer and a diode-connected transistor temperature sensor
to measure the available wind power for green power generation.
edn081101di_id 61
10/30/2008 1:14:47 PM
designideas
fore, requires estimating air density,
which is inversely proportional to absolute temperature; measuring air speed;
and calculating a cube.
Heres how the wind-power meter
does it. Diode-connected Q1 has a bias
of 550 mA for a 258C (298K) base-toemitter voltage of approximately 600
mV and a temperature coefficient of
22 mV/8C. Thus, Q1 is a voltage reference that tracks the approximate idealgas-law temperature dependence of air
density: 20.3%/8C. Meanwhile, optical sensor O1 works with a free-spinning anemometer impeller to produce
wind-speed-proportional frequency:
FW510 Hz/m/sec. Conversion of VQ1
and FW into a 1-mV51W/m2 output
signal is then the function of the thirdorder X3Y3Z-multiplying behavior of three cascaded CMOS-switch
FVC (frequency-to-voltage-converter)
charge pumps: S1, S2, and S3.
FVC S1/IC1A generates a negative
voltage of 20.173V Q13F W; FVC
S2/IC1B generates V252V3FW50.173
VQ13FW2; and FVC S3/IC1D generates 2V 3 520.173V Q1 3F W 3 . Finally, differential inverter IC1C shifts
and scales 2V 3 to output VOUT5
VX
IY
IX
IB1
IB2
IB2
IZ
IZ
IB1
IB
VY
0.423VQ13FW351V/kW/m2.
You can conveniently calibrate the
wind-power meter in an automobile
being driven on a windless day at a
constant speed of 18.6m/sec541.5
mph566.8 kph. With the anemometer exposed to the external slipstream, adjust the calibration trimming potentiometer for an output
voltage of 4V or, for better accuracy,
to the voltage that the following formula that accommodates true air density yields: VOUT51.14V3air-pressure
millibar/(2731ambient temperature
Celsius).EDN
C2
C1
C2
C1
(b) (b)
(a) (a)
DIANE
DIANE
edn080724di42922B
DIANE
10/30/2008 1:14:48 PM
designideas
Circuits drive
single-coil latching relays
220k
VSUPP
4 TO 15V
MAXINA 5054
CMOSLEVEL
INPUT
OR
INB
MAXINB 5054
33 nF
GND
OUTB
DPDT
SINGLECOIL
LATCHING
RELAY
COMMON
VSUPP
2.7 TO 5V
VCC
IN1
INPUT
OUTA
MAXINA 5054
edn080724di42811a DIANE
MAXINB 5054
R1
33 nF
COMMON
GND
NO2
edn080724di42811c
DIANECOM2
NC1
220k
COIL
CURRENT
INB
(b)
GND
VDD
TTLLEVEL
INPUT
OUTB
DPDT
SINGLECOIL
LATCHING
RELAY
NOTES:
IF YOU REVERSE THE LOGIC, YOU MUST DO SO FOR BOTH INPUTS.
FOR TTL LOGIC, USE A MAX5054BATA.
FOR CMOS LOGIC, USE A MAX5054AATA.
(c)
INA
0.1 F
MAXINB 5054
RESET
(a)
VSUPP
4 TO 15V
INB
RESET
0.1 F
R2
OUTA
COIL
CURRENT
INPUT
SIGNAL
COIL
PULSES
MAXINA 5054
SET
OUTA
COIL
CURRENT
COMMON
INA
SET
INA
0.1 F
VDD
VDD
OUTB
DPDT
SINGLECOIL
LATCHING
RELAY
NO1
COM1
NC2
33 nF
INPUT
SIGNAL
0.1 F
COMMON
COIL
PULSES
NOTES:
USE A MAX5054BATA.
R2=(VR1)220 k,
R1=(R2/VR), AND
VR=[(VSUPP2.4V)/2.4V].
GND
MAX4684/
MAX4685
(d)
VSUPP
2.7 TO 5V
DPDT
SINGLECOIL
LATCHING
RELAY
INPUT
SIGNAL
COIL
PULSES
VCC
IN1
SET
SET
NO2
OR
COIL
CURRENT
IN2
edn080724di42811d
IN2
RESET
RESET
0.1 F
COMMON
(e)
COM2
NC1
DIANE
COIL
CURRENT
NO1
COM1
DPDT
SINGLECOIL
LATCHING
RELAY
NC2
GND
MAX4684/
MAX4685
edn080724di42811e
edn081101di_id 64
DIANE
10/30/2008 1:14:49 PM
designideas
The electronic circuitry to drive one
of these relays from logic signals can be
a half-bridge if dual supply voltages are
available or a full bridgethat is, an
H-type power driverif only a single
supply voltage is available. The need
to generate reversible-current pulses
through the two-terminal coil imposes the use of these bridge topologies.
Because the relay itself does not consume power under static conditions,
the driving circuitry should also consume minimal power under the same
conditions.
Figure 1 illustrates a variety of driving circuits, depending on the inputsignal-logic levels, their coding, and
the magnitude of the available supply voltages. The circuits in figures 1a
through c drive relays for voltages of
4 to 15V. The circuit in Figure 1c requires two separate control lines: The
set line sets the relay, and the reset line
resets it. You can code the set and reset
signals as positive (active high) or negative (active low). You must use the
levels, and the one in Figure 1b operates from TTL levels. After each transition, the signal must remain stable for
longer than the relays minimum operating time. The circuits in figures 1a
and c typically draw quiescent currents
of 40 mA, and the one in Figure 1b
typically draws approximately 50 mA.
The circuits in figures 1d and 1e are
similar to those in figures 1a, 1b, and
1c, but their supply-voltage range is 2.7
to 5.5V, and their maximum quiescent
current is only 50 nA.
Because the single-coil latching relay
has a memory of its own, you must initialize its position after power-up to a
known state, either by exercising the
input logic or by analyzing and responding to a signal from the contacts circuitry. Any of these circuits
can deliver as much as several hundred milliamps in either polarity while
pulse-driving a relay coil. You can find
technical information and data sheets
for the ICs in these circuits at www.
maxim-ic.com.EDN
edn081101di_id 67
10/30/2008 1:14:49 PM
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
60 Achieve precision temperature
R1
62 Instrumentation-amplifier-based
Q1
D1
D3
R2
Q2
D6
D5
D2
D4
tery-voltage monitor
R3
Q3
DIANE
additional cost because you can simultaneously drive N21 LEDs, thereby
reducing peak currents N21 times.
Figure 1 shows the approach for
N53 and M56, but you can use the
same criteria for different values of N;
in this case, you can simultaneously
drive two LEDs. The current-limiting resistors connect in parallel with
D1
D2
D3
D4
D5
D6
VBAT
Ground
High impedance
High impedance
VBAT
Ground
Yes
No
No
No
No
No
No
Yes
No
No
No
No
Ground
VBAT
High impedance
No
No
Yes
No
No
No
High impedance
Ground
VBAT
No
No
No
Yes
No
No
VBAT
High impedance
Ground
No
No
No
No
Yes
No
Ground
High impedance
VBAT
No
No
No
No
No
Yes
Ground
VBAT
VBAT
No
No
Yes
No
No
Yes
VBAT
VBAT
Ground
No
Yes
No
No
Yes
No
VBAT
Ground
VBAT
Yes
No
No
Yes
No
No
designideas
three microcontroller ports: the six
available when using Charlieplexing
to drive one LED at a time and three
new combinations to drive two LEDs
at a time. The microcontroller port
grounds the transistors base. This action fixes a junction-drop voltage at
the emitter and collects and sinks all
the LED currents to ground without
overconstraining the microcontroller
port, which has to sink only the transistors base current plus 0.7V per resistor. Each of the other ports set to the
R2
100k
74HC4053
2 X0
15
X
1
X1 A
S2
10
C2
0.001 F
R1
10k
10k
5V
11 S3
13 X1 A
5V
12
X
X0
74HC4053
SAMPLE
Q1
SPD50P03L
9 S1
3 X1 A
5
5V
VS
0V
TEC SPECS:
IMAX=1A.
VMAX=2V.
QMAX=1W.
DTMAX=61C.
74HC4053
VCC
GND
EN
6
5V
VS
SAMPLE
16
5V
VEE 7
0.1 F
100k
1
/10W
ENABLE
TEC
DRIVE
5V
0.47 F
50V 1M
22 F
402k
1
/10W
RT
THERMISTOR
R3
20k
1M
1/
10W
RMAX=(5VVMAX)/IMAX.
RFP30N06LE-ND
3
3W
5V
3
4
TEMPERATURE100k SETPOINT
ADJUSTMENT =
4RT AT SETPOINT.
R5
1k
SAMPLE
ENABLE
TEC
DRIVE
TEC
HEAT
SINK
SEEBECK-VOLTAGE
SAMPLE PULSE
C1
22 F
X0
74HC4053
SAMPLE
MARLOW
NL1011T
14
LT1782
1k
2200 pF
50V
SEEBECK-COMPENSATION ADJUSTMENT
R4
1k
I=IMAX TO 2.5IMAX.
Figure 1 This circuit periodically sets the thermoelectric coolers drive current to
zero, sampling the Seebeck voltage and holding it in a storage capacitor to achieve
stable temperature control with real-world heat sinks and thermocouples.
TEC (thermoelectric-cooler)
temperature-control systems
often have limited stability. The causes
of these limitations are the thermal
properties of the system, not the performance of the control electronics.
Real-world thermal-control systems
incur nonzero thermal impedances in
the heat-transfer paths between the
TEC; the thermal load, which is the
object of thermostasis; the temperature
sensorfor example, a thermistor; and
the ambient temperature.
If the ratios of these impedances
dont balance, then even perfect thermostasis of the sensors temperature
doesnt equate to adequate stability of
the loads temperature. The circuit in
Figure 1 provides a thermoelectronic
design that directly measures the heat
flux through the TEC and then uses
the measurement to better estimate
and cancel the effects of thermal impedances. Its operation is based on the
fact that the total voltage that every
TEC develops is the sum of two components: an ohmic component proportional to drive current and the Seebeck
voltage, VS, which is proportional to
the temperature difference across the
TEC and, therefore, to heat flux.
In this circuit, however, the drive
current switches to zero approximately
every 100 msec because of the asymmetrical sample-pulse waveform that
multivibrator S2/S3 generates. Each
sample pulse turns off 5V transistor Q1,
which isolates the Seebeck voltage and
allows its sampling through S1 and storage capacitor C1 to hold it. The duty
factor of the sampling pulse, which the
designideas
R1-to-R2 ratio sets, is less than 10% to
avoid significantly reducing the TECdrive capability of the circuit.
You apply the acquired Seebeck signal to the R3/R4/R5 adjustable-bridge
circuit, which empirically determines
the feedback ratio for both polarity
and amplitude to provide best stability. With proper bridge adjustment,
you can make gradient cancellation
nearly perfect over a wide range of
Instrumentation-amplifier-based
current shunt exhibits 0V drop
Marin tofka, Slovak University of Technology, Bratislava, Slovakia
B
IO
V
IO = R .
R2
R3
VOUT VOUT
=
R3
2R
5 V .
2R
R2R3=R2/3 .
Passive current shunts for mea- A is theoretically 0V, regardless of the
suring the value of current flow- magnitude and polarity of the current
Figure 2 The value of R3 is two times
ing through a relatively small-value re- flowing into the input.
that of R2 for a 0V drop at Input A in
sistor often have a full-scale voltage
The design uses the Analog DevicFigure 1.
drop of 60 mV for higher-power equip- es (www.analog.com) AD8223 instrument and 200 mV for electronic in- mentation amplifier because it has a destruments. Similarly, simple current-to- fault voltage gain of five; this value re- in Figure
1 should be high-precision,
edn080821di42972
DIANE
voltage converters, in which the mea- mains close to the ideal one with high low-temperature-coefficient types. In
sured current flows through a sensing precision. The typical gain error at the the experimental circuit with a value
resistor, often have even higher voltage default value of gain is 0.03%, and the of 20V for R1 and R2, there is an inputdrops. In some cases, however, the volt- worst-case error is 0.1% for the B-grade referred-current zero shift of 0.8 mA,
age drop between the input terminal IC (Reference 1). For gain of five and and the voltage drop at Input A varies
and the ground must be as low as pos- R1 and R2 having the same value, you by 0.27 mV at a 1-mA input current.
sible; 0Vindependent of the value can derive that the value of R3 is two Similar slope of negative-voltage variof measured currentis ideal. If your times that of R2 for a 0V drop at Input ations occurs at Input A for negativeapplication requires this feature, you A (Figure 2). Resistors R1, R2, and R3 input current. The transfer constant,
can use the current-to-voltor transresistance, of the circuit is:
VS OR VS
VS
age converter in Figure 1.
(DVOUT)/(DIIN)525R.
In this circuit, resistor R1
Thus, for instance, an input
IO
serves as a classic currentcurrent of 1 mA causes the voltsensing resistor, on which
age of 2100 mV to appear at the
A
2 7 AD8223
V
1
the instrumentation amplioutput. Because the output-cur5V
RG
6
R1 NC
OUT
fier senses the measured current capability of the AD8223 is
8 R REF
20
G
NC
100 nF
B
3
rent, resulting in the voltage 0V
approximately 2.5 times higher
5
4
drop. The instrumentation
for sinking output current than for
R2
amplifier, along with R1, not
sourcing current, the input scale
47
nF
20
V
only serves as an inverting
can be higher for positive currents
VS
current-to-voltage convertby a factor of 2.5. You can further
R3
er, but also creates a voltincrease the scales for both posi40
age through a resistive nettive and negative currents by inwork at Point B. This voltcreasing the supply voltages from
Figure 1 This instrumentation amplifier serves two
age is equal in magnitude
65V to 612V; you can also use
purposes: It forms acurrent-to-voltage converter havto a voltage drop on R1 and
12V and 25V. If your design reing atransresistance of 25R, and it exerts avoltage
has the opposite polarity to
quires an even higher input curdrop of opposite polarity at point B, resulting in a zero
DVR1. The net result is that
rent, place a precision voltage
potential at Input A, regardless of input-current I/0.
the value of voltage at Input
buffer, having appropriately high
edn080821di42971 DIANE
designideas
output-current capability, between the
output of the instrumentation amplifier and resistor R3.EDN
R e fe r e nce
Single-Supply, Low-Cost Instrumentation Amplifier, AD8223, Ana-
lation. Because the Hall-effect IC incorporates internal signal conditioning and hysteresis, no additional components are necessary to read a basic
frequency from the device, unlike with
the traditional current-transformer
method.
The circuit in Figure 2 converts the
pulses from the Hall-effect IC into a
dc voltage that the most basic voltmeter can read. The Hall-effect IC provides an open-collector output. You
need only a pullup resistor. The sensor
converts the series of generated pulses,
which the LM2917 frequency-to-voltage converter from National Semiconductor (www.national.com) converts
to a voltage. The selection of C1 and
R1 scales the output voltage in relation
to the range of frequencies that the
charge-pump section of this device will
encounter. In the case of a four-stroke,
single-cylinder engine, a range to 5000
rpm is more than sufficient.
The circuit provides an output voltage as high as 5V and requires a battery-supply voltage of 9V. Operation is
straightforward: By pressing the Halleffect IC against the spark-plug wire,
the voltage on the DVM (digital volt9V DC
IB
VB
22k
5%
1
3
2 UGN3030T
C1
0.47 F
CERAMIC
5%
Y
Z
X
VH
Figure 1 A current flowing through a semiconductor in the Y direction produces a negligible potential difference in the X direction.
edn080918di43461
470
5%
6
5
7
1
2
LM2917
8
10k
5%
3
R1
147k
1%
1 F
TANTALUM
DIANE
VOUT
1 mV/RPM
edn080918di43462
DIANE
designideas
meter) can readily interpret the revolutions per minute. Because the measurement is noninvasive, this method
can easily perform repeated measurements or analysis of multicylinder engines. Measurement of automobile
engines differs slightly. Automobile
engines have mechanical distributors
that spark on every other engine revolution. Ignition systems without distributors and with one ignition coil per
cylinder also spark on every other engine revolution.
Because there is no electrical contact with the ignition system, this circuit intrinsically provides isolation
from the high voltage. Interfacing to
microprocessors and microcontrollers
thus becomes a matter of compatible logic levels. The Hall-effect ICs
power-supply voltage is 4.5 to 24V dc,
which enables it to work with standard 5V processors as well as automotive voltages. You can interface multiple sensors to provide ignition diagnosis and timing analysis in automotive
applications.EDN
D3
5.6V
1N5232B
R1
2200
5%
LED1
WP7104IT
Q1
2N3904
R2
82
5%
D1
1N4148
D2
1N4148
Figure 1 The parts for this 9V battery-voltage monitor cost less than
34 cents.
edn081002di43091 DIANE
(PLACED IN 10-2 FOLDER)
designideas
Edited By Martin Rowe
and Fran Granville
D Is Inside
54 Simple microcontroller-
designideas
IC2
CD4053B
6V
2
12
X0
X
X1
S2
IC1D
14
LMC6064
13
0.01F
15 499k
499k
A
10
6V
6V
13
11 S3
X1
A
X
12
IC1E
LMC6064
14
IC
1C
LMC6064
9
C2
0.0015 F
IC2
CD4053B
S1 9
4
X1
X
X0
SOLAR-PANEL
INPUT
6 TO 36V,
0.1 TO 50W
499k
VQ1
IC1A
1
LMC6064
VPF
1M
IC1B
LMC6064
100 pF
C3
0.01 F
4.5 TO 36V
10 F
50V
1M
THERMALLY
COUPLED
LP
VOUT PROGRAM
16
VCC
8
GND
7
VEE
EN
R1
7.2k
R2
36k
VIN
CLOCK
SYNC
VFB
SW1
SW2
INTVCC
0.1 F
VOUT
14V MAXIMUM
2.5A MAXIMUM
PLLIN VOUT
FCB
10 F
IC3
RSENSE
LTM4607
SENSE
BUCK/BOOST
REGULATOR
SS
200
6V
RUN
ON/OFF
Q1
2N4401
IC2
CD4053B
6V
499k
1k
2N4401
IC2
CD4053B
VQ2
Q2
C1
1 F
11
10
X0
4.7 H
10 F
35V
330 F
25V
VOUT MAX=0.8(1100k/RP).
RP=R1R2.
0.007
SENSE
SGND
0.007
PGND
Figure 2 This maximum-power-point-tracking controller relies on the well-known logarithmic behavior of transistor junctions.
edn081205di4289fig2
from the solar panels negative terminal; IS1 is the saturation current of
Q1; x1 is the arbitrary gain constant,
which IC3 determines; V is the voltage input from the solar panels positive terminal; IS2 is the saturation current of Q2; K is degrees Kelvin; VPF is
the power-feedback signal; and VIP
is the calculated power-input signal.
Because k, q, IS1, IS2, x1, and 499 kV
are all constants and T15T25T, however, for the purposes of the perturband-observe algorithm, which is interested only in observing the variation
of current and voltage with perturbation, effectively, VQ15(kT/q)log(I),
and VQ25(kT/q)log(V).
The series connection of Q1 and
mike
Q 2 yields V PF 5V Q1 1V Q2 5(kT/q)
[log(I)1log(V)]5(kT/q)log(VI), and,
because of IC1Bs noninverting gain
of three, VIP53(kT/q)log(V I)Q765
mV/% of change in watts. The VIP
log (power) signal couples through C1
to synchronous demodulator S1, and
error integrator and control op amp
IC1C integrates the rectified S1 output
on C3. The IC1C integrated error signal closes the feedback loop around
the IC3 regulator and results in the
desired maximum-power-point-tracking behavior.
Using micropower parts and design techniques holds the total power
consumption of the maximum-powerpoint-tracking circuit to approximate-
designideas
Simple microcontroller-temperature
measurement uses only a diode
and a capacitor
Andreas Grn, Wedemark, Germany
MICROCONTROLLER
VCC
CHARGE CYCLE
RPULLUP
1 nF
leakage (Figure 1). An easy way to
measure current over such a large range
(a)
of two to three decades is to charge and
discharge a capacitor and measure the
MICROCONTROLLER
DISCHARGE CYCLE
time or frequency.
A general-purpose I/O pin of a miINPUT
crocontroller charges a capacitor either by using it temporally as an output or by enabling a pull-up resistor,
C
D
which is available in some controllers
1 nF
(Figure 2a). After charging the pin,
DIANE
(b)
you configure it as a high-impedanceedn080807di42932a
(PLACED IN THE 8-21 FOLDER)
input, and a capaciFigure 2 Capacitor C first charges
tor discharges through
through the pull-up resistance of the
the leakage current of
microcontrollers I/O pin configured
the diode (Figure 2b).
as an output (a). The capacitor then
The discharge time
discharges through the reverse leakthen is proportional to
age of diode D1 (b).
the temperature of the
diode; thus, the diode
exhibits exponential
the smaller DIANE
the reverse current and
edn080807di42932b
(PLACED
IN THE
8-21 FOLDER)
behavior. Depending
the
longer
the discharging time. Perion the type of diode, ods longer than a few seconds are usuthe exponential be- ally unsuitable. Making the capacitors
havior can be nearly value too low leads to errors because
ideal. Calibration of the capacitance of any cable and the
a base point is neces- capacitance of the PN-junction diode
sary because the abso- come into effect.
lute value of the curTypically, a power diode, such as a
rent varies greatly at a 1N4001 with a capacitance of 1 nF,
given temperature.
gives suitable results. The discharge
Selecting the diode time is approximately 0.3 to 1 sec at
Figure 1 The reverse current of a PN-junction diode
and the value of the room temperature, falling into the milli
shows an exponential dependency over temperacapacitor requires second range at 1008C. The PN-juncture; increasing the temperature by approximately
some care. The small- tion diode of a power transistor should
12K doubles the leakage.
er the PN junction, also work.EDN
overhead voltage is available for control circuits. A current-mirror architecture is suitable but usually works only
with ICs with well-matched transistors and in which the silicon substrate
holds them at one temperature. However, high currentsapproximately
100 mAare not normally possible. A
thermal runaway can occur in circuits
using unfavorable combinations of discrete bipolar transistors. In this scenario, one LED-driver transistor becomes
designideas
slightly hotter than the others, its gain and cools again toward the ambient and mount all of them on the same
increases, and it takes more current and temperature during the off period. The part of the PCB (printed-circuit
gets even hotter until it self-destructs. thermal-runaway effect does not have board). The supply voltage can be as
This Design Idea shows how you can time to develop.
low as 2.5V for certain LEDs, espeavoid this problem for pulsed-currentThe capacitor prevents transient os- cially infrared types, and the collecmirror applications.
cillations at switch-on or -off. Use the tor current can exceed 100 mA per
The current mirror comprises Q4 same transistor type for Q4 through Q7 LED.EDN
through Q7 with conVCC
nected bases and emitR2
R3
ters, and the collecD1
50
10
1.2V
tor current of Q3 is the
control output (Figure
R1
1). Resistor R 3 con- DRIVE
1k
PNP
Q1
verts Q3s collector curPNP
Q2
LED1
LED2
LED8
LED7
rent to a feedback voltC1
age. Transistors Q1 and
Q2 form a voltage-difference amplifier. The
control-transistor curR4
100 BC817
BC817
BC817
BC817
BC817
rent after feedback is
1.2V/R3, and the LEDs
Q3
Q7
Q4
Q5
Q6
have a similar current.
GND
Because of the pulsed
operationsay, 25%
duty at 3 Hzthe tranFigure 1 A pulsed-current mirror comprising transistors Q4 through Q7 drives multiple LEDs from
sistor temperature does
a low supply voltage.
not reach a stable value
edn080612DI42711
DIANE
designideas
Edited By Martin Rowe
and Fran Granville
Program excelerates
microcomputer-I/O allocation
D Is Inside
54 Microcontroller measures
ter, it helped with the functional allocation and is an elegant and practical
approach for almost any project. The
online version of this article, at www.
edn.com/081215dia, provides a sample
spreadsheet that you can download.
First, you enter all the pins in ascending order (Column A in Figure
1). The LPC2138 can have as many as
four functions per pin. Columns C to
F show the functions and their corresponding pin numbers. Next, you insert the data-validation feature in each
concomitant cell in Column B. When
you click on a cell with this setup, a
circuit runs at 3V
designideas
some statistics on the usage and availability of pins based on the allocation
to allow you to keep tabs on the allocation as it progresses. Cell M101 has
conditional formatting, so it turns red
if the pins you allocate to the microcontroller exceed the total number of
pins available on the microcontroller
as calculated in cell B73. You can add
hardware I/O to the right of the table
to ensure that you include all I/O.
The usage of the spreadsheet takes
place as follows:
1. Delete cells B4 to B67.
2. Delete cells K4 to N87.
3. Create a list of project I/Os and
fill in the I/O-allocation table. Insert rows for additional pins, remembering to update the entries
in columns K and O.
4. Allocate those pins on the microcontroller that you cannot use
for general I/O, such as the JTAG
pins for emulation.
5. Drag down the split-box indicator so that the worksheet appears
something like that in Figure 2.
6. In the upper pane, select the cell
in Column B associated with the
desired pin. Select the configuration from the drop-down box.
7. Go to the project-I/O function
in Column N in the lower pane.
Enter an equals sign and then
click on the desired pin in Column A in the upper pane, scrolling up or down if necessary. The
selected cell reference then fills
into the formula. Complete the
entry with the enter key.
8. Repeat for all the I/O.
9. Drag the split-box indicator back
to the top to remove the screen
split.
Some of the features in Excel can
really make this model shine. For
instance, the pin allocation of the
LPC2138 does not follow the logical
ordering of the pins. Perhaps it would
help to see Port 0 listed in ascending
order. You can use Excels sort feature
to group like functions together.
To see where the information comes
from, click on any entry in Column N,
select the tools menu item, then select auditing and trace precedents.
If you use this procedure with all the
Figure 2 Two panes with the split box allow for easy pin allocation.
Figure 3 The precedent feature lets you verify that you have allocated all the
pins and that each pin has a unique assignment.
designideas
Microcontroller measures
resistance without an ADC
Ashish Aggarwal, Netaji Subash Institute of Technology, Dwarka, India
VREG
IN
VCC
IC2
OUT
GND
TXD
10k
IC1
RXD
4.2V
2 ATTINY13
C1
R1
10 nF
VCC
MIKE
VCC
PB1
PB0
PB2
SENSOR
edn080807di42942 DIANE
(PLACED IN THE 8-21 FOLDER)
designideas
ment, the established magnetic field in L1 collapses, causing
a reverse induced voltage that
makes D1 conduct. The energy in L1 transfers to C2, which
stores the energy until it is sufficient to light up the LEDs.
The relationship between
the supply voltage (VIN), the
inductor (L), its peak current (IPK), and the microcontrollers on time (TON) is VIN5
L3IPK/TON.
For a supply voltage of 3V,
you should select an inductor
with a nominal value of 10 mH
and a saturation current larger
than 1.5A. You can calculate
the microcontrollers on time
as 5 msec. Listing 1, which is
available in the Web version
of this Design Idea, at www.
edn.com/081215dic, uses this
value for the charge pumps
on time. The program in Listing 1 is so simple that it takes
only 22 bytes of the 1-kbyte
3V
C1
22 F
L1
10 H
D1
1N5819
PB2 7
Q1
IC1
ATTINY13 ZTX618
4
DIANE
IPK
TON
IDLE
T
C2
1 F
DIANE