Eliminating Timing Penalty Of

Scan
Guide
Mr.
N.Subbaiah

By
S.Rajesh
13181J5012

Overview
Fundamentals of DFT
Eliminating Timing Penalty of Scan

Fundamentals of DFT

Terminology
Fault Models
Testability Analysis
Ad Hoc Approach
Structured Approach
Scan Architectures

Terminology
Controllability : It is defined as difficulty is
setting a particular signal logic level to 0 or 1 .
Observability : It is defined as difficulty in
observing the state of a particular signal.
Fault Simulation : Evaluating the effectiveness
of a particular pattern set is known as fault
simulation.

Fault Models
Defect : A defect in an electronic design is the
unintended difference between the
implemented hardware and its intended
design.
Error : A wrong signal output generated by a
defective system is called an error. An error is
a effect whose cause is some defect.
Fault Model : A representation of a defect at
an abstract level is known as Fault Modeling.

Fault Models

Stuck-at Faults
Transistor Faults
Transition Faults
Path Faults
Analog Faults

Single Stuck-At Fault Model

Properties of the Fault Model
1. Fault can be at the input or output of the
gate.
2. Fault line is permanently set to 0 or 1 .
3. Only one line is faulty.

Single Stuck-At Fault Model

AND
1
1
0

OR

Why not Multiple Stuck-At Faults.

Usually, several stuck-at faults can be
simultaneously present in the circuit.
A circuit with w nets could have a possible of
3-1 fault combinations i.e, s-a-1, s-a-0, fault
free.
Even a moderate w will result in enormous
number of multiple stuck at faults.

Testability Analysis
This analysis provides a report on how easy is it
to control and observe the nodes.
SCOAP Testability Analysis
Probability-Based Testability Analysis
Simulation-Based Testability Analysis

SCOAP
SCOAP Scandia Controllability and Observability
Analysis Program.
Sequential Measures :
SC0 : Controllability of 0
SC1 : Controllability of 1
SO : Observability of a State

Combinational Measures :
CC0 : Controllability of 0
CC1 : Controllability of 1
CO : Observability of a State

SCOAP
AND
1/1/4

2/3/2

OR

1/1/4
4/2/0

1/1/3
0 Controllability ( CC0 )

1 Controllability ( CC1 )

PI

AND

Min ( input 0 controllabilities ) + 1

( input 1 controllabilities ) + 1

OR

( input 0 controllabilities ) + 1

Min ( input 1 controllabilities ) + 1

Observability ( CO )
PO

AND

( output observability, CC1 of other inputs ) + 1

OR

( output observability, CC0 of other inputs ) + 1

Design for Testability

Ad Hoc
Test Point Insertion
Test logic Insertion

Structured Approach
Scan design

Scan Design
Types of Scan Cells :
Mux Scan
Clocked Scan
Level Sensitive Scan Design

Mux Scan

Scan Architectures
Full Scan
Partial Scan
Random Access Scan

Transition Faults
Fault Model :
0 1 : Slow to Rise
1 0 : Slow to Fall
Number of Stages to Find a fault :
Initialization
Launch of Transition

ATPG for At-Speed Faults

Launch of Capture

ATPG for At-Speed Faults

Launch of Shift

Comparison of LOS and LOC

Comparison of LOS and LOC

LOC
Pattern Generation depends on functional logic of
present path and previous path which results in less
controllability and hence less coverage.
Timing requirements for scan enable is not stringent.

LOS
Pattern Generation does not depend on previous
path logic and is more controllable and more test
coverage.
Timing is stringent for scan enable.

Eliminating Timing Penalty of Scan

Design
Move the scan MUX off the critical path
Additionally, 1 FF and 1 MUX inserted per transformation
Transformation applied on only critical path sinks
MUX delay moved elsewhere
Before transformation
F_out

F_in

S_in

Scan_en

Q S_out

original

S_in

MUX

F_in

MUX

original

Scan_en

F_out

MUX

After transformation

S_out

shadow

Sel_shadow

Performance Improvement
Scan penalty:
MUX-delay + fanout-delay
Performance saving by this approach :
MUX-delay - fanout-delay

Scan Operation : Capture

Sel_Shadow = 1
Scan_en = 0

Scan Operation : First Shift

Sel_Shadow = 0
Scan_en = 1

Scan Operation : Remaining Shifts

Sel_shadow = 1
Scan_en = 1

Experimental Results :
Timing Before inserting Scan
Critical Path Timing

0.013416 ns

Ordinary Mux Scan Design

Critical Path Timing

-0.957568 ns

Critical Path Timing after

compile

-0.743518 ns

Stuck at test Coverage

100 %

Transition Test Coverage

96.80 %

Modified Mux Scan Design

Critical Path Timing

0.002776 ns

Stuck at Test Coverage

99.82 %

Transition Test Coverage

94.23 %

Disadvantages
If source and destination both are critical then
the flop cannot be replaced.
Hence we adopt partial scan, where flops in
timing critical paths are specified as non scan
instances.

Future Work
Implement the design using partial scan and
compare the results.
Generate an efficient test set for partial scan
design.
Implement scan using both partial scan with
modified flop with trade off in coverage and
timing.

References
Scan and atpg process guide by Mentor Graphics.
VLSI Test Principles and Architectures by L.Wang,
C.Wen and X.Wen .
Eliminating the Timing Penalty of Scanby V D Agarwal
and Sinanoglu.
www.wikipedia.org
www.edn.org