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I.
INTRODUCTION
129
V1
V2
Clock
Hold Signal
130
control signal only goes low after the clock goes high,
forcing the AND gate output low. Thus, while the hold
control signal switches asynchronously from high to low at
the end of the scan shift cycle, which loads V1 into the hold
latch, the actual timed control signal sent to the hold latch by
the hold alignment block switches synchronously after the
next active clock edge.
V1
Clock
0
Scan I/P
D- Flip-flop
V2
Hold Latch
Scan enable
Clock
IV.
Hold Signal
During the first part of the scan-in cycle, both the hold and
the timed hold latch control signals are high. Notice,
however, that when the hold is switched low (to logic 0),
the AOI controlled hold latch signal does not respond
immediately; instead it remains latched high while the clock
is low.
From Figure 4 it can be seen that this is because of
feedback from this initial high value, along with the high
inverted clock signal, generates a high (logic 1) at the AND
gate output, which propagates through the OR gate, keeping
the OR output latched high. This high timed hold latch
131
TABLE I.
Circuits
99.72%
98.91%
100%
99.35%
98.81%
98.54%
98.29%
98.24%
99.03%
99.38%
98.54%
98.67%
98.87%
98.70%
99.62%
98.21%
98.57%
99.14%
98.67%
99.38%
99.24%
99.14%
98.23%
98.82%
98.13%
99.53%
S208
S298
S344
S349
S382
S386
S400
S420
S444
S510
S526
S526n
S641
S713
S820
S832
S953
S1196
S1238
S1423
S1488
S1494
S5378
S9234
S13207
S15850
It can be therefore concluded that the DTESFF based designfor-test methodology offers a promising and cost effective
solution to achieving high TDF coverage in a scan based
delay testing environment at the cost of high area overhead.
This can make it viable to use low cost partial enhanced scan
along with the slow hold signal designs discussed in this
paper, particularly in applications where low area overhead
requirement is essential at the cost of fault coverage. Optimal
selection of DTESFF in partial enhance scan design for
significant delay test coverage with lower area overhead
remains an open question and is the subject of our ongoing
research.
VI.
[1]
[2]
[3]
[4]
[5]
V.
CONCLUSION
[6]
[7]
[8]
[9]
[10]
[11]
[12]
132
REFERENCES
[14]
[15]
[16]
[17]
[18]
[19]
[20]
[21]
[22]
[23]
[24]
133