2/21/2015

qrp.gr/coreROM/
Coreropememory
Apracticalguideofhowtobuildyourown.

bySV3ORA

Thisarticlepresentsmyexperiencesindesigningandimplementingacoreropememory.Iamimplementingafunctional70bit
memory(ten7bitswords)fordemonstrationpurposes.
Core rope memory is a magnetic read only memory (ROM). Contrary to ordinary coincidentcurrent magnetic core memory, which
wasusedforRAM,theferritecoresinacoreropearejustusedastransformers,operatingintheirordinarynonsaturation
region. A pulse from a word line wire passing through a given core, is coupled to the bit line wire and interpreted as a
binary"one"whileawordlinewirethatbypassesthecoreisnotcoupledtothebitlinewireandisreadasa"zero".

ToimplementtheROM,firstthesuitabletoroidalcoreswerechosen.IhavechosentheAmidonFT2343coresbecauseoftheir
smallsizetheyaresmall,butnotsosmallsoastobedifficulttowind.Nevertheless,anycorecouldbeused,evenanon
toroidone,sinceanycorecanreassembleatransformer.
The first step in the design, is to measure the voltage that will be induced to the secondary winding, when a pulse comes
intothesingleturnprimary.Ifthevoltageistoolowforyourapplication,thenyoucaneitherincreasethevoltageofthe
inputpulse,orincreasethenumberoftheturnsinthesecondarywinding.Ihavechosenthesecondmethod,soastomakethe
memorymoresensitivetolowervoltageinputpulses.
After some experimentation, I have found 30 turns for the secondary to be an acceptable number, giving an output pulse of
about15Vfromaninputpulseofroughly5V.Dependingonyourapplication,youmayneedtochangethisnumbertosuityour
needs. Also, the size of the winding was not too big, so it was practical to wind on these small cores without too much
effort.

http://qrp.gr/coreROM/

1/6

2/21/2015

qrp.gr/coreROM/

Testing the transformer requires a pulse generator. Remember, transformers are AC devices, meaning that they can operate
eitheroncontinuousACorpulsemode,notDC.Aquickpulsegeneratorcanbeeasilymadeusinga555timer.Suchschematics
arereadilyavailableontheinternetandinthe555datasheet.ThepulsegeneratorIused,wasconnectedtotheprimaryof
thetransformerthrougha100nFcapacitor,tocutanyDCfrompassingontoit.
Initial test above, shows the result of a pulse coming into the primary of the transformer. My scope was triggered on the
falling edge of the pulse first, so the negative pulse is shown first, instead of the positive. For illustration purposes,
the positive pulse will be described first, because in reality the positive pulse occurs first (unless a negative pulse is
sentthrough).
The top trace shows the pulse output from the capacitor of the pulse generator. This pulse is fed into the singleturn
primary of the transformer. The bottom trace shows the pulse out of the secondary of the transformer. A rising edge of the
input positive pulse (from 0 to 5v), causes a positive pulse on the transformer secondary. Then, as long as the pulse peak
staysat5vonthe555,noDCpassesthroughthecapacitorandthereisalsonoAC(orpulse)topassthroughit.Thus,no
voltage is induced at the transformer secondary. Finally when the falling edge of the pulse comes (from 5v back to 0), it
causesanegativepulseonthetransformersecondary.

Toimplementthe7bitwordmemory,sevenidenticaltransformersareneeded.Firstwindthesecondary,whichiscomposedof
30 turns of 0.16mm diameter wire, wound in the direction (polarity or phase) shown in the picture above. The primary is
composedof1turnof0.16mmdiameterwire,woundinthedirectionshowninthepicture.Donotwindtheprimaryyet,asthis
willbedoneduringprogrammingofthememorylateron.Windingsphaseisimportant,sofollowthediagramabove.

http://qrp.gr/coreROM/

2/6

2/21/2015

qrp.gr/coreROM/

Next,asmallpieceofprotoboardcanbeusedtoplacetheseventransformers,asshowninpictureabove.Theorientationof
the transformers was chosen so that coupling between transformers is kept to minimum, in a try to minimize potential noise
fromunwantedtransformercoupling.
Theorientationofthetransformerscanbeeasilylostwhenwindingtheprimaryandalsofromvibrations.Thusasmallamount
ofinstantgluemustbeused,tokeeptheminplace.TheglueholdsthecoreandthesecondarywindingfirmlyontothePCB.

If the memory is to be made modular or used in more than one systems, rows of pins must be used for the I/O connections.
ThesepinsallowforeasyconnectionandremovaloftheROMfromasystem,withouttheneedforsoldering.Furthermore,these
pinsmustbeinstalledinsuitableplaces,sothatextracablingforinterconnectionsiskepttominimum.Agoodexampleis
shownabove.
Followingthepriorprocedure,afunctionalnonprogrammedROMcanbemade.Eventually,aprogramhastobewrittenforit.
Fordemonstrationpurposes,Iwroteasimpleprogramthatlightsupdigitsinasevensegmentdisplay.First,let'sconsider
acommonsevensegmentdisplay.

http://qrp.gr/coreROM/

3/6

2/21/2015

qrp.gr/coreROM/

Each row selection of the memory, must light up a specific digit in the seven segment display. Thus, each row must contain
thenecessarydata,sothattheappropriatesegmentsofthedigitlightup.Accordingtothesevensegmentdisplayabove,a
tablecanbedrawnsothateachmemoryrowcontainslogic"one"wherethesegmentneedstobeonandlogic"zero"wherethe
segmentneedstobeoff.Inthenexttable,logic"one"isrepresentedbydotsandlogic"zero"bytheabsenceofdots.

Nowthatasimpleprogramiswritten,itmustbe"written"intheROMaswell.WritingaprogramintothiskindofROM,means
winding ten wires either through or outside of the appropriate cores. Each time a wire passes through a given core, the
output of this specific transformer reads a binary "one", while each time a wire bypasses a given core, the output of this
transformerreadsabinary"zero".
Tobetterunderstandhowtoprogramthememory,considertheprogramtableaswellasthenextschematicdiagram.Todisplay
digit0onthesevensegmentdisplay,allsegments,apartfromsegmentDelta(Greekletter),havetobeatlogic"one".This
meansthatthewirethatrepresentsdigitzero(whichhasbeenchosentobeat"memoryaddress"zero)mustpassthroughall
cores,exceptfromthe4thcore,thatisconnectedtosegmentDelta.Thisisclearlyshownintheschematicdiagram.Now,you
canfigureouttherestofthedigitsconnectionsbyyourself.

http://qrp.gr/coreROM/

4/6

2/21/2015

qrp.gr/coreROM/

The next picture shows digit 0 (at address zero) programmed into the memory. As explained previously, the wire that
representsthisdigitmustpassthroughallcores,exceptfromthe4th.

Followingthesameprocedure,therestofthewindingsmustbewound.Forthepossibilityofnoisereduction,bypassedwires
arebroughtquitefarfromthebypassedcores,justtomakesurethatnounwantedcouplingwillbemade.

Testingthememoryrequiresapulsegenerator.Remember,transformersareACdevices,meaningthattheycanoperateeitheron
continuous AC or pulse mode, not DC. A quick pulse generator can be easily made using a 555 timer. Such schematics are
readilyavailableontheinternetandinthe555datasheet.ThepulsegeneratorIused,wasconnectedtothememorythrougha

http://qrp.gr/coreROM/

5/6

2/21/2015

qrp.gr/coreROM/

100nFcapacitor,tocutanyDCfrompassingontothememory.
To test the "programmed" memory, a common cathode seven segment display must be connected to it. The appropriate segments
anodes must be connected to the appropriate transformers outputs, as indicated in the schematic diagram. Then, connect the
pulsegeneratoroutputtooneofthetenmemoryaddresses,thatrepresentoneofthetendigits.Theappropriatedigitshould
lightup.Hereisashortvideothatdemonstratesthisoperation.

Asmentionedearlier,thememoryworksonlywithpulses,noDC.Thus,forthesevensegmentdisplaytolightupcontinuously,
the pulse generator must continuously generate pulses, so that the appropriate memory address is periodically selected and
theappropriatedataoutputsareperiodicallyset.IfyourpulsegeneratorfrequencyisaboveafewtensofHz,youreyewill
seethesegmentsastheywerecontinuouslyglowing.
Moretocome...
Backtomainsite

http://qrp.gr/coreROM/

6/6