SENSOR LESS CAPACITOR DETERIORATION

ESTIMATION IN A BUCK CONVERTER USING RIPPLE

VOLTAGE
Introduction
Electrolytic capacitor uses electrolyte as one of its plates and thereby achieving larger
capacitance per unit volume. It has high volumetric efficiency because of its enhanced plate
surface area and very thin dielectric layer. Electrolytic capacitors uses cost efficient case sizes
and are capable of giving high capacitance value and usability at high voltages as shown in Fig 1.
They are widely used in power electronic circuits, filtering circuits, timing networks, by-pass,
coupling and other applications. Electrolytic capacitors are generally reliable, however they are
subjected to age related deterioration and eventual failure.

Fig. 1. Types of capacitors for different voltage and capacitance

Mostly the capacitors will be replaced on periodic basis, when the capacitor deteriorates.
However, within this periodic based maintenance there is the possibility of unexpected shutdown
and failure. Hence, online condition monitoring of electrolytic capacitors is important for critical
high performance applications. Early detection of incipient faults will enable controlled
shutdowns of power converters and thereby reducing the outage time and repairs. Hence, in this
project a cost effective sensor less capacitor deterioration estimation using already deployed
sensors in a synchronous buck converter has been proposed. This project focusses on identifying
ESR and capacitance deterioration in an electrolytic capacitor. This project involves developing
a Simulink model for closed loop synchronous buck converter with cascade controller. The
developed buck converter is simulated for different load, reference voltage and input voltage
condition to study the reliability of the closed loop controller. The feasibility study of different
parameters like duty, output voltage and inductor current of the developed buck converter for
deterioration detection is carried out. Finally, the methodology for capacitance and ESR
deterioration using output ripple voltage has been proposed along with estimation of

deterioration value. The feasibility of implementing the proposed algorithm in online and its pros
and cons has been analyzed and discussed in this project report.

Research scope
The criteria for defining failures in the capacitor involves the following standards,
1. Change in the capacitance (20% to 30%)
2. Change in the tangent of loss angle (1.5 to 3.0 times the initial value)
3. Change in the leakage current (excess of the specified value)
The most common failure in electrolytic capacitor is reduction in the capacitance due to the
evaporation or leakage of electrolyte. The computer motherboards with failed capacitors due to
electrolyte leakage and evaporation are shown in Fig 2. The evaporation may occur due to
sudden surge or long term usage. The reduction in the content of electrolyte increases the ESR
(Equivalent Series Resistance) and decrease in the capacitance value. ESR is also influenced by
corrosion of lead which connects the plates in the capacitor.

Fig. 2. Failed capacitors in computer motherboards

In this project increase in the ESR value and decrease in the capacitance value are considered
for deterioration detection. As the change in the capacitance beyond 20% is easily identifiable,
this research work involves deterioration detection within 10%. It is imperative that, if the
proposed methodology works for 10% for more than 10% it will work. A feasibility study of
capacitor deterioration detection using modulated gate pulse to the switch, capacitor current and
output voltage of the buck converter has been carried out. From the study, it was identified that
output ripple voltage serves as best indicator of change in the capacitor value. Hence output
voltage of the buck converter is used as key signal for condition monitoring of capacitors in buck
converter. As the method is based on pre-existing sensor on buck converter, the methodology can
be adopted only for a particular temperature. The Fig 3 shows the variation of ESR with respect
to temperature and frequency. Hence, at the expense of an extra temperature sensor the reliability
of the proposed methodology can be increased significantly. The prognosis of the capacitor value
is based on the deviation of the dielectric angle in the converter output voltage and the
manufacturer characteristic curve for dielectric angle Vs estimated life remaining. Hence, in this
research work the deviation of dielectric angle with respect to time will be estimated. The
consolidated information of the research scope of this project is given in Table I.

Fig. 3. Variation of capacitance with temperature and frequency

Table I. Research scope of this project

Converter
Control
Constraint
Capacitor deterioration detection
Key signal
Deterioration limit
Prognosis

Buck converter
Voltage and current control
Constant temperature
Increase in ESR and decrease in Capacitance
Output voltage
<10%
Dielectric angle Vs estimated life remaining

Closed loop control of buck converter

The buck converter is designed using the design specification given in Fig 4. The output
capacitor and inductor values are designed as given by equation (1) and (2). Current mode
control is designed to improve the transient performance of the system. The controller is
designed by using the average state equation of the buck converter. The compensator for voltage
loop is designed using the transfer function for

as given by equation (3). The compensator

time constant for voltage loop is designed such that the closed loop system with voltage loop is
underdamped with = 0.2 as given by equation (3). The time constant for the current loop is
determined such that the natural frequency of the current loop is 10 times as that of the voltage
loop. Increase naturally frequency increases the dynamic of the system. The current loop transfer
function and its natural frequency are shown in equation (4). The developed two loop
compensator integrated with the buck converter transfer function and is shown in the Fig 5. The
robustness of the developed two loop compensator is analyzed for different load and reference
voltages and its output voltages and load currents are shown in Fig 6. The controller performance
is studied under open circuit and short circuit conditions. The appropriate current and voltage
waveforms are shown in Fig 7.

Fig. 4. Buck converter and its design specifications

(1)
(2)

(3)
(4)

Fig. 5. Buck converter with cascade control

Fig. 6. Buck converter performance for different loading and output voltage

Fig. 7. Open and short circuit voltage and current of buck converter with cascade control

Methodology for Capacitance deterioration detection

The framework of the methodology is shown in Fig 8. The input to the capacitor deterioration
detection algorithm is the buck converter output voltage. As the capacitor ripple voltage is used
for diagnosis, the output voltage is sampled at low frequency typically

. To avoid the

aliasing effect of switching frequency components and its sidebands, the anti-alias filter is used
before sampling the output voltage. The methodology is based on the Fast Fourier Transform
(FFT), which requires a window of signal as input. Hence, the sampled signal is buffered using a
buffer, the length of the buffer depends on the frequency resolution. Higher frequency resolution
results in higher buffer size. In this research work buffer size is kept at 5

. The samples

stored in the buffer are used for FFT computation. The FFT resolves the input time domain
signal into frequency domain with angle and magnitude information. Hence, the angle and
magnitude information of each frequency component can be easily extracted from FFT. The
switching frequency components magnitude is reduced by the output LC filter in buck converter.

Hence, the dominant frequency component present in the output voltage other than the DC
component will be the ripple component. The magnitude and angle information of this ripple
component is extracted and used as the key indicator for capacitor ESR and capacitance
diagnosis. The angle and magnitude information is used by trend analysis to estimate the ESR
and capacitance deterioration rate. A threshold is fixed for relative change in the ESR and
capacitance angle. Any change in the capacitance or ESR value will cause change in the angle of
the ripple voltage. If the relative change exceeds the threshold value then the corresponding
angle value is recorded with the time information from the real time clock. From the first two
samples of the recorded data, the slope information is calculated and curve fitting is done for the
other time intervals using the previously recorded values. The characteristic curve formed will
give information regarding the percentage change in the capacitance or ESR value with respect
to time. Using this estimated characteristic curve and capacitance change Vs estimated life
remaining curve from manufacturer, the estimated life remaining can be computed and notified.
The methodology can work only for a particular temperature, as the ESR value and capacitance
value will change with respect to temperature. This issue ca be overcome by deploying an extra
temperature sensor and thereby increasing the reliability of the methodology for different
temperature.

Fig. 8. Framework of the methodology for capacitor deterioration detection

Results and discussion

The simulated results of capacitance and deterioration for different percentages with 100% load
is shown in Fig. 9 (a) and (b) respectively. From the frequency spectrum of the output voltage it
can be inferred that the frequency of ripple voltage is 278 Hz. The ripple frequency component
remains the same from 2 to 10% for both capacitor and ESR deterioration. From the Fig 6, it is
evident that the change in the value of capacitance and ESR cause shift in the ripple component
angle with respect to the healthy capacitor. The characteristic curve for capacitance and ESR
deterioration is shown in Fig 9. From the Fig 9, it is clear that capacitance decreases cause the
angle to decrease and vice versa for ESR deterioration. The relative change in the angle is

proportional to the relative change in the capacitance and ESR value. Hence, the deviation of the
ripple component angle is the direct indicator of capacitance and ESR deterioration.

(a) Capacitance deterioration at 100% load

(b) ESR deterioration at 100% load

Fig. 8. Buck converter output voltage and corresponding frequency spectrum

Fig. 9. Variation of ripple voltage angle for capacitance and ESR deterioration

Ripple angel estimation based on curve fitting

Fig. 10. Ripple voltage angle estimation based on linear curve fitting

The Fig 10 shows the estimation curve for ripple voltage angle variation. The variation in angle
value is estimated using the previous two sample points from the point of estimation. The slope
values are then fitted with line equation to form a linear slope. From the Fig 10, it can be seen
that there is a shift between actual and estimated data. This shift is because the first time value (X
value in line equation) is taken as 1 rather than 0. Hence, from the Fig it is clear that the
estimation can be done simply by curve fitting and thereby yielding ripple voltage angle Vs time.
Most manufacturers will provide capacitance or dielectric angle Vs estimated life remaining
characteristics curve in their datasheet. Using the datasheet information and the estimated angle
variation information, the remaining life time can be easily estimated.

Conclusion
A methodology for capacitor deterioration detection in a buck converter has been simulated,
studied and results are discussed. The methodology is able to identify the change in the
capacitance and ESR value as change in the ripple voltage angle. Using the ripple voltage angle,
the estimated deterioration of ripple angle is calculated using simple linear curve fitting. The
generated curve can be used with the manufacturer capacitance or dielectric angle Vs estimated
life remaining characteristics curve to identify the current health condition of the capacitor. The
proposed methodology uses the same DSP used to drive the switch and the sampling frequency
requirement is less than the controller frequency. However, sufficient SRAM size is required for
FFT computation and needs to be integrated with temperature sensor for reliable capacitor
deterioration detection for a wide range of temperature.