BLACKFIN INSTRUCTION SET

Theory

Preface
This part of the course, Blackfin Instruction Set describes in brief about the Instruction Set
of Blackfin which is required for the Course. Students are expected to have a prior
knowledge on the concepts and programming of microprocessors which creates ease in
understanding the topics. For detailed understanding please refer to the Blackfin
Instruction Set provided by Analog Devices. Link for reference is
http://www.analog.com/static/imported-files/processor_manuals/Blackfin_pgr_rev2.2.pdf

Contents
SNo.

Topic

Syntax Terminology

Load

Store

Move

Logical Operations

Arithmetic Operations

Shift Operations

Control Code Bit Management

Bit Operations

10

Program Flow Control

11

Circular Addressing

1. Syntax Terminology
In Blackfin Register Set, there are three primary units using which
Instruction Set is studied.
i.
Data Registers
ii.
Address Registers
iii.
System Registers
In the processor, a word is 32 bit long and half-word is 16 bit long. H
denotes the higher order 16 bits of a 32 bit register and L denotes lower order
16 bits of a 32 bit register. W denotes lower order 32 bits of a 40 bit
accumulator Register and X denotes higher order 8 bits of 40 bit
accumulator.

1.1 Data Registers

(a)

(b)

Data Registers receive operands from the data busses for the
computational units and store the results. There are 8 data registers
i.e. R0, R1, R2 R7 where each register is of 32 bit size. Each Data
Register can be accessed as two 16 bit registers, higher or lower i.e.
R0.H, R1.H, R2.H R7.H (higher 16 bits of a data register) or
R0.L, R1.L, R2.L R7.L (lower 16 bits of a data register).
Accumulator Registers: The processor has two accumulators, A0
and A1. Each accumulator can be accessed as 16 bit low half An.L
or 16 bit high half An.H and its eight bit extension as An.X. Each
can also be referred to as 32 bit lower half register i.e. An.W and 8

bit higher register An.X where n = 0,1. The illustration is shown in

Fig. 1.1

Fig. 1.1

1.2 Address Registers

The Pointer Registers are used as pointers for addressing operations.
There are six pointer registers P0, P1, P2, .. P5. Each pointer register is of
32 bit. Each pointer can also be referred to as two sixteen bit registers i.e.
higher 16 bits as P0.H, P1.H, P2.H, P5.H and lower 16 bits as P0.L,
P1.L, P2.L, P5.L. The 32 bit data present in the memory location
pointer by a P register is denoted as [Pn] and 16 bit data present in the
memory location pointed by a P register is denoted by w[Pn] where n =
0,1, .. 5.
Data Address Registers or Circular buffer registers are Index Registers(I0,
I1, I2, I3) which are used to point a memory location, Length
Registers(L0, L1, L2, L3) which denote the size of the buffer in bytes,
base registers(B0, B1, B2, B3) which denote the starting address in the
buffer and modifier registers(M0, M1, M2, M3) which are used as offsets
for changing the address locations. Index, Length, Base registers are
associative whereas modifier is not.

1.3 System Registers

Loop Counter register, LC0 and LC1 are called the system registers. They
are used in hardware looping to denote the number of times loop is being
executed. At times LT0, LT1 which are loop top addresses and LB0 and
LB1 which are loop bottom addresses are also used in indicating the
starting and ending address of the buffer.
Register File Instruction summary:
(i)
Reg: Any Pointer register(P5-0) or Data register(R7-0)
(ii)
Dreg: R7-0 , Any 32 bit Data Register among R0 to R7
(iii)
Preg: P5-0 , Any Pointer Register among P0 to P5
(iv)
Dreg_hi: R7-0.H , Higher 16 bits of any Data Register
(v)
Dreg_lo: R7-0.L , Lower 16 bits of any Data Register
(vi)
Reg_lo_hi: R7-0.L, P5-0 , 16 bit register high or low. It can be a
Pointer Register or a Data Register
(vii) genreg: R7-0, P5-0, A0.X, A0.W, A1.X, A1.W, Any Data Register
or a Pointer Register or an Accumulator
(viii) dagreg: I3-0, M3-0, B3-0, L3-0, Any Circular buffer Register
(ix)
Dreg_even: R0, R2, R4, R6, Any even Data Register
(x)
Dreg_odd: R1, R3, R5, R7 , Any odd Data Register
(xi)
uimm16:16-bit unsigned field, with a range of 0 through 65,535 i.e.
0 to 2^16-1
(xii) sat_flag : non optional saturation flag, (S)or (NS). Thi sis to
control the overflow
(xiii) imm7 : 7-bit signed field, with the range of 64 through +63 i.e.
-2^6 to 2^6-1
(xiv) uimm4 : 4-bit unsigned field with a range of 0 through 15 i.e. 0 to
2^4-1
(xv) uimm5 : 5-bit unsigned field with a range of 0 through 31 i.e. 0 to
2^5-1

(xvi) imm6 : 6-bit signed field, with a range of 32 through +31 i.e. -2^5
to 2^5-1
(xvii) imm3: 3-bit signed field, with a range of 4 through 3 i.e. -2^2 to
2^2-1
(xviii) uimm3: 3-bit unsigned field, with a range of 0 through 7 i.e. 0 to
2^3-1
(xix) opt_sat : optional (S) (without the quotes) to invoke saturation of
the result. Not optional on versions that show (S) in the
syntax

2. Load Instructions
Load Instructions are used to load any value either a constant or a value from
memory into a register. It can be a Data Register or a Pointer Register.
Following are the types that come under Load Instructions
Load Immediate
Load Data/Pointer Register
Load Half-word zero-extended
Load Half-word sign-extended
Load High/Low Data register Half

2.1 Load Immediate

The Load Immediate instruction loads immediate values, or explicit
constants, into registers. 32 bit registers can be loaded with sign-extended
or zero extended immediate values.
Syntax
Half-word Load:
Reg_lo_hi= uimm16; /*16-bit value into low/high half data or address
register*/
Zero-extended Load:

Reg= uimm16(Z);
/*16-bit value into zero-extended into data or
address
register*/
Sign-extended Load:
Reg= uimm16(X);
/*16-bit value into sign-extended into data or
address
register*/
Examples:
1. Consider a 16 bit number 0XA123
2. Load Half word: P0.l=0XA123
3. Zero-extended:
R0=0XA123(Z) => R0=0X0000A123
4. Sign-extended:
R0=0XA123(X) => R1=0XFFFFA123

2.1 Load Pointer/Data Register

The Load Pointer Register instruction loads a 32-bit P-register with a
32-bit word from an address specified by a P-register.
Syntax
reg=[Preg]; /*indirect*/
Example
P3=[P4];
R6=[P4];

2.2 Load Half-Word Zero Extended

The Load Half-Word Zero-Extended instruction loads 16 bits from a
memory location into the lower half of a 32-bit data register. The
instruction zero-extends the upper half of the register.
Syntax
Dreg=W[Preg](Z);

Example
R5=W[P5](Z);

2.3 Load Half-Word Sign-Extended

The Load Half-WordSign-Extended instruction loads 16 bits signextended from a memory location into a 32-bit data register. The Pointer
register is a P-register. The MSB of the number loaded is replicated in the
whole upper-half word of the destination D-register.
Syntax
Dreg=W[Preg](X);
Example
R5=W[P5](X);

2.4 Load High/Low Data Register Half

The Load High Data Register Half instruction loads 16 bits from a
memory location indicated by an I-register or a P-register into the most
significant half of a 32-bit data register. The operation does not affect the
least significant half.
The Load Low Data Register Half instruction loads 16 bits from a
memory location indicated by an I-register or a P-register into the least
significant half of a 32-bit data register. The operation does not affect the
most significant half of the data register.
Syntax
Dreg_hi=W[Preg];
Dreg_lo=W[Preg];
Example

R7.H=w[p3];
R4.L=w[p4];

3. Store Instructions
Store Instructions are used to store the register values into the memory of
processor

3.1 Store Data/Pointer Registers

The Store Pointer Register instruction stores the contents of a 32-bit P
register to a 32-bit memory location.
The Store Data Register instruction stores the contents of a 32-bit Dregister to a 32-bit memory location. The destination Pointer register can be
a P-register, I-register
Syntax
[Preg]=Preg;
[Preg]=Dreg;
Example
[P4]=P3;
[p4]=r4;

3.2 Store High/Low Data Register

The Store High Data Register Half instruction stores the most
significant 16 bits of a 32-bit data register to a 16-bit memory location.
The Store Low Data Register Half instruction stores the least
significant 16 bits of a 32-bit data register to a 16-bit memory location. The
Pointer register is either an I-register or a P-register.

Syntax
W[Preg]=Dreg_hi;
W[Preg]=Dreg_lo;

Example
W[p4]=r4.h;
W[p4]=r4.l;

4. Move Instructions
Move Instructions are used to move data between any register to another
register

4.1 Move Register

The Move Register instruction copies the contents of the source register
into the destination register. The operation does not affect the source
register contents. All moves from smaller to larger registers are sign
extended.
Syntax
genreg=genreg;
genreg=dagreg;
dagreg=genreg;
dagreg=dagreg;
Example
R4=p2;

4.2 Move Conditional

The Move Conditional instruction moves source register contents into a
destination register, depending on the value of CC.

Syntax
IF CC reg = reg; the move occurs only if CC = 1.
IF ! CC reg = reg ; the move occurs only if CC = 0.

Example
IF CC p4=r3;

4.3 Move Half to Full-Word Zero-Extended

The Move Half to Full Word Zero-Extended instruction converts an
unsigned half word (16 bits) to an unsigned word (32 bits). The
instruction copies the least significant 16 bits from a source register into
the lower half of a 32-bit register and zero-extends the upper half of the
destination register. The operation supports only D-registers. Zero
extension is appropriate for unsigned values. If used with signed values, a
small negative 16-bit value will become a large positive value.
Syntax
Dreg = Dreg_lo (Z) ;
Example
R1=r3.l(z);

4.4 Move Half to Full-Word Sign-Extended

The Move Half to Full Word Sign-Extended instruction converts a signed
half word (16 bits) to a signed word (32 bits). The instruction copies the
least significant 16 bits from a source register into the lower half of a 32-bit
register and sign-extends the upper half of the destination register. The
operation supports only D-registers.
Syntax

Dreg = Dreg_lo (X) ;

Example
R1=r3.l(x);

5. Logical Operations
This chapter discusses the instructions that specify logical operations such
as AND, NOT, OR, exclusive-OR, and bit-wise exclusive-OR
(BXORSHIFT) operations.

5.1 &(AND)
The AND instruction performs a 32-bit, bit-wise logical AND operation
on the two source registers and stores the results into the dest_reg. The
instruction does not implicitly modify the source registers. The dest_reg
and one src_reg can be the same D-register. This would explicitly
modifies the src_reg.
Syntax
Dreg =Dreg &Dreg ;
Example
r4 =r4 &r3 ;

5.2 | (OR)
The OR instruction performs a 32-bit, bit-wise logical OR operation on the
two source registers and stores the results into the dest_reg. The instruction
does not implicitly modify the source registers. The dest_reg and one
src_reg can be the same D-register. This would explicitly modifies the
src_reg.

Syntax
Dreg =Dreg |Dreg ;
Example
r4 =r4 |r3 ;

5.3 ~(NOT ONES COMPLEMENT)

The NOT Ones Complement instruction toggles every bit in the 32-bit
register.
Syntax
Dreg =~Dreg ;
Example
r3 =~r4 ;

5.4 (Exclusive-OR)
The Exclusive-OR (XOR) instruction performs a 32-bit, bit-wise logical
exclusive OR operation on the two source registers and loads the results
into the dest_reg.The XOR instruction does not implicitly modify source
registers. The dest_reg and one src_reg can be the same D-register. This
would explicitly modifies the src_reg.
Syntax
Dreg =Dreg ^ Dreg ;
Example
r4 = r4 ^ r3 ;

6. ARITHMETIC OPERATIONS

Following are the arithmetic operations that are taken advantage

ABS
ADD & SUBTRACT
ADD Immediate
MAC Instructions (Multiplication)
NEGATE
SIGNBITS

6.1 ABS
The Absolute Value instruction calculates the absolute value of a 32-bit
register and stores it into a 32-bit dest_reg according to the following
rules.
Syntax
Dreg =ABS Dreg ;
Examples
r3 =abs r1 ;

6.2 ADD Instructions

The Add instruction adds two source values and places the result in a
destination register.
Syntax
Pointer Registers 32-Bit Operands, 32-Bit Result
Preg =Preg +Preg ;
Data Registers 32-Bit Operands, 32-bit Result
Dreg =Dreg +Dreg ; /*no saturation support but shorter instruction
length */

 Dreg =Dreg +Dreg (sat_flag); /*saturation optionally supported,but at

the cost of longer instruction length */
Data Registers 16-Bit Operands, 16-Bit Result
Dreg_lo_hi =Dreg_lo_hi +Dreg_lo_hi (sat_flag);
Examples
r5 =r2 +r1 ;
p5 =p3 +p0 ;
r4.l =r0.l +r7.h (s);
r0.l =r2.h +r4.l(ns);

6.3 SUBTRACT
The Subtract instruction subtracts src_reg_2 from src_reg_1 and places
the result in a destination register.
Syntax
Dreg = Dreg - Dreg ;
Dreg = Dreg - Dreg (sat_flag) ;
Dreg_lo_hi = Dreg_lo_hi Dreg_lo_hi (sat_flag) ;
Example
r5 = r2 - r1 ; /* 16-bit instruction length subtract, no saturation */
r4.l = r0.l - r7.l (ns) ;
r4.l = r0.l - r7.h (s) ; /* saturate the result */

6.4 ADD Immediate

The Add Immediate instruction adds a constant value to a register
without saturation.
Syntax

Dreg +=imm7 ; /*Dreg =Dreg +constant */

Preg +=imm7 ; /*Preg =Preg +constant */
Ireg +=4 ; /*word address pointer increment */

Examples
p5 +=-4 ; /*decrement by adding a negative value */
i1 +=4 ;

7. MAC Instructions
We will see the following three types of multiplication performed using
MAC0 Or MAC1 unit.
a) Multiply 16-Bit Operands
b) Multiply and Multiply-Accumulate to Accumulator
c) Multiply and Multiply-Accumulate to Half-Register

7.1 MULTIPLY 16-bit Operands

The Multiply 16-Bit Operands instruction multiplies the two 16-bit
operands and stores the result directly into the destination register with
saturation.
Syntax
Multiply-And-Accumulate Unit 0 (MAC0)
Dreg_lo =Dreg_lo_hi *Dreg_lo_hi (opt_mode );
/*16-bit result into the destination lower half-word register */
Dreg_even =Dreg_lo_hi *Dreg_lo_hi (opt_mode ); /*32-bit result */
Multiply-And-Accumulate Unit 1 (MAC1)
Dreg_hi =Dreg_lo_hi *Dreg_lo_hi (opt_mode );
/*16-bit result into the destination upper half-word register */
Dreg_odd =Dreg_lo_hi *Dreg_lo_hi (opt_mode ); /*32-bit result */

Examples
r3.l=r3.h*r2.h ; /*MAC0.Both operands are signed Fractions.*/
r3.h=r6.h*r4.l (fu); /*MAC1.Both operands are unsigned fractions.*/
r6=r3.h*r4.h ; /*MAC0.Signed fraction operands, results saved as 32
bits.*/
Opt_mode:
Default: Signed fraction. Multiply 1.15 x 1.15 to produce 1.31 format data
after shift correction. Sign extend the result to 9.31 format before passing it
to the Accumulator. Saturate the Accumulator after copying or
accumulating to maintain 9.31 precision.
FU: Unsigned fraction. Multiply 0.16 x 0.16 to produce 0.32 format data.
Perform no shift correction. Zero extend the result to 8.32 format before
passing it to the Accumulator. Saturate the Accumulator after copying or
accumulating to maintain 8.32 precision.
IU: Unsigned integer. Multiply 16.0 x 16.0 to produce 32.0 format data.
Perform no shift correction. Zero extend the result to 40.0 format before
passing it to the Accumulator. Saturate the Accumulator after copying or
accumulating to maintain 40.0 precision.
IS: Signed integer. Multiply 16.0 x 16.0 to produce 32.0 format data.
Perform no shift correction. Sign extend the result to 40.0 format before
passing it to the Accumulator. Saturate the Accumulator after copying or
accumulating to maintain 40.0 precision

7.2 Multiply and Multiply-Accumulate to Accumulator

The Multiply and Multiply-Accumulate to Accumulator instruction
multiplies two 16-bit half-word operands. It stores, adds or subtracts
the product into a designated Accumulator with saturation

Syntax
Multiply-And-Accumulate Unit 0 (MAC0) Operations
A0 =Dreg_lo_hi *Dreg_lo_h i(opt_mode); /*multiply and store */
A0 +=Dreg_lo_hi *Dreg_lo_hi (opt_mode ); /*multiply and add */
A0-=Dreg_lo_hi *Dreg_lo_hi (opt_mode ); /*multiply and subtract */
Multiply-And-Accumulate Unit 1 (MAC1) Operations
A1 =Dreg_lo_hi *Dreg_lo_hi (opt_mode); /*multiply and store */
A1 +=Dreg_lo_hi *Dreg_lo_hi (opt_mode ); /*multiply and add */
A1 =Dreg_lo_hi *Dreg_lo_hi (opt_mode ); /*multiply and subtract
*/
Examples
a1+=r6.h*r4.l (fu) ; /* MAC1, only. Both operands are unsigned
fractions. Accumulate into A1 */

7.3 Multiply and Multiply-Accumulate to Half-Register

The Multiply and Multiply-Accumulate to Half-Register instruction
multiplies two 16-bit half-word operands. The instruction stores, adds or
subtracts the product into a designated Accumulator. It then copies 16
bits (saturated at 16 bits) of the Accumulator into a data half-register.
Syntax
Multiply-And-Accumulate Unit 0 (MAC0)
Dreg_lo =(A0 =Dreg_lo_hi *Dreg_lo_hi )(opt_mode );
Dreg_lo =(A0 +=Dreg_lo_hi *Dreg_lo_hi )(opt_mode );
Dreg_lo =(A0 =Dreg_lo_hi *Dreg_lo_hi )(opt_mode );
Multiply-And-Accumulate Unit 1 (MAC1)
Dreg_hi =(A1 =Dreg_lo_hi *Dreg_lo_hi )(opt_mode );
Dreg_hi =(A1 +=Dreg_lo_hi *Dreg_lo_hi )(opt_mode );
Dreg_hi =(A1 =Dreg_lo_hi *Dreg_lo_hi )(opt_mode );

Examples
r5.h=(a1+=r6.h*r4.l)(fu); /*MAC1,only.Both operands are unsigned
fractions. Add the product into A1,then copy to r3.h */

7.3 NEGATE(Twos Complement)

The Negate (Twos Complement) instruction returns the same magnitude
with the opposite arithmetic sign.
Syntax
Dreg = Dreg ;
Example
r5 =-r0 ;

7.4 SIGNBITS
The Sign Bit instruction returns the number of sign bits in a number, and
can be used in conjunction with a shift to normalize numbers. This
instruction can operate on 16-bit, 32-bit, or 40-bit input numbers.
Syntax
Dreg_lo = SIGNBITS Dreg ; /* 32-bit sample */
Dreg_lo = SIGNBITS Dreg_lo_hi ; /* 16-bit sample */
Dreg_lo = SIGNBITS A0 ; /* 40-bit sample */
Example
r2.l = signbits r7 ;
r1.l = signbits r5.l ;

8. SHIFT OPERATIONS
Following are the shift operations that are taken advantage
Arithmetic Shift

 Logical Shift
Rotate

8.1 Arithmetic Shift

The Arithmetic Shift instruction shifts a registered number a specified
distance and direction while preserving the sign of the original number.
The sign bit value back-fills the left-most bit positions vacated by the
arithmetic right shift.
Syntax
Constant Shift Magnitude
Dreg>>>= uimm5; /* arithmetic right shift (a) */
Dreg<<= uimm5; /* logical left shift (a) */
Dreg_lo_hi= Dreg_lo_hi>>> uimm4; /* arithmetic right shift (b) */
Example
r3 >>>= 9 ; /* 16-bit instruction length arithmetic right shift */
r3.l = r0.h >>> 7 ; /* arithmetic right shift, half-word */

8.2 Logical Shift

The Logical Shift instruction logically shifts a register by a specified
distance and direction. Logical shifts discard any bits shifted out of the
register and backfill vacated bits with zeros.
Syntax
Data Shift, Constant Shift Magnitude
Dreg>>= uimm5; /* right shift (a) */
Dreg<<= uimm5; /* left shift (a) */
Dreg_lo_hi= Dreg_lo_hi>> uimm4; /* right shift (b) */
Dreg_lo_hi= Dreg_lo_hi<< uimm4; /* left shift (b) */

Data Shift, Registered Shift Magnitude

Dreg>>= Dreg; /* right shift (a) */
Dreg<<= Dreg; /* left shift (a) */
Dreg_lo_hi= LSHIFT Dreg_lo_hiBY Dreg_lo; /* (b) */
Dreg= LSHIFT DregBY Dreg_lo; /* (b) */
Example
r3 <<= 17 ; /* data left shift */
r3.l = r0.l >> 4 ; /* data right shift, half-word register */

8.3 Rotate
The Rotate instruction rotates a register through the CC bit a specified
distanceand direction. The CC bit is in the rotate chain. Consequently, the
first value rotated into the register is the initial value of the CC bit.
Syntax
Constant Rotate Magnitude
Dreg =ROT Dreg BY imm6 ;
Registered Rotate Magnitude
Dreg = ROT Dreg BY Dreg_lo ;
Examples
r4 =rot r1 by 8 ; /*rotate left */
r4 =rot r1 by -5 ; /*rotate right */
r4 =rot r1 by r2.l ;

9. Control Code Bit Management

These Instructions discuss the affect of CC bit in the ASTAT register and
the operations that can be made using this CC bit.

9.1 Compare Data/Pointer Register

The Compare Data/Pointer Register instruction sets the Control Code
(CC) bit based on a comparison of two values. The input operands are
data/pointer registers.
Note: You cannot compare a pointer register with data register.
A single compare instruction using two register should be same.
Syntax
CC = reg== reg; /* equal, register, signed (a) */
CC = reg== imm3 ; /* equal, immediate, signed (a) */
CC = reg< reg; /* less than, register, signed (a) */
CC = reg< imm3; /* less than, immediate, signed (a) */
CC = reg<= reg; /* less than or equal, register, signed(a) */
CC = reg<= imm3; /* less than or equal, immediate, signed (a) */
CC = reg< reg(IU) ; /* less than, register, unsigned (a) */
CC = reg< uimm3(IU) ; /* less than, immediate, unsigned (a) */
CC = reg<= reg(IU) ; /* less than or equal, register, unsigned (a) */
CC = reg<= uimm3 (IU) ; /* less than or equal, immediate unsigned
(a) */
Examples
cc =r7 ==1 ;
cc =R0 <R3 ;
/*If r0 =0x8FFF FFFF and r3 =0x0000 0001,then the signed operation
produces cc =1,because r0 is treated as a negative value */
cc =p2 <-4 ;
cc =r0 <r3 (iu);
/*If r0 =0x8FFF FFFF and r3 =0x0000 0001,then unsigned
operation produces CC =0,because r0 is treated as a large unsigned
value */

cc =p3 <=2 (iu);

9.2 Move CC
The Move CC instruction moves the status of the Control Code (CC) bit
to and from a data register or arithmetic status bit.
Syntax
Dreg =CC ; /*CC into 32-bitdata register,zero-extended */
CC =Dreg ; /*CC set if the register is non-zero */
Examples
r0 =cc ;
cc =r4 ;

9.3 Negate CC
The Negate CC instruction inverts the logical state of CC
Syntax
CC =!CC ;
Examples
cc =!cc

10. BIT Operations

These Instructions discuss how the bits of a register can be manipulated.

10.1 BITCLR
The Bit Clear instruction clears the bit designated by bit position in the
specified D-register. It does not affect other bits in that register.
Syntax

BITCLR (Dreg ,uimm5 );

Examples
bitclr (r2,3); /*clear bit 3 (the fourth bit from LSB) in R2 */

10.2 BITSET
The Bit Set instruction sets the bit designated by bit_positionin the
specified D-register. It does not affect other bits in the D-register.
Syntax
BITSET (Dreg ,uimm5 );
Examples
bitset (r2,7); /*set bit 7 (the eighth bit from LSB) in R2 */

10.3 BITTGL
The Bit Toggle instruction inverts the bit designated by bit position in the
specified D-register. The instruction does not affect other bits in the Dregister.
Syntax
BITTGL (Dreg ,uimm5 );
Examples
bittgl (r2,24);/*toggle bit 24 (the 25th bit from LSB in R2 */

10.4 BITTST
The Bit Test instruction sets or clears the CCbit, based on the bit designated
by bit position in the specified D-register.

Syntax
CC =BITTST (Dreg ,uimm5 ); /*set CC if bit =1 */
CC =!BITTST (Dreg ,uimm5 ); /*set CC if bit =0 */
Examples
cc =bittst (r7,15); /*test bit 15 TRUE in R7 */

11. PROGRAM FLOW CONTROL

These Instructions discuss about the program flow and how the program
counter is affected.

11.1 Jump
The Jump instruction forces a new value into the Program Counter (PC) to
change program flow
Syntax
JUMP user_label; /* user-defined address label*/
Example
JUMP get_new_sample ; /* assembler resolved target, abstract offsets */

11.2 If CC Jump
The Conditional JUMP instruction forces a new value into the Program
counter (PC) to change the program flow, based on the value of the CC bit
Syntax
IF CC JUMP user_label;
IF !CC JUMP user_label;
Example
IF CC JUMP dest_label;

11.3 LOOP
The Zero-Overhead Loop Setup instruction provides a flexible,counterbased, hardware loop mechanism that provides efficient,zero-overhead
software loops
Syntax
For Loop0
LOOP loop_name LC0=Preg; /*loop_name: A symbolic identifier*/
LOOP_BEGIN loop_name;
LOOP_END loop_name;
For Loop1
LOOP loop_name LC1=Preg;
LOOP_BEGIN loop_name;
/* Place instructions to be executed here*/
LOOP_END loop_name;

12. CIRCULAR ADDRESSING

Index Register
The set of 32-bit registers I0, I1, I2, I3 that normally contain byte addresses
of data structures. Abbreviated I-register or Ireg.
Modify Registers
The set of 32-bit registers M0, M1, M2, M3 that normally contain offset
values that are added or subtracted to one of the Index Registers.
Abbreviated
as Mreg.
Length Registers
The set of 32-bit registers L0, L1, L2, L3 that normally contain the length (in
bytes) of the circular buffer. Abbreviated as Lreg. Clear Lreg to disable
circular addressing for the corresponding Ireg. Example: Clear L3 to disable
circular addressing for I3.
Base Registers
The set of 32-bit registers B0, B1, B2, B3 that normally contain the base
address (in bytes) of the circular buffer. Abbreviated as Breg.
Initializations to be made while declaring an array as a circular buffer:
i0.l= array_name;
i0.h= array_name;
L0= (no of elements in the array*no. of bytes each element is)
b0=i0;