ELEC4602 Notes

Matthew Davis
Semester 2, 2014
The University of New South Wales
Abstract
These summary notes are for Microelectronics Design and Technology (ELEC4602) in
semester 2, 2014. If you find any mistakes, email m.davis@student.unsw.edu.au. More notes
can be found at elsoc.net/notes.php. Note that table numbers, figure numbers, page numbers
and the table of contents are all clickable hyperlinks.

Contents
1 Manufacturing

2 Symbols

3 Transistor Equations
3.1 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Small Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4
5
5

4 Noise
4.1 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 MOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6
6
6

5 Amplifiers
5.1 Common Source . . . . .
5.2 Common Drain Amplifier
5.3 Common Gate . . . . . .
5.4 Differential Pair . . . . . .
6 Op
6.1
6.2
6.3

6.4
6.5
6.6
6.7
6.8

Amps
Gain . . . . . . . . . . .
Output Voltage Range .
Input Voltage Range . .
6.3.1 Minimum . . . .
6.3.2 Maximum . . . .
Slew Rate . . . . . . . .
Transistor Sizing . . . .
Compensation Capacitor
Small Signal Model . . .
Compensation Resistor .

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7
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8
8

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9
10
10
10
10
11
11
11
12
12
14

7 Miller Effect

15

8 Samplers
8.1 Sampling Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Charge Injection and Dummy Switches . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 Offset Cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15
16
16
17

9 Comparators
9.1 Multi-Stage comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2 Latching comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18
19
20

10 D/A and A/D Converters

10.1 Errors . . . . . . . . . . . . . . . . . . . .
10.2 Digital To Analog Converters . . . . . . .
10.2.1 Multiplexed Resistor String . . . .
10.2.2 Binary Weighted Resistor Ladder .
10.2.3 Binary Weighted Capacitor Ladder
10.3 Analog To Digital Converters . . . . . . .
10.3.1 Successive Approximation . . . . .
10.3.2 Algorithmic . . . . . . . . . . . . .
10.3.3 Pipelined Algorithmic . . . . . . .

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21
21
21
21
21
22
23
23
24
25

11 Digital Logic
11.1 Inverter . . . . . .
11.2 Buffers . . . . . . .
11.3 Static CMOS Logic
11.3.1 Propagation
11.3.2 Sizing . . .
11.4 Transmission Gates

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26
26
26
28
28
28
30

12 Flip Flops and Latches

12.1 Transmission Gate Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3 Dynamic Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

31
31
31
31

13 Memory Elements
13.1 Overall Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2 6 Transistor Static Memory Element . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3 Dynamic Memory Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

32
32
33
34

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Delay
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List of Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Capacitances in an NMOS transistor . . . . . . . . .

Small signal model of a transistor . . . . . . . . . . .
T-model of MOS transistor . . . . . . . . . . . . . .
Noise in a MOS transistor . . . . . . . . . . . . . . .
Common Source Amplifiers . . . . . . . . . . . . . .
Common Source Amplifier Small Signal Model . . .
Common Drain Amplifiers . . . . . . . . . . . . . . .
Common drain amplifier equivilant circuit . . . . . .
Common gate amplifier . . . . . . . . . . . . . . . .
Differential Pair . . . . . . . . . . . . . . . . . . . . .
Operational Amplifier . . . . . . . . . . . . . . . . .
Approximate op amp bode plot (without zero) . . .
Small signal model of an op amp (without RC ) . . .
Op amp bode plot including zero, before adding RC
The Miller Effect . . . . . . . . . . . . . . . . . . . .
Basic sampling circuit . . . . . . . . . . . . . . . . .
Sampling jitter . . . . . . . . . . . . . . . . . . . . .
Dummy Switch . . . . . . . . . . . . . . . . . . . . .
Sampling with offset cancellation . . . . . . . . . . .
Basic comparator with offset cancelling . . . . . . . .

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5
5
6
6
7
8
8
9
9
10
11
13
13
14
15
16
16
17
18
18

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

A multi-stage comparator . . . . . . . . . . . .
Simplified latching comparator . . . . . . . . .
Full latching comparator . . . . . . . . . . . . .
ADC/DAC Errors . . . . . . . . . . . . . . . .
Multiplexed Resistor String DAC . . . . . . . .
Resistor binary weighted ladder ADC . . . . .
Capacitor binary weighted ladder ADC . . . .
Successive Approximation ADC . . . . . . . . .
Single stage algorithmic ADC Schematic . . . .
Single stage algorithmic ADC operation . . . .
Pipelined algorithmic ADC (3 bits) . . . . . . .
Inverter . . . . . . . . . . . . . . . . . . . . . .
Inverter transfer function and crowbar current .
String of buffers of increasing size . . . . . . . .
Simple NAND gate and its propagation delay .
Transmission gate . . . . . . . . . . . . . . . .
Flip flop implemented using transmission gates
Dynamic Latch . . . . . . . . . . . . . . . . . .
Overall structure for most memory . . . . . . .
6 transistor static memory . . . . . . . . . . . .

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19
20
21
22
23
23
24
25
25
26
27
28
29
29
30
30
31
32
32
33

The 2 Types of MOS transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables
1

Manufacturing

Annealing: Removes cracks by heating then slowly cooling.

Sputtering: Heat aluminium until it splutters metal onto the chip.

Symbols

Type

Symbols
S

PMOS

NMOS

Select

top of circuit

yes

P-select

bottom of circuit

no

N-select

Inside n-well?

Normal Location

B
S

Table 1: The 2 Types of MOS transistors

The most common symbols are shown in Table 1.
To remember which way around the source and drain are, remember that for NMOS (the normal
one), VDD is the top rail, so the drain is at the top. PMOS is less intuitive than NMOS, so the
opposite is true, and the drain is connected furthest from VDD .
To remember which way around the arrows go, remember that the arrows always point to a N
doped region (this is true of BJTs too).

Transistor Equations

These equations are all in techpar.pdf.

iD =



1
W
k
2
COX
(VGS Vth ) 1 +
vDS
2
L
L
|
{z
}

Saturation drain current

Channel length modulation

iD

W
= COX
L




1
k
(vGS Vth )vDS vDS 2
1+
vDS
2
L
|
{z
}

Triode drain current

Channel length modulation

Vth

p

p
= Vth0 +
|2F vBS | |2F |
{z
}
|

Threshold voltage

Bulk-Source Effect

Where:
VEF F = VGS Vth is the effective voltage
is electron mobility
is the bulk effect parameter

(1)

 COX is the gate capacitance per unit area

Vth is the threshold voltage
Vth0 is the zero bias threshold voltage (threshold voltage with no bulk-source effect)
k = L

3.1

Modes

Saturation mode means the transistor is being used as an analog amplifier

0 < vDS < VEF F = vGS Vth
Triode mode means the transistor is being used as digital switch
vDS > VEF F = vGS Vth

3.2

Small Signal Model

The parasitic capacitances in an NMOS are shown in Figure 1. They look the same in a PMOS.

G
CGS

CGD

D
n+

n+

CSB

CDB

Figure 1: Capacitances in an NMOS transistor

The small signal model is shown in Figure 2.
CGD
G

D
Gm Vgs

CGS

RDS

gm b VBS

S
CSB

CDB

B
Figure 2: Small signal model of a transistor

The values in the small signal model are given by:

ID
W
= COX (VGS Vth )
VGS
L
ID
k ID
=
=
VDS
L
Id
=
VBS

gm =
1
rDS
gmb

(2)

If the bulk terminal is equal to the source terminal, clearly CBS and CDB are shorted, so they
have no effect, so there is no bulk effect, and the left current source can be ignored.
The T-model is another model for MOS transistors which is exactly equivalent to the normal
model. It is shown in Figure 3. Note that no current enters the gate, because the current through
the Is current source is by design equal to the current through the g1m resistor.
D
Is
rds

G
1
gm

Is

Figure 3: T-model of MOS transistor

4
4.1

Noise
Resistors

Noise in a resistor is given by

Vn2R = 4kT R (V2 Hz1 )

4.2

MOS

Figure 4 shows the sources of noise in a MOS transistor.

D

2
Vng
(f )

2
Ind
(f )

G
S

Figure 4: Noise in a MOS transistor

The noises are given by:
2
Ind
(f ) = 4kT
2
Vng
(f ) =

2 1
3 gm

(White Noise)

kf
W LCOX f

Pink Noise

To refer the gate noise to the output, it needs to be multiplied by gm 2 . To refer the drain noise to
the input, it needs to be divided by gm 2 .
Therefore the combined output refered noise of a MOS transistor is:
In2total (f ) =

5
5.1

kf gm 2
2 1
+ 4kT
W LCOX f
3 gm

Amplifiers
Common Source

The most basic common source amplifier has been shown in Figure 5a. Where the output needs
be a voltage (instead of a current), the circuit in Figure 5b can be used instead. Because Vin is
fixed, the PMOS is effectively a resistor, so the circuit is the same as 5a.
Note that the sources are tied to VDD and ground, which is why its a common source amplifier.
The small signal model of the common course amplifier is shown in Figure 6 on the next page. It
has the following properties:
rin =
rout = rds k RL
Vout
= gm (rds k RL ) = gm rout
Av =
Vin
VDD
S
Vin
RL
D
Vout
Ibias

D
Vin

D
Vin

(a) Passive Load (current output)

(b) Active Load (voltage output)

Figure 5: Common Source Amplifiers

5.2

Common Drain Amplifier

The common drain or source follower amplifier is shown in Figure 7 on the following page.
To analyse this circuit, we will use the T-model shown back in Figure 3 on the previous page,
which results in the equivalent circuit shown in Figure 8 on page 9.

Vout
rds

gm Vin

Vin

RL

Figure 6: Common Source Amplifier Small Signal Model

Vin

Vin
Ibias
S

S
D

Vout

Vout

Vbias

RL

S
(a) Passive Load (current output)

(b) Active Load (voltage output)

Figure 7: Common Drain Amplifiers

The common drain amplifier therefore has the following properties:
Av =

rds k rdsb
rds k rdsB + g1m

rout = rdsB k rds k

1
gm

rin =

5.3

Common Gate

The common gate (cascode) amplifier is shown in Figure 9 on the next page.
The common gate amplifier doesnt amplify current or voltage. It simply provides a high input
impedance for the source, and a low output impedance for the load.
The common gate amplifier has the following properties:
iout
=1
iin
rds + RL

gm rds
= rds + Rin gm rds

A=
rin
rout

5.4

Differential Pair

A differential pair can be seen in Figure 10 on page 10.

In a small signal context, each NMOS draws a current which is proportional to the respective input
voltage. The current mirror up top produces a current in the right branch which matches that in

Is
rdsB

Vin
1
gm

Is

Vout
rds

Figure 8: Common drain amplifier equivilant circuit

RL
iout
Vbias
iin

Iin

Rin

Figure 9: Common gate amplifier

the left branch. Current addition at the output node then means that the output current is the
difference between the the two drain currents, which is proportional to the difference between the
input voltages.

rin =
rout = rds1 k rds2
iout = io1 io2 = gm (Vin1 Vin2 )

Op Amps

The schematic of a basic 2 stage op amp has been shown in Figure 11 on page 11.

io1
io1
io2

io1 io2

Vin1

Vin2

Ibias

Figure 10: Differential Pair

6.1

Gain
rout1 = rds2 k rds5

Stage 1 output resistance

rout2 = rds3 k rds8

Stage 2 output resistance

Av1 = gm5 rout1

Stage 1 DC gain

Av2 = gm8 rout2

Stage 2 DC gain

A0 = Av1 Av2 = gm5 rout1 gm8 rout2

6.2

Overall DC gain

Output Voltage Range

In order to operate correctly, each transistor needs to be in saturation. Therefore the output
voltage can swing to within a threshold voltage of the supply rail.
0 + Vth3 Vout VDD Vef f 8
Note that Vef f 6 = Vef f 7 = Vef f 8 = VthP + (VDD Vbias ).

6.3

Input Voltage Range

The op-amp common mode input range is equal to the common mode input range of the differential
pair.
6.3.1

Minimum

If the input voltage is too low VSD4,5  VSG4,5 VthP , so M4 and M5 move into triode mode. To
avoid that happening we need:
VSD4,5 VSG4,5 VthP
VD4,5 > VG4,5 VthP
VG4,5 > VD4,5 VthP
10

M6

Vbias

M7

> |Vef f 7 |

M8

Ibias

M4

M5

V+
CC

VthN ?

Vout
RC

rout2
+

rout1
M1

> |Vef f 8 |

M2

M3

> |Vef f 3 |

Figure 11: Operational Amplifier

For M1 and M2 to remain in saturation, we need VD1,2 > VthN , so VD4,5 > VthN
VG4,5 > VthN VthP
VCMmin = VthN VthP
6.3.2

Maximum

If the input voltages are too high, M4 and M5 will turn off.

6.4

Slew Rate

The drain of M5 remains at an approximately constant voltage. Therefore, if the output voltage
changes very quickly, most of that voltage change will need to also happen across CC . (Were
neglecting RC for now.) The maximum rate of change of the voltage across CC is proportional to
current through M7 (Ibias ). So


 dVout  Ibias
=
max 
dt 
CC

6.5

Transistor Sizing

The op amp in Figure 11 has 7 transistors, so there are 14 parameters to choose. Here is one way
of deciding the dimensions of each transistor:
1. Work out how much power you have available, and hence the available current. You also
need to consider
noise rejection: larger currents means less noise
speed: larger currents means faster circuits
matching: larger currents means better matching
2. Choose your effective voltage

11

3. Choose L (same for all transistors). Shorter means faster, but reduces gain. Choose at least
2 times the minimum length.
4. Choose your widths based on the above.
5. Double check that all saturation currents agree. If this isnt the case, one of the transistors
will go out of saturation.

6.6

Compensation Capacitor

The op amp shown in Figure 11 on the previous page has 2 stages, and therefore 2 poles. Therefore,
if we want to connect this op amp with feedback (which we always do), the system would be
marginally stable, which is not good enough. Thats why we introduce the compensation capacitor
(CC ). It adds a 3rd pole, which is the dominant pole, thereby increasing the phase margin.
For now well ignore RC . It is explained in Section 6.8 on page 14.
Because of the Miller Effect 1 , CC appears much larger to the node between the stages. It is seen
as CC times the gain of the second stage. So Ceq = CC gm3 rout2 .
The dominant pole is given by:
1

1
1
=
rout1 Ceq
rout1 gm3 rout2 CC

Therefore increasing CC will decrease the frequency of the dominant pole, which will increase the
phase margin and increase stability.
The angular gain bandwidth product is given by:
ta A0 1 =

gm5
CC

The transfer function therefore looks like Figure 12 on the following page. Neglecting non-dominant
poles because well only use the op amp within its bandwidth, the transfer function can be approximated by:
A0
A0
A0 1
A(s) =
s =
(3)
1 + s1
s
1
Note that the DC gain becomes infinite with this approximation. This corresponds to the dashed
line in Figure 11 on the previous page.
Equation 3 was an approximation of the transfer function of the op amp. A more accurate model
would include the 2nd pole.
A(s) =

ta


s 1+

s
2

Where ta = A0 1

It can be shown that:

Phase Margin = 90 tan1

t
2

Where t is the point such that |A(t )| = 1. For 2  ta we can approximate t ta .

6.7

Small Signal Model

The small signal model for the op amp in Figure 11 on the previous page is shown in Figure 13 on
the following page.
1 The

Miller effect is described in Section 7 on page 15.

12

|A(s)|

A0
gm5
CC

A(s)

90
Phase Margin
180

Figure 12: Approximate op amp bode plot (without zero)

The gain of the first stage is really gm5 V+ gm4 V , but that is equal to gm5 Vin since gm5 =
gm4 .
At high frequencies CC effectively becomes a short circuit, so Figure 13 becomes a 2 node circuit.
The voltage across the 2nd stage current source becomes Vo1 , so it acts as a resistor of value g1m .
1
We know that gm rds  1, so we can assume gm3
 rout1 + rout2 .Therefore the 2nd pole can be
approximated as:
1
gm3
2
=
(4)
RC
Cout1 + Cout2
This circuit has a zero. To work out its value, set Vout = 0, so the current through rout2 and CD2
CC
Vo1

Vout

Vin

gm5 Vin

rout1

gm3 Vo1

Cout1

rout2

Figure 13: Small signal model of an op amp (without RC )

13

CD2

is zero. Therefore all the current through CC goes through the gm3 Vo1 current source.
gm3 Vo1 =
s0 =

6.8

Vo1
1
s0 CC

gm3
CC

(5)

Compensation Resistor

From equation 5 we see that by putting in the compensation capacitor, we have introduced a zero
in the right half plane (there was previously a zero at infinity).
Looking back at equations 5 and 4 on the preceding page we can figure out where the zero lies
compared to 2 . Cout1 and Cout2 are just parasitic capacitances, and so they are far smaller than
CC . Therefore the zero lies to the left of 2 . Therefore the bode plot in Figure 12 on the previous
page is wrong. It should look like Figure 14, and the transfer function should look like:


s
A0 1 gm3
C
 C

H(s) = 
s
1 + 1
1 + s2

|A(s)|
A0

ta

A(s)

45
90
135
180
225
270
Figure 14: Op amp bode plot including zero, before adding RC
Clearly this is unstable, since the phase angle when the gain is 0dBis almost -270 . This is definitely
unstable.
If a resistor RC is added in series with CC , the zero moves. Looking back to the small signal model
in Figure 13 on the previous page and mentally adding a resistor in series with CC , if we then

14

follow the same working that we used for equation 5 on the preceding page we get:
Vo1
+ RC
1
s0 = 1
gm3 RC

gm3 Vo1 =

1
s0 CC

(6)

1
From equation 6 we see that by varying RC from zero (no resistor) to gm3
, we can move the zero
further from the origin, past 2 to . So we can make the transfer function actually look like
Figure 12 on page 13.
1
then the zero actually moves into the left half plane (s0 < 0). So the
If we choose RC > gm3
transfer function looks like Figure 14 on the previous page, except the phase contribution from the
zero is positive.

Miller Effect

Figure 15 shows the Miller Effect.

When a capacitor is placed across an element with large gain, a small change in the input voltage
results at a large change in voltage at the output. Therefore a small change in input voltage results
in a large change in voltage across the capacitor, which results in a large amount of charge passing
through the capacitor. Capacitance is measured in units of charge per volt, so the input sees a
larger capacitance than just C, it sees C(1 + |(|A)) AC
Similarly the output sees a slightly
smaller
value. The ratio of output voltage to input voltage


1
1
is A , so the output sees C 1 + |A| C. Alternatively, a change in output voltage results
in a small change in input voltage, so the output sees a capacitor of value about C, tied to
ground.
C
Vin
C(1 A)
Vin

Vout
C 1

1
A

Vout

(a) Capacitor across element with gain

(b) Capacitances seen by input and output

Figure 15: The Miller Effect

Samplers

A basic sampling circuit can be seen in Figure 16 on the next page.

When the sampling signal (s ) goes high, the NMOS acts like a closed switch, so CH charges up
to Vin . Then when the sampling signal goes low, the NMOS acts like an open switch, so Vout is
just the voltage across the capacitor, which is the value of Vin at the last falling edge of s .

15

Vin

Vout
CH

Figure 16: Basic sampling circuit

8.1

Sampling Jitter

The device is sampling the input as long as the gate voltage is at least one threshold voltage higher
than the input voltage. s > Vin + VthN . This is quite bad because s has a finite fall time, so
the point at which the transistor turns off depends on the input. This can be seen more clearly in
Figure 17.
V
s
VthN
Vin

VthN
t
error

error

Figure 17: Sampling jitter

When the input voltage is high, it is sampled earlier than we intend2 , and when the input voltage
is low it is sampled later than the ideal spot. This error is called sampling jitter. The way to
minimize this error is to minimize the fall time of the selection signal.

8.2

Charge Injection and Dummy Switches

When the transistor in Figure 16 is on, the total charge sitting in the channel is3
Qch = Cch VEF F = W L COX (VDD Vin VthN )

(7)

The channel charge in an NMOS is negative.

When the transistor is turned off, that charge has to go somewhere. The transistor needs to be
turned off very quickly (for reasons discussed in Section 8.1). So half the charge goes out the drain,
2 Assuming
3 The

magic

we intend to sample when s = 0V.

2
factor which appears in techpar.pdf doesnt appear here because were in the triode (switch) region.
3

16

and half goes out the source. When this charge passes to ground through CH , the voltage across
CH drops. This introduces an error, equal to
1
Qch
Vout = 2
CH

Additionally, the gate-drain overlap capacitance introduces a similar error.

The speed of the sampling circuit is limited by = Ron CH . If we multiply the speed and the
accuracy together we get:
2CH
1
1
=

|Vout |
Qch Ron CH
Subbing in equation 7:
(8)
=
=

2CH

W L COX VEF F

1
1
COX W
L VEF F

CH

2
L2

(9)

Equation 9 tells us that we really want to minimise L in order to get a good sampler. It also
tells us that we cant have both good speed and good accuracy. There is a trade off between the
two.
An effective way to reduce charge injection errors is to add a dummy switch. Figure 18 shows a
sampling circuit with a dummy switch.
s

SD

Vin

SD
VDD
Vout
t

CH

VDD
t

(a) Circuit

(b) Signal timing

Figure 18: Dummy Switch

The timing of the sampling signals is important. Figure 18b shows that the dummy switch signal
(DS ) is an inverted and delayed version of the main signal (s ).
When s goes low, charge is injected through CH into ground, increasing the voltage across CH .
Then after a short delay, SD goes high, so the dummy switch sucks up some charge into its
channel, all4 from ground through CH , which decreases the voltage across CH . If the dummy
switch is half the width of the main switch, and the same length, the charges will approximately
cancel out, so the charge injection error will be drastically reduced.

8.3

Offset Cancellation

Figure 19 on the following page shows an example of a sampling circuit with offset cancellation.
4 The

main switch is now open, so no charge can pass through it.

17

2
s
VDD

Vin

Vin VOS

0V

Vout

VOS

VDD

t
(a) Circuit

(b) Signal timing

Figure 19: Sampling with offset cancellation

When 1 is high, the op amp is configured as a unity gain buffer. Both input terminals are equal,
so V = 0V, so the bottom of the capacitor is at VOS (the offset voltage). Therefore the voltage
across the capacitor is Vin VOS .
When 1 is low and 2 is high, the bottom of the capacitor is connected only to the negative
input of the terminal, which is of infinite impedance. Therefore no current can flow through the
capacitor, so the voltage across it remains Vin VOS . The top right NMOS is on, so the voltage at
the output equals the voltage at the top of the capacitor, which equals (Vin VOS ) + VOS = Vin .
Hence, the offset voltage has not introduced an error.

Comparators

A basic offset-cancelling comparator can be seen in Figure 20.

s
VDD
1
2
Vin
1

VOS

t
+

Vout
VOS

VDD
(a) Circuit

t
(b) Signal timing

Figure 20: Basic comparator with offset cancelling

When 1 is high, the left end of the capacitor is shorted to ground, so the capacitor is charged to
VOS .
When 1 is low and 2 is high, no current can pass through the capacitor, since the right end is
only connected to the negative input of the op amp (which has infinite impedance). Therefore the
voltage across the capacitor remains VOS . The difference in voltage between the op amp input

18

terminals5 (including offset voltage) then becomes (Vin + VOS ) VOS . Assuming infinite gain, the
output is high iff Vin > 0, which is not dependant on offset voltage.

9.1

Multi-Stage comparator

A multi-stage comparator can be seen in Figure 21.

1A1

1A2

1A3
Vout

2
Vin
1

(a) Circuit

1A1
t

1A2

Vd
t

1A3

Vg = Vd

t
Vtipping

use

reset
(b) Signal timing

Vg

(c) Per stage transfer function

Figure 21: A multi-stage comparator

Each of the 3 stages is a common source amplifier. When a gate voltage is high, most of the biasing
current passes through the dependant current source in the small signal model (Figure 2 on 5), so
not much passes through rds , so the drain voltage is low. When the gate voltage is low, most of the
biasing current passes through rds , so the drain voltage is high. Hence, each stage is an inverter
with a transfer function looking like Figure 21c.
During the reset phase, the gate of each NMOS is tied to the drain. This fixes each stage at the
intersection of the dotted line Vg = Vd and the transfer function in Figure 21c (Vg = Vd = Vtipping ).
This is roughly the point of maximum gain. We will call this gain A. The leftmost capacitor is
charged so that the voltage across it equals Vtipping . Similarly, the other two capacitors are charged
such that the input to the respective stage is also Vtipping . In this way all stages are set up to be
at their points of maximum gain. This eliminates offset errors, and maximises speed.
5 Because

there is no feedback when 1 is low, the input terminals arent at the same voltage.

19

Opening the switches between the gate and drain on each stage will cause an error due to charge
injection into the capacitor to the left of that stage. This error will then be amplified by A. The
reason that there is a delay between 1A1 , 1A2 and 1A3 is so that each stage exists reset mode
after the previous. This ensures that the errors from charge injection in the previous stages are
eliminated, since the voltage across the capacitor adapts to the error in such a way that the gate
voltage is still Vtipping . This eliminates each charge injection error, except the last.
The error due to charge injection in the last stage is amplified by A before reaching the output.
In contrast, the input signal is amplified by AN before reaching the last stage (where N is the
number of stages), so this error is negligible.
When 2 goes high, the gate voltage on stage 1 becomes Vin + Vtipping . This means that a slightly
positive or slightly negative value of Vin will result in a very low or very high drain voltage Vd1 .
The gate voltage in stage 2 will therefore be Vd1 + Vtripping , which will result in an extremely high
or extremely low drain voltage Vd2 , and so on for the 3rd stage.
In this way, Vin is amplified by a factor of AN , with negligible errors due to offset and charge
injection.

9.2

Latching comparator

Latching comparators use positive feedback to achieve infinite gain.

A very simple version is shown in Figure 22. Each inverter has a transfer function similar to6
Figure 21c on the preceding page.
If, for example, the left node was at a slightly higher voltage than the right, the bottom inverter
would amplify that different, which would drive down the voltage of the right node. Then the top
inverter would drive up the voltage on the left node even further, and so on.

Figure 22: Simplified latching comparator

This circuit has infinite gain. It could correctly compare any two arbitrarily close voltages (neglecting noise). However it has no inputs and no reset mechanism. This circuit is also very fast, because
the poles are in the right half plane, so the voltage grows exponentially over time (V (t) et/ ),
instead of decaying over time (V (t) et/ ).
A full latching comparator is shown in Figure 23 on the next page.
If we turn on the redNMOS and ignore (turn off) the other coloured components, Figure 23 on the
following page is the same as Figure 22.
The redpart is the reset sub-circuit. When the reset signal is high, the redNMOS turns off, thereby
breaking the feedback. The redPMOS turns on, thereby shorting the drains of the black PMOSs
to VDD . The drains of the black NMOSs fall back to ground, because nothing is keeping them
up.
The bluepart is the circuit which inputs the voltages to be compared. When the reset input goes
low the whole circuit comes out of the reset mode, into the comparison mode. If one of the inputs
is higher than the other, the circuit will become unstable.
6 Replace

Vg with Vin and Vd with Vout .

20

reset

reset

Vinb

Vina

Figure 23: Full latching comparator

Vina and Vinb could be the outputs of a pre-amp.

10

D/A and A/D Converters

Throughout this section, N will refer to the number of bits.

10.1

Errors

Figure 24 on the following page shows the most common types of errors in analog to digital
converters (ADCs) and digital to analog converters (DACs).
essential non-linearity (ENL) is measured using the maximum deviation from the ideal output
(in either direction).
differential non-linearity (DNL) is measured using the maximum deviation in the difference
between 2 outputs (for a DAC) or between 2 inputs which result in different outputs (for a
ADC).
Offset errors can be easily calibrated out. Gain errors are normally not an issue. DNL and ENL
are an issue because they cause a distortion which is very hard to remove.

10.2
10.2.1

Digital To Analog Converters

Multiplexed Resistor String

Figure 25 on page 23 shows a DAC which works by multiplexing the nodes of a voltage divider.
If an actual analog multiplexer is used instead of 2N switches, there are O(log2 (N )) switches, N
signals and 2N 1 resistors. The downside of this structure is that it requires a lot of resistors.
The other downside is that it consumes a lot of static power, compared to capacitor structures (see
Section 10.2.3 on the following page.)
10.2.2

Binary Weighted Resistor Ladder

Figure 26 on page 23 shows a binary weighted resistor ladder ADC.

21

Offset Error
output

output
ideal

ideal

Gain Error

input

input

(a) Gain Error

(b) Offset Error

output

output
Ideal

ideal

Differential
Non-Linearity

Essential
Non-Linearity

DNL
input

input

(c) Essential Non-Linearity

(d) Differential Non-Linearity

Figure 24: ADC/DAC Errors

Each bit of information controls one switch.
This should be analysed using superposition.
For each bit which is a 1, the respective switch is closed and a current passes through the respective
resistor, into the feedback resistor, which creates a voltage at the output. Since the voltage at either
end of the resistor is fixed (when the switch is closed), it is essentially just a current source. The
current is inversely proportional to the resistance, which is 2N i R (where 0 is the most significant
bit (MSB) and N 1 is the least significant bit (LSB)). Hence, the voltage at the output is
proportional to the sum of connected current sources, which is proportional to the sum of 2 to the
power of the bits significance.
The advantages of this system are that it only requires O(log2 (N )) resistors and switches. It
consumes less static power than the resistor string.
Because the value of a resistor is proportional to its area, the binary weighted resistor ladder
requires approximately the same amount of area as the resistor string. (O(2N )).
Note that this configuration is inverting, which is why the resistors are tied to negative Vref .
10.2.3

Binary Weighted Capacitor Ladder

Figure 27 on page 24 shows a binary weighted capacitor ladder ADC.

It is similar to the binary weighted resistor ladder, but it consumes no static power (aside from
the op amp), since capacitors block DC.
The downside is that it is discrete time, since it requires a clock to reset it. During the reset phase,

22

Vref
D3
+
VLSB

R
D2

+
VLSB

Vout

R
D1

+
VLSB

R
D0

Figure 25: Multiplexed Resistor String DAC

D3

D2

D1

MSB
R

Vout

D0

LSB
2R

4R

8R

Vref
Figure 26: Resistor binary weighted ladder ADC
the feedback capacitor7 is shorted, so that it fully discharges to 0V.
After the reset phase, each switch turns on if it corresponds to a 1. That means the respective
capacitor charges up until Vref is across it. To do this, charge passes through the respective
capacitor, which must pass through the feedback capacitor. The more significant bits correspond
to larger capacitors which require more charge to reach Vref . This charge must pass through
the feedback capacitor, which increases its voltage. In this way, after everything has settled, the
voltage at the output equals the voltage across the feedback capacitor, which is proportional to
the sum of 2 to the power of each bit which is a 1.

10.3
10.3.1

Analog To Digital Converters

Successive Approximation

Successive approximation ADCs use a binary search to find the highest value which is less than
or equal to the input. They use a DAC to generate an analog voltage, and then a comparator
7 The

horizontal one.

23

reset

8C

4C

2C

MSB
D3

Vout
+

LSB
D2

D1

D0

Vref
Figure 27: Capacitor binary weighted ladder ADC
compares that to the input.
A high level schematic of this structure can be seen in Figure 28a on the next page.
The operation of this ADC is shown in Figure 28b on the following page. Note that the 2nd
last estimate is closer than the final estimate. However since it is higher than the input, the
comparator outputs a 0, so the successive approximation register saves a 0 into that respective bit.
A workaround for this is to add half an LSB to the input value before comparing it.
10.3.2

Algorithmic

A single stage algorithmic ADC is shown in Figure 29 on the next page.

The input range should be

Vref
2

Vin

Vref
2

For the first clock cycle, the leftmost switch is connects Vin to the sample and hold circuit.
The comparator then outputs a 1 if the input is positive and a zero if the input is negative. This
goes into the shift register as the MSB.
V

If the input to the shift register is a 1 or a 0, ref

is subtracted or added from the output of the
4
sample and hold circuit, respectively. The result is then amplified by a factor of two. The same
process is then repeated N 1 times, with the left switch changing to connect the output of the
amplifier to the sample hold input circuit.
The addition or subtraction and doubling is effectively a binary search. However, whilst the
successive approximation ADC implemented a binary search by changing the approximation, this
device implements it by recursively zooming in on the input. If the input to the sample hold circuit
V
Vref
and double it.
is positive, we know the input is somewhere from 0 to ref
2 . So we subtract
4
Vref
Vref
Vref
Vref
This changes 0Vto 2 , 4 to 0Vand 2 to 2 . We have stretched the window that we
know the input is in, back into the maximum input range of the device. This is how we zoom in
on half the input range.
This algorithm is shown in Figure 30 on page 26.
The resolution of this device is limited by the acuracy of the adder and multiplier.

24

Vin

Sample
Hold

Successive
Approximation
Register

Dout

DAC

Vestimate
(a) Schematic
V
Vin

Vestimate

clock cycles
0

(b) Operation

Figure 28: Successive Approximation ADC

10.3.3

Pipelined Algorithmic

A pipelined algorithmic ADC can be seen in Figure 31 on page 27.

It works in a very similar way to the normal algorithmic ADC. The single algorithmic ADC did the
comparing, addition and doubling using the same hardware, taking one clock cycle per bit. The
pipelined algorithmic ADC is made up of N single algorithmic converters, where the output of the
amplifier feeds into the sample and hold sub-circuit of the next single algorithmic converter.
This structure is N times larger than the simple algorithmic converter. It works at the same speed
per bit (same clock speed), but works on N samples at once, so it can sample once per clock cycle,
whereas the simple one sampled once per N clock cycles. There is a delay of N clock cycles, but
this normally doesnt matter very much.

Vin

Sample
Hold

V+

Shift Register

1
2

+
0

Vref
4

Vref
4

Figure 29: Single stage algorithmic ADC Schematic

25

Dout

V
Vref
2

V+
0V

Vref
2

Clock Cycles
Comparator Output

1
MSB

1
LSB

Figure 30: Single stage algorithmic ADC operation

11
11.1

Digital Logic
Inverter

A basic inverter is shown in Figure 32 on page 28.

The transfer function of this inverter, and the drain current Ix is shown in Figure 33 on page 29.
The drain current is called a crowbar current because the graph of Ix against Vin is shaped like
the slit on the end of a crowbar8 .

11.2

Buffers

Most static CMOS logic cant drive large loads. If we need to drive a large load, we insert a
buffer9 . If we need to drive a really large load, we insert several buffers of increasing size, as
shown in Figure 34 on page 29. The reason we dont use a single huge buffer is because the input
capacitance of the buffer would be large compared to the input capacitance of a small buffer.
If A is too large, then we have the same problem that we get if we just had one huge buffer. If
A is too small, well have heaps of buffers, which will consume lots of space and power and will
increase propagation delays.
As a rule of thumb:

r
A=

CL
3 to 5
Cin

8 Torsten said he didnt know why its called that. The textbook doesnt say, and I cant find anything on the
Internet on it. This is just my guess.
9 An inverter may be used as a buffer, as long as you adjust the logic accordingly.

26

Sample
Hold

Vin

D2 (t) (MSB)

1
2

+
0

Sample
Hold

Vref
4

Vref
4

D1 (t 1)

1
2

+
0

Sample
Hold

Vref
4

Vref
4

D0 (t 2) (LSB)

Figure 31: Pipelined algorithmic ADC (3 bits)

27

Ix
WP
L

Vin

Vout
WN
L

Figure 32: Inverter

11.3
11.3.1

Static CMOS Logic

Propagation Delay

Figure 35a on page 30 shows a basic NAND gate. To calculate the high to low10 propagation delay,
we use the model in Figure 35b on page 30.
Propagation delay is the time difference between when an input has half changed, to when the
output has half changed. To find this, we need to find the time constant seen by Vout in Figure
35b. Calculating this exactly is quite challenging. There is a simple approximation we can make
for circuits of this form. We basically use superposition for each capacitor.

N
X

CDN

n=1

N
X

!
RDSm

m=1

tpd = ln(2)
For the case of N = 3 shown in Figure 35b:
CD1 RDS1
+ CD2 (RDS1 + RDS2 )
+ CD3 (RDS1 + RDS2 + RDS3 )

Low to high propagation delay is calculated the same way. Even if there are parallel branches, we
only calculate the propagation delay for one path at a time (dont add the resistors in parallel).
This is because before the transition, each parallel path would be off (open), and then the input
changes. We assume this change only turns on (shorts) one branch, because if it turned on more,
the logic is not optimised.
11.3.2

Sizing

There are several methods of sizing the transistors in logic gates. All lengths are normally the
minimum length.
If area is your main concern, set all dimensions to minimum.
If speed (propagation delay) is your main concern, size so that the on resistances in each
branch are equal.
10 When

the output goes from high to low.

28

Vout

Vin

VDD

VDD VthP

VIH

VIL

VthN

Ix

Vin

Figure 33: Inverter transfer function and crowbar current

Set all NMOS widths to their minimum
Set all PMOS widths to twice the NMOS minimum (since carrier mobility in PMOS
transistors is half that of NMOS)
Where N transistors appear in series, multiply each of their widths by N .
Where there are N parallel branches, scale one branch so that the total resistance of
each branch is equal.
Where there are N parallel transistors in series with M parallel transistors and M 6= N ,
pick one single path from one end to the other, scale up the width of each transistor
in that path to make the total resistance equal to the unit resistance. Then scale all
the other parallel branches so that the total resistance from one end to the other is the
same regardless of which path you take.

Vin

A2

A3

A4

Cin

CL

Figure 34: String of buffers of increasing size

29

Vout
CD1
Vin1

Vin2

RDS1

Vin3
Vout

Vin1

CD2
RDS2

Vin2
CD3
RDS3
Vin3

(a) Circuit

(b) Model for propagation delays

Figure 35: Simple NAND gate and its propagation delay

Scale every transistor down until the smallest PMOS is equal to the unit PMOS, or the
smallest NMOS is equal to the unit NMOS.

11.4

Transmission Gates

Transmission gates act just like switches. When the enable (EN) signal is high, both the NMOS
and PMOS transistors turn on, shorting the two inputs. When the enable signal is low, they both
turn off, creating an open circuit between the two inputs.
The reason that both and NMOS and PMOS are needed (as opposed to just one) is because the
drain source resistance of an NMOS and PMOS becomes very high at VDD and 0V respectively.
This is because |Vgs | is small, so ID is small11 , so rDS is large12 .
EN

EN

EN

EN

(b) Symbol

(a) Circuit

Figure 36: Transmission gate

11 Refer
12 Refer

back to equation 1 on page 4.

back to equation 2 on page 6.

30

12
12.1

Flip Flops and Latches

Transmission Gate Flip Flop

Flip flops can be made using normal logic gates, as we learnt in ELEC2141. However they can be
made with fewer transistors using transmission gates, as shown in Figure 37.
E

E
Q

E
Q

Vin
E

clk

Figure 37: Flip flop implemented using transmission gates

Each half is just a pair of back to back inverters, which act as a memory element. The loop can
be broken by turning off the top transmission gate in the respective loop.
When the clk signal is low, Egoes high and E goes low. The left half of the flip flop becomes
disconnected from the right half. The input is connected through to the left loop. The left loop
isnt closed, since the top left transmission gate is open.
When clk transitions from low to high, the input is disconnected from the circuit, while the left
loop closes, thereby saving the input state in the left loop. The transmission gate joining the
two loops turns on, thereby propagating the (inverted) input value into the right loop, which is
now opened. Due to the finite propagation delay of each element, a change in the input when clk
transitions from high to low will not result in an erroneous output.

12.2

Timings

Propagation delay is the time between the rising edge of the clock, and a change in the output
Set up time is the time from a change in the input to the rising edge of clk, for the latest change
in input which will successfully propagate to the output that clock edge. This value can be
negative13 .
Hold time is the time from a rising edge of clk to a change in input, for the earliest change in
input which not propagate to the output that clock edge. This value can be negative.
Contamination delay is equal to the minimum propagation delay.

12.3

Dynamic Latch

A dynamic latch is shown in Figure 38 on the following page. This is the smallest memory element
that can be built. It is only 4 transistors.
13 Since the clk signal must first pass through 2 inverters, the clock seen by the flip flop circuit is slightly delayed
to the clock we measure at the input pin. Hence set up time can be negative

31

ON

VX

Q
Cin

ON

Figure 38: Dynamic Latch

When the ON signal is high, the transmission gate turns on, and this circuit simply becomes
an inverter. When the ON signal is low, the parasitic capacitance (Cin ) of the inverter and
transmission gate means that the voltage stays at VX .
However even when the transmission gate is off, a tiny current trickles through the bulk-source
junction of one of the transistors, which slowly charges or discharges the parasitic capacitance.
This causes the value to be corrupted after about 1ms. Consequently, this type of memory needs
to be refreshed frequently.

13
13.1

Memory Elements
Overall Structure

Most random access memory (RAM) and read only memory (ROM) blocks use a structure similar
to the one shown in Figure 39.
Each dotted square is one byte of memory. The 2N +M bytes are arranged in a grid. The N most
significant bits activate the row. The horizontal lines are called word lines, because we activate
the whole row, and throw away the bits we dont care about.

Address

N +M
/

2N Muliplexer

The M least significant bits select the column. For reading, the voltage in the selected bit is
passed down the bit line (vertical line) to then output pin. For writing, the voltage from the I/O
pin passes up the bit line and writes the only enabled cell, which is the selected bit.

2M Muliplexer
I/O

Figure 39: Overall structure for most memory

32

13.2

6 Transistor Static Memory Element

Figure 40 shows a common6 transistor memory structure.

Word Line

read

Data
Figure 40: 6 transistor static memory
The blue parts make up the memory element for a single bit. This is what the blue square in
Figure 39 on the previous page represents. The dotted blue rectangles indicate that this structure
(including the green word line) is repeated many times. The green connections make up the word
line. The red connections and components make up the bit line and the logic at the bottom of
each bit line.
The 4 innermost blue transistors make up two back to back inverters. This is what saves the
bit. The outermost blue NMOS transistors connect the bit and its compliment to the bit line.
They are enabled by the word line. NMOS transistors are only good at transmitting zeros14 , so to
transmit a 1, we transmit a zero to/from the Q side.
When reading (read =1), the red tri-state buffers which are pointing up are disabled (hi impedance
output). If the saved bit is a 0, then the right (true) bit line (red vertical line) is pulled low, and
this value is buffered out onto the Data line with the right downwards pointing tri-state buffer. If
the saved bit is a 1, then the left (complementary) bit line is pulled low, and this value is buffer
out onto the Data line with the downwards pointing inverting tri-state buffer.
14 Due

to a high impedance when transmitting voltages close to their gate voltage

33

When writing (read =0), the downwards pointing tri-state buffers are disabled. The right upwards
pointing tri-state buffer buffers the value of Data onto the right (true) bit line. The left upwards
pointing inverting tri-state buffer buffers the complimentary value of Data onto the left (complimentary) bit line. Whichever bit line is low will transmit a zero through the outermost blue NMOS
into the respective inverter, which will pull either Q or Q low.

13.3

Dynamic Memory Element

Sorry I havent written this bit yet.

Acronyms
ADC analog to digital converter
DAC digital to analog converter
DNL differential non-linearity
ENL essential non-linearity
LSB least significant bit
MSB most significant bit
RAM random access memory
ROM read only memory

About
All the diagrams in this document were drawn in LATEX, using the tikz and circuitikz packages.
Table numbers, figure numbers, page numbers and the table of contents are all clickable hyperlinks.

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